JPH09274566A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the pipeline processing speed of an instruction sequence including a branching instruction by simultaneously executing pipeline information from the instruction next to the branching instruction and the pipeline processing of a branching destination instruction when the branching instruction is inputted to a pipeline. SOLUTION: Two kinds of processing on the D stage of the pipeline are simultaneously executed by a 1st instruction register 15 provided with a decoder, 2nd instruction register 16, 1st branching instruction detection circuit 18 and 2nd branching instruction detection circuit 19. A 1st selector 17 selects the instruction to be supplied to an address adder 6 for operand and an address adder 12 for instruction, and a 2nd selector 20 selects information showing the state of mask field of a conditional branching instruction to be supplied to a branch discrimination circuit 10. Besides, a 3rd selector 21 selects a branching instruction detecting signal to be supplied to an instruction sequence selection circuit 11 and the address adder 12 for instruction. The 1st selector 17, 2nd selector 20 and 3rd selector 21 are controlled by an output 11A of the instruction sequence selection circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline type information processing apparatus, and more particularly to an information processing apparatus capable of processing an instruction string including branch instructions at high speed.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional pipeline type information processing apparatus, and FIGS. 4 and 5 are time charts for explaining the pipeline processing of instruction sequences by the conventional information processing apparatus. Therefore, an information processing apparatus according to the related art will be described below with reference to these drawings. In FIG. 3, 1 is a first instruction buffer register, 2 is a second instruction buffer register, 3 is a selector,
4 is an instruction register, 5 is a branch instruction detection circuit, 6 is an operand address adder, 7 is an operand address modifier, 8 is an operand storage device, 9 is an operation execution unit, 1
0 is a branch determination circuit, 11 is an instruction sequence selection circuit, 12 is an instruction address adder, 13 is an instruction address modifier, and 1
Reference numeral 4 is a memory device for instructions.

An information processing apparatus according to the prior art is configured with functional blocks as shown in FIG. Then, each functional block is configured to have the functions described below.

The first instruction buffer register 1 and the second instruction buffer register 2 are registers that hold instructions in order to enable high-speed access of instructions.
It is used to hold the instruction sequence to be processed on one side and the branch destination instruction read by the branch instruction on the other side. The instruction sequence in each instruction buffer register 1, 2 is cut out to the selector 3 by the instruction cut-out aligner, which is not shown, to be processed next.

The selector 3 has a function of selecting one of the instructions cut out from the first instruction buffer register 1 and the second instruction buffer register 2 and supplying it to the instruction register 4. The instruction register 4 is a register in which the instruction supplied from the selector 3 is stored. The instruction in the instruction register 4 is decoded by a decoder (not shown).

As a first function, the branch instruction detection circuit 5 detects whether the instruction stored in the instruction register 4 is a branch instruction, and outputs a branch instruction detection signal to the instruction sequence selection circuit 1
1 and the instruction address adder 12 are provided. The branch instruction detection circuit 5 has a second function,
A conditional branch instruction that branches to the branch destination address when the instruction stored in the instruction register 4 is a branch instruction and the condition code is set to the state specified by the mask field of the branch instruction. If so, the branch determination circuit 10 has a function of supplying information indicating the state of the mask field of the conditional branch instruction.

The operand address adder 6 determines the operation content according to the instruction stored in the instruction register 4, and the index or base register data supplied from a general-purpose register (not shown) or a part of the instruction register 4 or the like. It has a function of calculating the logical address of the operand using. The operand address modifier 7 has a function of converting the logical address from the operand address adder 6 into a physical address. Operand storage device 8
Has a function of supplying the data specified by the physical address from the operand address modifier 7 to the operation executing unit 9.

The operation execution unit 9 has a function of executing an operation using operand data supplied from an operand storage device 8 and a general-purpose register (not shown), and the executed instruction is an instruction for changing a condition code. In that case, it has a function of determining the condition code from the operation result and supplying the condition code to the branch determination circuit 10.

The branch determination circuit 10 determines whether or not to branch based on the condition code supplied from the operation execution unit 9 and the information indicating the state of the mask field supplied from the branch instruction detection circuit 5. For branching, it has a function of supplying a branch success signal to the instruction sequence selection circuit 11.

The instruction sequence selection circuit 11 has, as a first function, the instruction sequence supplied from the instruction storage device 14 based on the branch instruction detection signal supplied from the branch instruction detection circuit 5 as a first instruction buffer register. It is provided with a function of selecting which of the first and second instruction buffer registers 2 to store. In addition, the instruction sequence selection circuit 11 has a second function of executing the instruction stored in the first instruction buffer register 1 or the second instruction buffer register 2 based on the branch success signal supplied from the branch determination circuit 10. The selector 3 selects a signal for selecting which is supplied to the instruction register 4.
Has a function of supplying to.

When the instruction stored in the instruction register 4 is a branch instruction, the instruction address adder 12 uses an index or base register data supplied from a general-purpose register (not shown) or a part of the instruction register 4. It has a function of calculating a branch destination logical address by using it.

The instruction address modifier 13 converts the logical address from the instruction address adder 12 into a physical address, and the instruction storage device 14 specifies the instruction specified by the physical address from the instruction address modifier 13. Columns
It has a function of supplying the first instruction buffer register 1 and the second instruction buffer register 2.

In an information processing apparatus composed of functional blocks having the above-described functions, the branch instruction detection circuit 5 generally detects the conditional branch instruction described above,
If the condition code that is the basis for determining the branch determination of the conditional branch instruction has not been determined, and whether a branch will occur is not determined, the first instruction buffer register 1, or
At the same time that the processing of reading the branch destination instruction to the second instruction buffer register 2 is executed, the pipeline processing of the instruction next to the conditional branch instruction is executed in advance.

Then, the information processing apparatus determines whether or not a branch occurs by determining the condition code, and if the branch occurs, the first instruction buffer register 1 or the second instruction buffer register. A branch destination instruction is cut out from 2 to the instruction register 4 and pipeline processing is executed.
If no branch occurs, the pipeline processing of the instruction next to the conditional branch instruction, which was previously executed, is continued as it is.

By executing the processing as described above,
The information processing apparatus can execute the instruction next to the conditional branch instruction faster than usual even when the condition code has been determined for a long time and an upper branch does not occur.

This function is usually called a preceding process when the branch decision is undecided. Then, this function does not execute the pipeline processing of the instruction next to the conditional branch instruction in advance when the branch determination is undecided, but by executing the pipeline processing of the branch destination instruction in advance. It is also possible to execute the branch target instruction faster than usual when an upper branch occurs in which the determination of the condition code is long.

Next, with reference to FIG. 4 and FIG. 5, the processing operation when the above-described conventional information processing apparatus processes the conditional branch instruction will be described. In FIGS. 4 and 5, the upper horizontal axis indicates the pipeline execution cycle, and D, Di, A, Ai,
T, Ti, B, Bi, and E represent pipeline stages, and perform the following processes, respectively.

The D stage decodes the instruction stored in the instruction register 4 and refers to a general register (not shown) for operand address generation which is performed in the A stage. When the instruction stored in the instruction register 4 is a branch instruction, the Di stage performs a process of referring to a general register (not shown) for generating a branch destination instruction address, which is performed in the Ai stage.

In the A stage, the contents of a general register (not shown) referred to in the D stage and a part of the instruction register 4 are used to perform a process for obtaining the logical address of the operand by the operand address adder 6. The Ai stage is
If the instruction stored in the instruction register 4 is a branch instruction, D
Contents of a general-purpose register (not shown) referred to in the i stage,
Using a part of the instruction register 4, the instruction address adder 12 performs processing for obtaining the logical address of the branch destination instruction.

In the T stage, the logical address of the operand obtained by the operand address adder 6 in the A stage is converted into a physical address by the operand address modifier 7. If the instruction stored in the instruction register 4 is a branch instruction, the Ti stage receives Ai
At the stage, the instruction address modifier 13 converts the logical address of the branch destination instruction obtained by the instruction address adder 12 into a physical address.

The B stage refers to the operand storage device 8 by the physical address of the operand obtained by the operand address modification device 7 in the T stage,
In the case of an instruction that transfers the operand data to the operation executing unit 9 and uses the data stored in the general-purpose register (not shown) as the operand data, the content of the general-purpose register (not shown) is transferred to the operation executing unit 9. If the instruction stored in the instruction register 4 is a branch instruction, the Bi stage refers to the instruction storage device 14 by the physical address of the branch destination instruction obtained by the instruction address modifier 13 in the Ti stage, and branches to the branch destination. The instruction sequence is transferred to the first instruction buffer register 1 or the second instruction buffer register 2. Then, the branch judgment of the branch instruction is determined,
When the branch is taken or when the pipeline processing of the branch destination instruction is executed in advance by the preceding processing when the branch determination is not determined, the processing of storing the branch destination instruction in the instruction register 4 is performed. . That is, in the above case, the branch destination instruction is input to the pipeline and the D stage is started in the cycle next to the Bi stage of the branch destination instruction.

The E stage uses the operand data previously obtained by the operation executing unit 9 to execute the operation. The operation result is written to a general-purpose register (not shown) or the operand storage device 8 by an instruction. When the instruction is an instruction that changes the condition code, the condition code is determined from the operation result and the condition code is supplied to the branch determination circuit 10. That is, the branch decision of the conditional branch instruction can be determined in the next cycle of the E stage of the instruction that changes the condition code, even if it is the fastest.

Since each stage of the above-mentioned processing can be processed without competition of the logic used, the processing can be executed by overlapping each stage utilizing this.

Next, a description will be given of the preceding processing when the branch determination is undecided in the information processing apparatus according to the prior art.

The time chart shown in FIG. 4 shows a case where the A instruction, the instruction 0, the BC instruction, the instruction 1, the instruction 2, and the instruction 3 are consecutive, the BC instruction branches to the instruction Z, and the branch determination is not made. The pipeline processing when the pipeline processing of the instruction next to the conditional branch instruction is executed prior to the determination will be described. In FIG. 4, the A instruction is an instruction for changing the condition code, and the BC instruction is
It is a conditional branch instruction that branches to the branch destination address when the condition code is set in the state specified by the mask field. Instruction 0, instruction 1, instruction 2, instruction 3, and instruction Z are conditional Without changing the code, and
It is assumed that the instruction is not a branch instruction.

In the information processing apparatus shown in FIG. 3, when the A instruction, the instruction 0, the BC instruction, the instruction 1, the instruction 2, and the instruction 3 are read from the instruction storage device 14 into the first instruction buffer register 1, the instruction string. The selection circuit 11 selects the first instruction buffer register 1, sequentially cuts out the instructions following the A instruction to the instruction register 4, and inputs them into the pipeline. As a result, as shown in FIG. 4, from the first cycle to the sixth cycle, the D stage processing of the A instruction, the instruction 0, the BC instruction, the instruction 1, the instruction 2, and the instruction 3 is sequentially started.

When the BC instruction is detected by the branch instruction detection circuit 5, the process of reading the branch destination instruction is started. When the branch destination instruction Z is read, the instruction Z is
It is stored in the second instruction buffer register 2 by the instruction sequence selection circuit 11. That is, in the third cycle of FIG. 4, the processing of the Di stage that refers to the general-purpose register (not shown) for generating the address of the instruction Z that is the branch destination instruction is started,
Hereinafter, the processing of each stage of Ai, Ti, and Bi as described above is performed. After the completion of these processes, the D stage process of the instruction Z is started in the seventh cycle.

When the operation execution unit 9 completes the operation of the A instruction, the condition code is determined, and the determined condition code is supplied to the branch determination circuit 10 in the fifth cycle. Also,
Information indicating the state of the mask field of the BC instruction is output from the branch instruction detection circuit 5 in the branch determination circuit 10 in the third cycle.
Is supplied to. The branch determination of the BC instruction is determined based on these two pieces of information, and the branch success signal is supplied to the instruction sequence selection circuit 11 in the sixth cycle. When the branch success signal is supplied, the instruction sequence selection circuit 11 causes the selector 3 to select the second instruction buffer register 2. Therefore, the next 7th
In the cycle, the instruction Z is supplied from the second instruction buffer register 2 to the instruction register 4 and input to the pipeline. At this time, at the same time, the pipeline processing of instruction 1, instruction 2, and instruction 3 is canceled.

That is, in the case of the processing shown in FIG. 4, the condition code is determined in the fifth cycle, the branch decision of the BC instruction is determined in the sixth cycle, and the processing of the D stage of the instruction Z is started in the seventh cycle. At the same time, the pipeline processing of instruction 1, instruction 2, and instruction 3 is stopped.

The time chart shown in FIG. 5 shows the A instruction and the B instruction.
When the C instruction, the instruction 0, the instruction 1, the instruction 2, and the instruction 3 are consecutive and the BC instruction branches to the instruction Z, and when the branch determination is undecided, the pipeline of the instruction next to the conditional branch instruction. The processing of the pipeline when the processing is executed in advance is described. The meaning of each instruction in FIG. 5 is the same as the above-mentioned instruction shown in FIG.

In the information processing apparatus of FIG. 3, when an A instruction, a BC instruction, an instruction 0, an instruction 1, an instruction 2, and an instruction 3 are read from the instruction storage device 14 into the first instruction buffer register 1, an instruction string is selected. The circuit 11 selects the first instruction buffer register 1 by the selector 3, sequentially cuts out the instruction following the A instruction to the instruction register 4, and inputs the instruction into the pipeline. As a result, as in the case of FIG. 4, as shown in FIG. 5, from the first cycle to the sixth cycle, the processing of the D stage of the A instruction, BC instruction, instruction 0, instruction 1, instruction 2, and instruction 3 is performed. It will be started sequentially.

When the BC instruction is detected by the branch instruction detection circuit 5, the process of reading the branch destination instruction is started. When the branch destination instruction Z is read, the instruction Z is
It is stored in the second instruction buffer register 2 by the instruction sequence selection circuit 11. That is, in the second cycle of FIG. 5, the processing of the Di stage that refers to the general-purpose register (not shown) for generating the address of the instruction Z that is the branch destination instruction is started,
Hereinafter, the processing of each stage of Ai, Ti, and Bi as described above is performed. However, since the operation of the A instruction is completed in the fifth cycle and the condition code is determined, and the branch determination is determined in the sixth cycle, the processing of the D stage of the instruction Z can be started in the seventh cycle. Becomes At the same time, the pipeline processing of instruction 0, instruction 1, instruction 2, and instruction 3 is stopped in the seventh cycle.

Comparing FIG. 4 and FIG. 5, the instruction Z in FIG.
It is understood that the input to the pipeline (start of the D stage of the instruction Z) is effectively one cycle later than the case of FIG.
This is because the branch decision is decided and the instruction Z is input to the pipeline in the next cycle. In the case of the example shown in FIG.
Since the instruction branch determination is delayed by one cycle, the pipeline injection of the instruction Z is delayed by one cycle. Also,
In this example, even if the decision on the branch decision of the BC instruction is made one cycle before, the processing of two D stages cannot be performed at the same time.
After all it will be delayed by one cycle.

As described above, the conventional information processing apparatus controls so that the branch destination instruction is input to the pipeline after the branch determination is determined.

[0035]

As described above, in the information processing apparatus according to the prior art, after the branch decision is determined,
Since the control is made so that the branch target instruction is input to the pipeline, if the branch determination is delayed, the branch target instruction will inevitably be input to the pipeline too late. There is.

An object of the present invention is to solve the above-mentioned problems of the prior art, to insert a branch target instruction into the pipeline before the branch judgment is determined, and to execute pipeline processing from the instruction next to the branch instruction. An object of the present invention is to provide an information processing apparatus that enables pipeline processing of branch target instructions to be executed at the same time and can improve the processing speed of a pipeline of an instruction sequence including branch instructions.

[0037]

According to the present invention, the object is to provide an instruction buffer means for temporarily holding an instruction sequence sequentially read from a memory, and to sequentially read the instructions held in the instruction buffer means. In a pipeline processing type information processing apparatus that performs processing of each stage of decoding, operand reading, and execution for each instruction, when a branch instruction is input to the pipeline, This is achieved by simultaneously executing the pipeline processing from the instruction and the pipeline processing of the branch destination instruction determined by the branch instruction.

[0038] Further, the object is to provide the information processing device
A plurality of instruction buffer registers as the instruction buffer means, a plurality of instruction registers including a decoder corresponding to the plurality of instruction buffer registers, a plurality of branch instruction detection circuits corresponding to the instruction registers, and the plurality of instruction registers A selector for selecting an instruction from one of the branch instruction detection circuits, a selector for selecting mask field state information of a conditional branch instruction from one of the plurality of branch instruction detection circuits, and one of the plurality of branch instruction detection circuits. And a selector for selecting a branch instruction of the above.

As described above, the present invention provides a means for simultaneously executing the pipeline processing from the instruction next to the branch instruction and the pipeline processing of the branch destination instruction when the branch instruction is input to the pipeline. By providing the instruction to be executed, even if the branch determination is slow, when the branch determination of the branch instruction is determined, the instruction to be executed is pipelined from the instruction next to the branch instruction and the pipeline of the branch destination instruction. It can be selected during the process. Therefore, the present invention can reduce the processing time of an instruction sequence including a branch instruction.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of an information processing apparatus according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a pipeline type information processing apparatus according to an embodiment of the present invention, FIG.
FIG. 4 is a time chart illustrating pipeline processing of an instruction sequence by the information processing device according to the embodiment of the present invention.
In FIG. 1, 15 is a first instruction register, 16 is a second instruction register, 17 is a first selector, 18 is a first branch instruction detection circuit, 19 is a second branch instruction detection circuit, 20 is a second selector, and 21 is It is a third selector, and the other symbols are the same as those in FIG.

The information processing apparatus according to one embodiment of the present invention shown in FIG. 1 detects branch instructions by using first and second instruction registers 15 and 16 instead of the instruction register 4 in the information processing apparatus according to the prior art shown in FIG. First and second instead of the circuit 5
The branch instruction detection circuits 18 and 19 are provided, and the two instruction registers described above and the first, second and third selectors for selecting information from the two branch instruction detection circuits are provided.

In FIG. 1, the first instruction register 15 is
This is a register in which the instruction supplied from the first instruction buffer register 1 is stored. The instruction in the first instruction register 15 is decoded by a decoder (not shown) and supplied to the first selector 17.

The second instruction register 16 is a register in which the instruction supplied from the second instruction buffer register 2 is stored. The instruction in the second instruction register 16 is decoded by a decoder (not shown) and supplied to the first selector 17.

The first selector 17 is connected to the first instruction register 1
5 and the instruction supplied from the second instruction register 16 are selected and supplied to the operand address adder 6 and the instruction address adder 12.

As a first function, the first branch instruction detection circuit 18 detects whether the instruction stored in the first instruction register 15 is a branch instruction, and outputs a branch instruction detection signal to the third instruction.
The second function is provided with a function of supplying the selector 21. As a second function, the instruction stored in the first instruction register 15 is a branch instruction and the condition code is designated by the mask field of the branch instruction. If the conditional branch instruction is to branch to the branch destination address when it is set, it has a function of supplying the second selector 20 with information indicating the state of the mask field of the conditional branch instruction.

As a first function, the second branch instruction detection circuit 19 detects whether the instruction stored in the second instruction register 16 is a branch instruction and outputs a branch instruction detection signal to the third instruction.
The second function is provided with a function of supplying the selector 21. As a second function, the instruction stored in the second instruction register 16 is a branch instruction and the condition code is designated by the mask field of the branch instruction. If the conditional branch instruction is to branch to the branch destination address when it is set, it has a function of supplying the second selector 20 with information indicating the state of the mask field of the conditional branch instruction.

The second selector 20 selects the information indicating the state of the mask field of the conditional branch instruction supplied from the first branch instruction detection circuit 18 and the second branch instruction detection circuit 19 to select the branch determination circuit 10. It has a function to supply to.

The third selector 21 selects the branch instruction detection signal supplied from the first branch instruction detection circuit 18 and the second branch instruction detection circuit 19, and the instruction sequence selection circuit 11 and the instruction address adder 12 are selected. It has a function to supply to.

In the information processing apparatus according to the embodiment of the present invention configured as described above, when a branch instruction is input to the pipeline, the pipeline processing from the instruction next to the branch instruction and the branch destination instruction are executed. By executing pipeline processing at the same time, even if the decision of branch decision is slow,
When the branch judgment of a branch instruction is decided, the instruction to be originally executed can be selected during the pipeline processing from the instruction next to the branch instruction and the pipeline processing of the branch destination instruction. The method will be described below.

The information processing apparatus according to one embodiment of the present invention is provided with two instruction registers (including a decoder (not shown)) and two branch instruction detection circuits, so that two processes of the D stage of the pipeline are executed simultaneously. can do. Then, by selecting the value obtained by the processing of the D stage, it is possible to execute from the A stage of the pipeline of either one of the instructions after the selection.

That is, in the information processing apparatus according to the embodiment of the present invention, the first instruction register 15 and the second instruction register 16, the first branch instruction detection circuit 18 and the second branch instruction detection circuit 19 are used for pipeline D The two stages are executed simultaneously, the first selector 17 is caused to select the instruction to be supplied to the operand address adder 6 and the instruction address adder 12, and the second selector 20 is supplied to the branch determination circuit 10. The third selector 2 selects the information indicating the state of the mask field of the conditional branch instruction.
1, an instruction sequence selection circuit 11 and an instruction address adder 1
The branch instruction detection signal supplied to 2 is selected.
The signal that controls the selection by the first selector 17, the second selector 20, and the third selector 21 is the output 11A of the instruction sequence selection circuit 11, which is the same as the output 11A of the instruction sequence selection circuit 11 described with reference to FIG. belongs to.

Next, the preceding process when the branch determination is undecided in the information processing apparatus according to the embodiment of the present invention will be described with reference to the time chart shown in FIG. The example shown in FIG. 2 shows a pipeline flow when the same instruction sequence as that shown in FIG. 5 is executed under the same condition.

In the information processing apparatus shown in FIG. 1, when the A instruction, the BC instruction, the instruction 0, the instruction 1, the instruction 2, and the instruction 3 are read from the instruction storage device 14 into the first instruction buffer register 1, the instruction string The selection circuit 11 includes the first selector 1
7 selects the first instruction register 15, the second selector 20 selects the first branch instruction detection circuit 18, and the third selector 21 selects the first branch instruction detection circuit 18. The instructions read from the instruction storage device and stored in the first instruction buffer register 1 are sequentially cut out from the A instruction to the first instruction register 15, decoded by a decoder (not shown), and input into the pipeline.

As a result, as shown in FIG. 2, from the first cycle to the sixth cycle, the processing of the D stage of the A instruction, the BC instruction, the instruction 0, the instruction 1, the instruction 2, and the instruction 3 is sequentially started.

When the BC instruction is detected by the first branch instruction detection circuit 18, the process of reading the branch destination instruction is started. Then, the instruction sequence selection circuit 11 stores the instruction Z in the second instruction buffer register 2. When the instruction Z is stored in the second instruction buffer register 2, the instruction Z is supplied to the second instruction register 16 and decoded by a decoder (not shown) in the next sixth cycle. Further, the second branch instruction detection circuit 19 detects whether or not it is a branch instruction.

That is, in the second cycle shown in FIG. 2, the processing of the Di stage for reading the instruction Z, which is the branch destination instruction, is started, and as described above, Ai, Ti,
The processing of Bi is performed, and the processing of the D stage of the instruction Z is performed in the sixth cycle. Then, the operation of the A instruction is completed in the fifth cycle, the condition code is determined, and the branch determination is determined in the sixth cycle. Therefore, the pipeline processing of the instruction Z can be started in the seventh cycle. Become. Then, in one embodiment of the present invention, as described above, the instruction Z
Since the processing of the D stage of is completed in the sixth cycle, the pipeline processing of the instruction Z can be started from the A stage in the seventh cycle. At the same time, the 7th
In the cycle, the pipeline processing of instruction 0, instruction 1, instruction 2, and instruction 3 is canceled.

Comparing the example shown in FIG. 5 according to the prior art with the example according to the embodiment of the present invention shown in FIG. 2, when the processing of the instruction Z which is the branch destination instruction is the embodiment of the present invention, It can be seen that one cycle is completed faster than in the case of.

As described above, according to the embodiment of the present invention, the branch destination instruction is input to the pipeline before the branch determination is determined, and the pipeline processing from the instruction next to the branch instruction and the branch destination instruction are executed. Pipeline processing of
When the branch determination is decided, the instruction to be executed can be selected in the middle of the pipeline processing, so that the processing speed of the pipeline of the instruction sequence including the branch instruction can be improved.

The above-described embodiment of the present invention is a means for executing the pipeline processing from the instruction next to the branch instruction and the pipeline processing of the branch destination instruction at the same time when the branch instruction is input to the pipeline. , D stage processing is executed at the same time.
Not only the processing of the stages, but the processing of each of the A, T, B, and E stages can be executed simultaneously. However, in order to have a configuration in which the processing after the A stage is also executed at the same time, the amount of material that configures the device becomes very large, and in the case where the pipeline processing proceeds without being disturbed, the branch determination is determined. The overhead caused by waiting (indicating the sixth cycle of instruction Z in FIG. 5) is 2
There are relatively few cases that exceed the cycle. Therefore, as in the above-described embodiment of the present invention, the configuration in which only the processing of the D stage is executed simultaneously is the most suitable configuration for efficiently reducing the overhead with the least amount of material. Can be said.

Although the above-described embodiment of the present invention has been described as including two instruction buffer registers, two instruction registers, and two branch instruction detection circuits, the present invention may be configured by providing more of these. . In this case, even when a plurality of branch instructions are included in the instructions being simultaneously processed by the pipeline, the processing of the instruction sequence including those branch instructions can be performed at high speed.

The embodiments of the present invention other than the present invention described in the claims include the following embodiments.

1. An instruction buffer unit for temporarily holding an instruction string sequentially read from the memory is provided, the instructions held in the instruction buffer unit are sequentially read, and processing of each stage of decoding, operand reading, and execution for each instruction is performed. In a pipeline processing type information processing apparatus that overlaps with each other, when a branch instruction is input to the pipeline, the pipeline processing from the instruction next to this branch instruction and the branch destination determined by the branch instruction An information processing apparatus, which executes pipeline processing of instructions at the same time, and selects an instruction to be executed in the middle of pipeline processing when a branch decision is determined.

2. When the pipeline processing from the instruction following the branch instruction and the pipeline processing of the branch destination instruction are being executed at the same time, when the instruction to be originally executed is selected in the middle of the pipeline processing when the branch judgment is decided, 2. The information processing apparatus according to 1, wherein the subsequent pipeline processing is continuously executed.

3. When the pipeline processing from the instruction following the branch instruction and the pipeline processing of the branch target instruction are being executed at the same time, the instruction that becomes unnecessary to be executed at the time of the decision of the branch is processed in the middle of the pipeline processing. The information processing apparatus according to the above 1, wherein the information processing apparatus cancels.

[0066]

As described above, according to the present invention,
When a branch instruction is input to the pipeline, a pipeline of an instruction string including the branch instruction is provided by providing means for simultaneously executing the pipeline processing from the instruction next to the branch instruction and the pipeline processing of the branch destination instruction. The processing speed of can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pipeline type information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating pipeline processing of an instruction sequence by the information processing device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a pipeline type information processing apparatus according to a conventional technique.

FIG. 4 is a time chart for explaining pipeline processing of an instruction sequence by the information processing device according to the related art.

FIG. 5 is a time chart illustrating pipeline processing of an instruction sequence by an information processing device according to the related art.

[Explanation of symbols]

 1 First Instruction Buffer Register 2 Second Instruction Buffer Register 3 Selector 4 Instruction Register 5 Branch Instruction Detection Circuit 6 Operand Address Adder 7 Operand Address Modifier 8 Operand Storage 9 Operation Execution Unit 10 Branch Decision Circuit 11 Instruction Sequence Selection circuit 12 Instruction address adder 13 Instruction address modifier 14 Instruction storage device 15 First instruction register 16 Second instruction register 17 First selector 18 First branch instruction detection circuit 19 Second branch instruction detection circuit 20 Second Selector 21 Third selector

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsukasa Inoue 1 Horiyamashita, Hadano City, Kanagawa Pref., Inside Hitachi Computer Electronics Co., Ltd. Inside the Hitachi Microcomputer System (72) Inventor Akihiro Nakatani 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Hitachi Microcomputer System (72) Inventor Masafumi Hakada 1 Horiyamashita, Hadano, Kanagawa Hitate Works General Computer Division

Claims (2)

[Claims] 1. An instruction buffer means for temporarily holding an instruction sequence sequentially read from a memory, sequentially reading the instructions held in the instruction buffer means, and decoding, operand reading, and executing each instruction. In a pipeline processing type information processing apparatus that performs the processing of each stage of 1), when a branch instruction is input to the pipeline, the pipeline processing from the instruction next to this branch instruction and the branch instruction An information processing apparatus, which executes pipeline processing of a determined branch destination instruction at the same time. 2. An instruction buffer means for temporarily holding an instruction sequence sequentially read from a memory is provided, the instructions held in the instruction buffer means are sequentially read, and decoding, operand reading, and execution for each instruction are performed. In an information processing apparatus of a pipeline processing system that performs the processing of each stage of the above, the plurality of instruction buffer registers as the instruction buffer means and a plurality of instruction registers including a decoder corresponding to the plurality of instruction buffer registers. A plurality of branch instruction detection circuits corresponding to the instruction register, a selector for selecting an instruction from one of the plurality of instruction registers, and a conditional branch instruction from one of the plurality of branch instruction detection circuits. A selector for selecting mask field state information and a branch instruction from one of the plurality of branch instruction detection circuits are selected. When a branch instruction is input to the pipeline, the pipeline processing from the instruction next to this branch instruction and the pipeline processing of the branch destination instruction determined by the branch instruction are executed at the same time. An information processing device characterized by: