JPH09247536A - Mos type solid-state image pickup device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MOS type solid-state image pickup device by which an object to be reproduced is not deformed due to movement of the object in the horizontal direction or the like by reading an electric charge of plural photo diodes simultaneously thereby reducing the time difference of image pickup timing of each picture element, and to provide a method for driving the device. SOLUTION: A unit cell is composed of a photo diode 1, an amplifier transistor(TR) 2, an address capacitor 33, a transfer TR 34, and a detection section 35, the address capacitor 33 is connected between the detection section 35 and a horizontal address and a gate of the transfer TR 34 is connected to a transfer signal line 32. The transfer TR 34 reads signal charges of the photo diode 1 simultaneously from all picture elements and gives them to the detection section 35 and they are stored in the address capacitor 33. Since the signal charge stored in all the photo diodes 1 are simultaneously read in the address capacitor 33 of each unit cell, the time difference in the image pickup timing of each picture element is reduced.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MOS type solid-state imaging device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, various amplification type solid-state imaging devices have been proposed as one of MOS type solid-state imaging devices. This type of solid-state imaging device amplifies a signal voltage due to a signal charge in each pixel, and can improve sensitivity which is a problem when the pixel is miniaturized.

FIG. 5 is a circuit diagram showing an outline of such a MOS type solid-state image pickup device. The address designation method in this MOS type solid-state image pickup device is called an XY sequential address type sensor because the address is sequentially called for each unit cell.

As shown in FIG. 1, this MOS type solid-state image pickup device has a photodiode 1 (1-1-1 to 1-3-3).
3), photodiode 1 (1-1-1 to 1-3-3)
Amplification transistor 2 (2-1-1) that amplifies the detection signal of
2-3-3), a vertical selection transistor 3 (3-1-1 to 3-3-3) for selecting a line from which a signal is read, and a reset transistor 4 (4-1-to reset signal charges).
Unit cells composed of 1 to 4-3-3) are arranged two-dimensionally.

In the figure, the pixels are 3 × 3, but in reality, a larger number of pixels are arranged.
The horizontal address lines 6 (6-1 to 6-3) wired in the horizontal direction from the vertical shift register 5 are connected to the gates of the vertical selection transistors 3 (3-1-1 to 3-3-3), Determine the line to read the signal from.

Similarly, the reset lines 7 (7-1 to 7-3) wired in the horizontal direction from the vertical shift register 5 are connected to the gates of the reset transistors 4 (4-1-1 to 4-3-3). It is connected.

Amplifying transistor 2 (2-1-1 to 2-3)
The source of -3) is the vertical signal line 8 arranged in the column direction.
(8-1 to 8-3). The load transistor 9 is provided at one end of the vertical signal line 8 (8-1 to 8-3).
(9-1 to 9-3) are connected, and a clamp capacitor 10 (10-1 to 10-3), a clamp transistor 11 (11-1 to 11-3), and a sample hold transistor 12 are connected to the other end. (12-1 to 12-3) and the sample hold capacitor 13 (13-1 to 13-3) are connected to the noise removal circuit.

This noise elimination circuit is connected to the horizontal signal line 15 via the horizontal selection transistors 18 (18-1 to 18-3) driven by the selection pulse supplied from the horizontal shift register 14.

FIG. 6 is a timing chart showing the operation of such a MOS type solid-state image pickup device, showing the state of pulses for any three horizontal periods within the vertical effective period.
When the address pulse 21 is applied to the horizontal address line 6-1 within the first horizontal blanking period, the vertical selection transistor 3 (3-1) of the horizontal address line 6-1 is applied.
Only -1 to 3-1-3) are turned on, and the source follower circuit is configured by the amplification transistor 2 and the load transistor 9 on this line.

As a result, the amplification transistor 2 (2-1-
1 to 2-1-3), that is, the same voltage as the photodiode 1 (1-1-1 to 1-1-3) is applied to the vertical signal line 8 (8-1 to 8-3). appear.

At this time, by applying the clamp pulse 22, the clamp transistors 11 (11-1 to 11-11
-3) is turned on and the clamp node 16 (16-1 to 16-1)
6-3) is fixed to the same voltage as the clamp power supply 17.

Next, the clamp transistor 11 (11-
After turning off 1 to 11-3), the reset pulse 23 for setting the reset line to the high level is applied to the reset transistor 4.

Then, the clamp node 16 (16-1 to 16-1
16-3) clamps the difference between the voltage when the clamp power supply 17 has the charges of the photodiode 1 (1-1-1 to 1-1-3) and the voltage when the signal charges are reset. It appears after being added to the voltage of the power supply 17.

Next, the sample hold transistor 1
The sample hold pulse 24 is applied to the gates of 2 (12-1 to 12-3), and the sample hold transistor 1
2 (12-1 to 12-3) is turned on, and this signal voltage is transmitted to the sample hold capacitor 13 (13-1 to 13-3).

The clamp capacitor 10 (10-1 to 10)
-3), the clamp transistor 11 (11-1 to 11-
3), the sample hold transistor 12 (12-1 to 12-1
12-3), sample and hold capacitor 13 (13-1 to 1
3-3) is the amplification transistor 2 (2-1
-1 to 2-3-3) as a noise reduction circuit that reduces the threshold variation.

After that, the horizontal selection pulse 25 (25-1 to 25-1
25-3) is a horizontal selection transistor 18 (18-1 to 1
8-3) in order, and the signals for one line are sequentially taken out from the horizontal signal line 15. By continuing these operations for each line in sequence, the signals of the photodiodes arranged two-dimensionally can be read.

[0017]

However, as described above, in the conventional MOS type solid-state image pickup device, the charge of the photodiode 1 in each unit cell is read out row by row. There is a problem that the signal accumulation timings in the diodes are different.

In particular, there is a big problem that the shape of the subject is distorted and reproduced when the subject is moving in the horizontal direction on the screen. The present invention has been made in view of the above circumstances, and a MOS capable of reducing the time difference of the image pickup timing of each pixel by simultaneously reading out the charges converted by a plurality of photodiodes.
A solid-state imaging device and a method for driving the same are provided.

[0019]

Therefore, first, in order to achieve the above-mentioned object, the invention according to claim 1 is a MOS type solid-state imaging device having a plurality of unit cells, wherein the unit cells are charged with light. Photoelectric conversion means for converting to, a charge holding means for holding the charge output from the photoelectric conversion means,
A first transfer gate that is connected between the photoelectric conversion unit and the charge holding unit and transfers the charge output from the photoelectric conversion unit to the charge holding unit when it is turned on; Voltage output means for outputting a voltage corresponding to the generated charge, and further comprising first control means for simultaneously turning on the first transfer gates of some of the plurality of unit cells. It is characterized by having done.

According to a second aspect of the present invention, in the MOS type solid-state image pickup device according to the first aspect, the unit cell is
Between the charge storage means and the charge storage means, which is connected between the first transfer gate and the charge storage means and stores the charge transferred from the first transfer gate. A second transfer gate that is connected and transfers the electric charge accumulated in the electric charge accumulating means to the electric charge holding means when the electric charge holding means is turned on; and a unit to be read out of the second transfer gate. And second control means for sequentially turning on the second transfer gates of the cells.

Further, in the invention according to claim 3, a photoelectric conversion means for converting light into an electric charge, a charge holding means for holding the electric charge output from the photoelectric conversion means, the photoelectric conversion means and the charge holding means. A first transfer gate which is connected between the charge transfer means and the charge transfer means and transfers the charge output from the photoelectric conversion means to the charge holding means when the charge transfer means is on. And a first control means for simultaneously turning on the first transfer gates of some of the unit cells among the plurality of unit cells. In the method of driving a solid-state image pickup device, the first control means simultaneously turns on the first transfer gates of some of the plurality of unit cells, and the photoelectric conversion means outputs the signals. The charge transferred to the charge holding unit,
The voltage output unit sequentially outputs voltages corresponding to the charges held in the charge holding unit of the unit cell to be read.

Further, the invention according to claim 4 is a photoelectric conversion means for converting light into an electric charge, a charge holding means for holding the electric charge output from the photoelectric conversion means, the photoelectric conversion means and the charge holding means. A first transfer gate which is connected between the charge transfer means and the charge transfer means and transfers the charge output from the photoelectric conversion means to the charge holding means when the charge transfer means is on. Charge output means connected to the first transfer gate and the charge holding means for storing the charge transferred from the first transfer gate, the charge storing means and the charge holding means. Second means connected between the charge storage means and the charge storage means for transferring the charge stored in the charge storage means to the charge holding means
A plurality of unit cells each including a transfer gate, and first control means for simultaneously turning on the first transfer gates of some of the plurality of unit cells; and the second transfer unit. The second unit cell of the gate to be read out
And a second control means for sequentially turning on the transfer gates of 1.
Of the plurality of unit cells by the first control means,
By simultaneously turning on the first transfer gates of some unit cells, the charges output from the photoelectric conversion means are simultaneously transferred to the charge storage means, and the plurality of first transfer gates are turned off. , The second control means sequentially turns on the second transfer gates of the unit cells to be read out of the second transfer gates, so that the charge accumulated in the charge accumulating means is changed to the charge. It is characterized in that the voltage is transferred to the holding means and the voltage output means outputs a voltage corresponding to the charges held in the charge holding means.

Next, the operation of the present invention will be described. In the invention according to claim 1, the first control means simultaneously turns on the first transfer gates of some of the plurality of unit cells, and the charges output from the photoelectric conversion means are transferred to the charge holding means. Since the voltage corresponding to the charge held in the charge holding means is output from the voltage output means, the charges output from the photoelectric conversion means of the plurality of unit cells can be read at the same time. The time difference can be reduced.

The invention according to claim 2 is the M according to claim 1.
In the OS type solid-state imaging device, the first control means simultaneously turns on the first transfer gates of some of the plurality of unit cells, and the charges output from the photoelectric conversion means are stored in the charge storage means. accumulate.

The second control means controls the second unit cell of the second transfer gate, which is the unit cell to be read out.
By sequentially turning on the transfer gates of, the charge accumulated in the charge accumulating means is transferred to the charge retaining means, and the voltage corresponding to the charge transferred to the charge retaining means is output from the voltage output means. The time difference in timing can be reduced.

According to a third aspect of the present invention, the first control means simultaneously turns on the first transfer gates of some of the plurality of unit cells, and charges output from the photoelectric conversion means. To the charge holding means, and the voltages corresponding to the charges held in the charge holding means of the unit cell to be read out by the voltage output means are sequentially output, so that they are output by the photoelectric conversion means of the plurality of unit cells. The charges can be read out at the same time, and as a result, the time difference between imaging timings can be reduced.

According to a fourth aspect of the present invention, the first control means simultaneously turns on the first transfer gates of some of the plurality of unit cells to charge the charges output from the photoelectric conversion means. Store in storage means.

Then, by the second control means, the second transfer gate of the unit cell of the second transfer gate is selected.
By sequentially turning on the transfer gates of, the charge accumulated in the charge accumulating means is transferred to the charge retaining means, and the voltage corresponding to the charge transferred to the charge retaining means is output from the voltage output means. The time difference in timing can be reduced.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a MOS solid-state imaging device according to an embodiment of the present invention. Note that the same parts as those in FIG.

The difference between the MOS type solid-state image pickup device of this embodiment and the conventional MOS type solid-state image pickup device lies in the structure of the basic cell. That is, the unit cell of the MOS type solid-state imaging device of the present embodiment is
The address capacitors 33 (33-1-1 to 33-3-3) are used as the horizontal address lines 6 (6-1 to 6-3) and the gates of the amplification transistors 2 (2-1-1 to 2-3-3). Connect between.

Further, the photodiode 1 (1-1-1 to 1-
1-3-3) and the amplifying transistor 2 (2-1-2-1).
The transfer transistors 34 (34-1-1 to 34-3-3) are connected to the gates of 1-2 to 3-3).

The gate of the transfer transistor 34 is connected to the transfer signal line 32 (32-1 to 32-3). The transfer transistor 34 includes a transfer signal line 32 (3
When a pulse signal is input from 2-1 to 32-3), the charge accumulated in the photodiode 1 (1-1-1 to 1-3-3) is transferred to the address capacitor 33 (33-1-1 to 33). -3
-3) and the detection unit 35 (35-1-1 to 35-3-3).

Detector 35 (35-1-1 to 35-35)
3) is a transfer transistor 34 (34-1-1 to 34-34).
3-3) is a portion for detecting the charge of the phototransistor 1 (1-1-1 to 1-3-3) transferred to the address capacitor 33 as a voltage.

Next, the operation of the MOS type solid-state image pickup device of this embodiment will be described with reference to the timing chart of FIG. The description of the operation of the noise reduction circuit is omitted.

Further, in FIG. 2, the vertical blanking period (V
-BLK) only the final period and the first two horizontal periods are shown. The timing chart of FIG. 2 is 3 × 3.
Although pixels are assumed, there are actually horizontal selection registers for the number of horizontal pixels.

First, in the vertical blanking period V-BLK, the transfer pulses 41 (41-1 to 41-3) are added to all the transfer signal lines 32 (32-1 to 32-3), and all pixels are added. At the same time, the signal charge of the photodiode 1 is detected by the detection unit 35.
The data is read out to (35-1-1 to 35-5-3) and stored in the address capacity 33 (33-1-1 to 33-3-3).

As a result, it is possible to prevent a time difference from occurring in the image pickup timing of each pixel. The method of simultaneously adding the transfer pulse to all the transfer signal lines may be realized by connecting the transfer signal lines to each other to form one transfer signal line, or each transfer signal line 32 (3).
A pulse signal may be simultaneously added to 2-1 to 32-3).

Next, the first horizontal blanking period (H-BL
K) through the horizontal address line 6-1 in the first row,
Address pulse 42-1 to address capacity 33-1-1,
33-1-2 and 33-1-3.

Address capacity 33 (33-1-1 to 33-33)
By applying an address pulse to 1-3),
The potentials of the channels of the amplification transistors 2-1-1 to 2-1-3 increase as compared with the other lines, and the load transistors 9 (9-1 to 9-3) and the amplification transistor 2 (2-1-2-1).
1-2-1-3) constitute a source follower circuit.

Therefore, the photodiode 1 (1-1-1)
The signal charge of (1-1-3) is detected by the detection unit 35 (35-1-1).
.. 35-1-3), a voltage substantially equal to the signal voltage impedance-converted by the clamp capacitor 10 (10-1 to 10).
-3) appears at the end.

Next, in order to sample the "0" level of the signal, a reset pulse 43-1 is applied to the reset line 7-1 of the first row to reset transistor 4 (4-1-).
1-4-1-3) is turned on, the reset gate is opened, and the signal charges of the detection unit 35 (35-1-1 to 35-1-3) are swept out to the drain.

Next, the reset is turned off and the reset level is sampled by the sample hold circuit. next,
In the horizontal valid period, the horizontal shift register 14 sequentially applies horizontal selection pulses 46 (46-1 to 46-3) to the horizontal selection transistors 18 (18-1 to 18-3),
Photodiodes 1-1-1 to 1-1-3 for one line
The output signals of are sequentially output to the horizontal signal line 15.

After sampling the output voltage of the photodiode 1 (1-1-1 to 1-1-3) in the first row in this manner, the second output voltage is similarly sampled within the next horizontal blanking period. By applying the address pulse 41-2 to the horizontal address line 6-2 of the line, the photodiode (1-2-1) of the second line is applied.
１1-2-3) are read out, and output signals are sequentially output to the horizontal signal line 15.

By sequentially repeating the above-described operation for each line, it is possible to read out the signals of all the photodiodes which are two-dimensionally arranged. Therefore,
According to the MOS type solid-state imaging device according to the present embodiment, the charge accumulated in all the photodiodes 1 (1-1-1 to 1-3-3) is transferred to the transfer transistor 34 (34-1-1).
34-3-3), it is possible to read out to the capacitor of each unit cell at the same time, so that it is possible to completely eliminate the time difference of the imaging timing of each pixel.

When the photodiode 1 is a buried type photodiode, depletion of the interface between the photodiode 1 and the silicon substrate can be prevented, and the transfer to the detector 35 is in the complete transfer mode. Therefore, afterimages and random noise can be reduced.

Further, in the above-mentioned embodiments, the reading of the charges of the photodiode is performed at the same time for all pixels. However, it is not limited to the case of reading all the pixels at the same time. May be.

Even if such a method is adopted, the time difference of the image pickup timing of each pixel can be reduced as compared with the conventional MOS solid-state image pickup device. Furthermore, the time from reading the signal to sampling is different between the first column and the last column, and there is concern that noise may increase due to the diffusion current from the substrate, for example. By forming a photodiode in this P well, the size can be made negligibly small.

Further, since a contact to be connected to the gate is formed in the detection section, it is not possible to form an embedded structure, but an embedded diode and a second gate are provided between the first gate and the detection section. If added and accumulated in this diode, the leak current generated at the interface can be further reduced.

FIG. 3 shows an M according to another embodiment of the present invention.
It is a figure which shows the structure of the unit cell of an OS type solid-state imaging device.
The same parts as those in FIG. 1 will be described with the same reference numerals. Although only the configuration of one unit cell is shown here, the same configuration is adopted for the other cells.

That is, the unit cell of the MOS type solid-state image pickup device of the above-mentioned embodiment is different from the unit cell of the MOS type solid-state image pickup device of the present embodiment in that the charge storage diode 51-1-1 and the transfer transistor are different. 52-1-1.

Specifically, the photodiode 1-1-1
The drain of the transfer transistor 52-1-1 is connected to the output side of the. In addition, the transfer transistor 52-1-1
The transfer signal line 53-1-1 is connected to the gate of, and the source of the transfer transistor 52-1-1 is connected to
The input side of the charge storage diode 51-1-1 is connected.

The drain of the transfer transistor 34-1-1 is connected to the output side of the charge storage diode 51-1-1. The transfer signal line 32-1 is connected to the gate of the transfer transistor 34-1-1, and the source of the transfer transistor 34-1-1 has the address capacitor 33-1-1 and the amplification transistor 2-. The gate of 1-1 is connected.

The charge storage diode 51-1-1
Is for accumulating charges transferred from the photodiode 1-1-1 via the transfer transistor 52-1-1.

Further, the charge storage diode 51-1-1
As shown in FIG. 4, the upper part is covered with the shielding layer 54 so that the light from the outside cannot be detected. Both the photodiode 1-1-1 and the charge storage diode 51-1-1 have a buried structure in which the surface is shielded with B ⁺ .

Next, the operation of the MOS type solid-state image pickup device of this embodiment will be described. First, the vertical blanking period V-B
In LK, transfer pulses are applied to all transfer signal lines 53 to open the transfer gates of the transfer transistors 52,
The signal charges of the photodiode 1 are read out at the same time for all pixels and stored in the charge storage diode 51.

As a result, it is possible to prevent a time difference from occurring in the image pickup timing of each pixel. The method of simultaneously adding transfer pulses to all the transfer signal lines 53 is realized by connecting the transfer signal lines 53 to each other to form one transfer signal line, as described in the above embodiment. Alternatively, a pulse signal may be added to each transfer signal line 53 at the same time.

Next, the transfer gate of the transfer transistor 52 is closed. Here, since the photodiode 1 adopts the embedded structure, the signal charges are completely transferred, so that there is no random noise.

Next, within the horizontal blanking period, the transfer signal line 32-1 of the unit cell in the first row to be read out
To the address capacitors 33 (33-1-1 to 33-1-3) by adding a transfer pulse to the signal charges of the photodiodes 1 (1-1-1 to 1-1-3) in the first row. Transfer and store.

Next, within the same horizontal blanking period, the first address pulse is applied via the horizontal address line 6-1 of the first row.
Address capacity 33 of the row (33-1-1 to 33-1-1
3) is applied.

Address capacity 33 (33-1-1 to 33-33)
By applying an address pulse to 1-3),
The potential of the channel of the amplification transistor 2 (2-1-1 to 2-1-3) rises as compared with other lines, and the load transistor 9 (9-1 to 9-3) and the amplification transistor 2 (2
A source follower circuit is formed by -1 to 2-1 to 3).

Therefore, the photodiode 1 (1-1-1)
The signal charge of (1-1-3) is detected by the detection unit 35 (35-1-1).
.. 35-1-3), a voltage substantially equal to the signal voltage impedance-converted by the clamp capacitor 10 (10-1 to 10).
-3) appears at the end.

At this time, by applying the clamp pulse 44, the clamp transistors 11 (11-1 to 11-11
-3) is turned on and the clamp node 16 (16-1 to 16-1)
6-3) is fixed to the same voltage as the clamp power supply 17.

Next, the clamp transistor 11 (11-
After turning off 1 to 11-3), a reset pulse 43-1 for setting the reset line 7-1 to a high level is applied to the reset transistors 4 (4-1-1 to 4-1-3).

Next, in order to sample the "0" level of the signal, the reset pulse 43-1 is applied to the reset line 7-1 of the first row, and the reset transistor 4 (4-1-
1-4-1-3) is turned on, the reset gate is opened, and the signal charges of the detection unit 35 (35-1-1 to 35-1-3) are swept out to the drain.

Then, the horizontal selection pulse 46 (46-1 to 46-3) is sequentially applied to the horizontal selection transistors 18 (18-1 to 18-3) by the horizontal shift register 14, and the photodiode 1-for one line 1- 1-1 to 1-1
-3 output signals are sequentially output to the horizontal signal line 15.

After the output voltage of the photodiode 1 (1-1-1 to 1-1-3) in the first row is sampled in this manner, the horizontal address line 6- of the second line is similarly sampled.
The address pulse 41-2 is applied to 2 to read out the signal charges of the photodiodes (1-2-1 to 1-2-3) of the second line, and output signals are sequentially output to the horizontal signal line 15.

By repeating the above-described operation for each line in sequence, it is possible to read out the signals of all the two-dimensionally arranged photodiodes. Therefore, according to the MOS type solid-state imaging device according to the present embodiment, since there is a temporary storage unit in addition to the photodiode,
The reset level can be sampled first and then the signal level. Therefore, it is possible to reduce random noise generated by the detection unit potential being crossed by the thermal noise of the reset transistor.

The transfer transistor 34 (34-1-
1-34-3-3), the photodiode 1 (1-1
-1 to 1-3-3) to the charge storage diode 51 (5
The method of accumulating charges in 1-1-1 to 51-3-3) is not limited to the case of simultaneously reading out all pixels, and may be performed simultaneously in two or more rows.

[0069]

As described above in detail, according to the present invention,
By simultaneously reading the charges converted by the plurality of photodiodes, it is possible to reduce the time difference between the image pickup timings of the pixels.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a MOS solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the MOS type solid-state imaging device according to the same embodiment.

FIG. 3 is a diagram showing a configuration of a unit cell of a MOS type solid-state imaging device according to another embodiment of the present invention.

FIG. 4 is a view showing a cross section of a unit cell of the MOS type solid-state imaging device according to the same embodiment.

FIG. 5 is a circuit configuration diagram showing an outline of a conventional MOS solid-state imaging device.

FIG. 6 is a timing chart showing an operation of a conventional MOS solid-state imaging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Photodiode, 2 ... Amplification transistor, 3 ... Vertical selection transistor, 4 ... Reset transistor, 5 ... Vertical shift register, 6 ... Horizontal address line, 7 ... Reset line, 8 ... Vertical signal line, 9 ... Load transistor, 10 ... Clamp capacitance, 11 ... Clamp transistor, 12 ... Sample and hold transistor, 13 ... Sample and hold capacitance, 14 ... Horizontal shift register, 15 ... Horizontal signal line, 16 ... Clamp node, 17 ... Clamp power supply, 18 ... Horizontal select transistor, 21 ... address pulse, 22 ... clamp pulse, 23 ... reset pulse, 24 ... sample hold pulse, 25 ... horizontal selection pulse, 31 ... power supply line, 32 ... transfer signal line, 33 ... address capacity, 34 ... transfer transistor, 35 ... detection Part, 41 ... Transfer pulse, 2 ... Address pulse, 43 ... Reset pulse, 44 ... Clamp pulse, 45 ... Sample hold pulse, 46 ... Horizontal selection pulse, 51 ... Charge storage diode, 52 ... Transfer transistor, 53 ... Transfer signal line, 54 ... Blocking layer .

Front page continuation (72) Inventor Hisanori Ihara 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Incorporated, Toshiba Research and Development Center

Claims (4)

[Claims] 1. A MOS solid-state imaging device comprising a plurality of unit cells, wherein the unit cells are photoelectric conversion means for converting light into electric charges, and electric charge holding means for holding electric charges output from the photoelectric conversion means. A first transfer gate that is connected between the photoelectric conversion unit and the charge holding unit and transfers the charge output from the photoelectric conversion unit to the charge holding unit when it is on; A voltage output unit that outputs a voltage corresponding to the electric charge held in the first unit cell, and the first unit of some unit cells of the plurality of unit cells.
And a first control means for simultaneously turning on the transfer gates of the MOS type solid-state image pickup device. 2. The unit cell, which is connected between the first transfer gate and the charge holding means, stores charge transferred from the first transfer gate, and the charge storage means. Second transfer gate, which is connected between the charge storage means and the charge storage means and transfers the charge stored in the charge storage means to the charge storage means when it is turned on. The MOS type solid-state image pickup device according to claim 1, further comprising a second control means for sequentially turning on the second transfer gates of the unit cells to be read out of the gates. 3. A photoelectric conversion unit that converts light into an electric charge, a charge holding unit that holds the electric charge output from the photoelectric conversion unit, and a photoelectric conversion unit that is connected between the photoelectric conversion unit and the electric charge holding unit. A unit consisting of a first transfer gate for transferring the electric charge output from the photoelectric conversion means to the electric charge holding means when it is on, and a voltage output means for outputting a voltage corresponding to the electric charge held in the electric charge holding means. A plurality of cells, and among the plurality of unit cells, the first of some of the unit cells
And a first control means for simultaneously turning on the transfer gates of the plurality of unit cells, the method for driving the MOS solid-state imaging device further comprising: The first transfer gate is turned on at the same time, the charge output from the photoelectric conversion means is transferred to the charge holding means, and the charge held in the charge holding means of the unit cell to be read by the voltage output means. A method for driving a MOS type solid-state imaging device, which sequentially outputs voltages corresponding to 4. A photoelectric conversion unit that converts light into an electric charge, a charge holding unit that holds the electric charge output from the photoelectric conversion unit, and a photoelectric conversion unit that is connected between the photoelectric conversion unit and the electric charge holding unit. A first transfer gate that transfers the charge output from the photoelectric conversion unit to the charge holding unit when it is on, a voltage output unit that outputs a voltage corresponding to the charge held by the charge holding unit, and the first transfer gate. A charge storage unit connected between the transfer gate and the charge holding unit and storing the charge transferred from the first transfer gate; and connected between the charge storage unit and the charge holding unit. There is a plurality of unit cells each including a second transfer gate that transfers the charge accumulated in the charge accumulating unit to the charge retaining unit when the unit is on, and some unit cells of the plurality of unit cells are included. The first
Of the second transfer gates, and second control means for sequentially turning on the second transfer gates of the unit cells to be read out of the second transfer gates. In the driving method of the MOS type solid-state imaging device, the method may further include:
By simultaneously turning on the first transfer gates of some unit cells, the charges output from the photoelectric conversion means are simultaneously transferred to the charge storage means, and the plurality of first transfer gates are turned off. , The second control means sequentially turns on the second transfer gates of the unit cells to be read out of the second transfer gates, so that the charge accumulated in the charge accumulating means is changed to the charge. A method of driving a MOS type solid-state image pickup device, which is characterized in that the voltage is transferred to holding means and the voltage output means outputs a voltage corresponding to the charges held in the charge holding means.