JPH09247156A - Line connection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To recover a stable source clock by excluding fluctuation in a data storage amount in a reception buffer by providing a source clock recovery means with a storage amount reference value setting means for setting a data storage amount and an average storage amount calculation means for an indicating average. SOLUTION: Various medium data 211 extracted by a packet disassembly means 100b are written in a reception buffer 201 synchronously with a network clock 11 at a receiver side. An average storage amount calculation means 206 outputs an average storage amount 215 from the buffer 201 to a control signal generating means 203. On the other hand, a storage amount reference setting means 205 outputs a storage amount reference value 216 being the reference of data read start from the buffer 201 to a control signal generating means 203. The signal generating means 203 controls a VCXO 204 that generates a VCXO control signal 213 based on the average storage amount 215 and outputs a recovered clock 214. Thus, a tentative fluctuation in the storage amount in the buffer in the communication network is excluded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique of a line connection device which takes in a packet from a communication network in which data communication of a packet which is divided into a certain length and sequentially outputted is performed.

[0002]

2. Description of the Related Art ATM is a broadband ISDN transmission technology.
Transfers media data having different characteristics such as video, audio, data, etc. uniformly divided into 53-byte long cells (relatively short packets). Therefore, when transferring data such as video and audio having a source clock that is asynchronous with the network clock of the communication network, it is necessary for the receiving side to have a function of reproducing the source clock. In addition, even when communicating with a terminal whose source clock is synchronized with the network clock of the communication network, if the terminal is connected to a communication network with a different clock, the function of reproducing the source clock of the transmitting side on the receiving side is provided. Will be needed. As a clock recovery function using the buffer storage amount, for example, "user / network interface" (T
There is a source clock reproduction function by the adaptive clock method, which is an optional function of AAL type 1 described on page 208 of TC Standard Vol. II, Volume 2, 1993, published by the Telegraph and Telephone Technical Committee.

FIG. 9 is a diagram showing a conventional line connection device having a source clock recovery function. In FIG. 9, 11 is a network clock of the communication network on the receiving side (not shown). Reference numeral 100a is a cell disassembling means for disassembling data sent from the line connection device on the transmission side in units of cells to extract various media data and performing error correction processing for transmission errors and the like. Further, reference numeral 200 is a source clock reproducing means, 201 is a receiving buffer which is composed of a memory, a read / write control circuit, etc., and stores the media data 211 extracted by the cell disassembling means 100a from the received data, and 202 is a receiving buffer. An accumulation amount measuring means for measuring the amount of data accumulated in 201, 203 a VCXO control signal 2 for controlling a voltage controlled crystal oscillator described later based on the accumulation amount 212 measured by the accumulation amount measuring means 202.
13 is a control signal generating means, and 204 is a reproduction clock 214 for reading data from the reception buffer 201.
Is a voltage controlled crystal oscillator (hereinafter referred to as VCXO). Then, the cell disassembling means 100a and the source clock regenerating means 200 constitute a line connection device.

The operation of the conventional line connection device having such a configuration will be described. In the line connection device on the data transmission side (not shown), various media data such as video, audio, and other data are divided into cells, and each cell is directed toward the line connection device on the data reception side at regular intervals and at equal intervals. Is output with.

In the line connection device on the receiving side, first, each cell received by the cell disassembling means 100a is disassembled and various media data is taken out. Here, in the line connection device on the transmission side, if a check byte for error correction processing for transmission errors such as cell loss or random error is added to each cell, data check is also performed for error correction processing. Run.

Next, the various media data 211 extracted by the cell disassembling means 100a are written in the reception buffer 201 in synchronization with the network clock 11 of the communication network on the receiving side. In addition, the accumulated amount measuring means 202 uses the reception buffer 20.
The amount of received data accumulated in 1 is measured, and the accumulated amount 212 is output to the control signal generating means 203.

Then, the control signal generating means 203 does not cause overflow or underflow in the receiving buffer 201 in which received data is accumulated, compared to the buffer capacity, due to the difference between the capacity of the receiving buffer 201 and the accumulated amount 212. As described above, the VCXO control signal 213 is generated based on the accumulated amount 212 to control the VCXO 204.

That is, when the network clock 11 of the communication network on the receiving side is larger than the rate of the reproduction clock 214, the amount of data accumulated in the reception buffer 201 increases and an overflow occurs. The VCXO control signal 213 is generated so that

On the contrary, when the network clock 11 of the communication network on the receiving side is smaller than the rate of the reproduction clock 214, the amount of data accumulated in the reception buffer 201 decreases and underflow occurs. Generates a VCXO control signal 213 so that

Here, reading of various media data from the reception buffer 201 is started when the measured storage amount 212 reaches a preset read start storage amount, and this read processing is performed by the VCXO control signal 213. Based on this, the VCXO 204 is performed in synchronization with the reproduced clock 214. The various media data read from the reception buffer 201 in this way are sent to the upper layer.

As described above, the VCXO control signal 213 is determined based on the accumulated amount 212 output from the accumulated amount measuring means 202, and the reproduction clock 214 output from the VCXO 204.
Feedback control is performed so that the clock signal coincides with the source clock.

[0012]

As described above, in the conventional line connection device having the source clock reproducing function, the rate of the reproduced clock 214 is controlled so that the data accumulated in the receiving buffer 201 becomes a constant amount. Therefore, the accumulated amount 212 has a great influence on the reproduced clock 214. Therefore, the reproduced clock 214 is easily affected by the fluctuation of the accumulated amount 212 due to the fluctuation of cell delay in the network,
There is a problem in that the jitter of the reproduction clock 214 (pulse temporal fluctuation) increases.

Further, when the accumulated amount measuring means 202 measures the accumulated data and outputs the accumulated amount 212 before the accumulated amount 212 reaches the accumulated amount reference value at the start of reading, for example immediately after starting the reception of data. , Control signal generating means 2
03 determines that the reception buffer 201 is underflowing, and sets the rate of the reproduction clock 214 to the network clock 1
The VCXO control signal 213 is determined so as to be smaller than 1. Then, the VCXO control signal 213 is determined so that the accumulated amount 212 becomes larger at the next measurement of the accumulated amount and the rate of the reproduction clock 214 becomes larger than the network clock 11. Therefore, when the difference between the source clock and the initial oscillation frequency of the VCXO 204 is large, the reproduction clock 2
14 is not stable and diverges.

Further, since the rate of the reproduction clock 214 is controlled so that a fixed amount of received data is accumulated in the reception buffer 201 regardless of the communication speed, the accumulated amount 212 serving as a control reference is set. If you set a value that does not cause underflow or overflow due to the influence of cell delay fluctuations regardless of the communication speed,
A large processing delay occurs in low speed communication.

Further, since writing and reading with respect to the reception buffer 201 are performed asynchronously, when each is performed intermittently (so-called burst-like) in cell units or the like, the accumulated data is measured by the accumulated amount measuring means 202. Since a large measurement error is included in each measurement, the accumulated amount 212 in each measurement also includes a large error.
Destabilize.

Further, since there is no correlation between the cell input to the cell disassembling means 100a and the writing to the receiving buffer 201, fluctuations in the processing time in the processing in the cell disassembling means 100a cause the reception buffer 201 to receive data. Fluctuations occur in the write timing. Therefore, the accumulated amount 212 for each measurement fluctuates, and the reproduced clock 214 becomes unstable.

Further, since the data is read from the reception buffer 201 at a predetermined speed, when the transmission side line connection device is outputting cells at a variable speed, the accumulated amount 212 for each measurement greatly fluctuates. Then, the reproduction clock 21
4 causes the stability of No. 4 to decrease, and also causes the overflow and underflow of the reception buffer 201.

The present invention has been made in order to solve the above problems, and provides a line connection device which eliminates instability, so-called jitter, which occurs in a reproduced source clock due to delay variation in cell transmission processing. The purpose is to get.

[0019]

A line connection device according to the present invention decomposes an input packet to extract data and packet decomposing means uses the data extracted by the packet decomposing means as a network clock of a communication network on the packet receiving side. The reception buffer that writes in synchronization, the storage amount reference value setting means that presets the storage amount reference value that is the reference for starting the reading process of the data stored in the reception buffer, and the storage amount of data in the reception buffer A storage amount measuring unit for measuring, and a data storage amount reference value calculating unit for calculating a data storage amount reference value when determining a control signal for controlling the voltage controlled crystal oscillator based on the data storage amount measured by the storage amount measuring unit. Based on the storage amount reference value preset in the storage amount reference value setting means and the data storage amount reference value calculated by the data storage amount reference value calculation means. A control signal generating means for generating a control signal, in which the control signal generating means data from the receive buffer on the basis of a control signal is output and a voltage controlled crystal oscillator for generating a reproduction clock when being read.

The data storage amount reference value calculating means uses the average value of the data storage amount measured by the storage amount measuring means as the data storage amount reference value.

Further, the data storage amount reference value calculation means calculates the value obtained based on the average value of the data storage amount measured in the past by the storage amount measurement means and the data storage amount newly measured by the storage amount measurement means. The data storage amount reference value is used.

The data storage amount reference value calculating means uses the storage amount reference value set in the storage amount reference value setting means as the first data storage amount reference value.

The storage amount reference value setting means is such that the setting of the storage amount reference value is variable according to the communication speed.

The accumulated amount measuring means is adapted to measure accumulated data at regular intervals.

Further, the storage amount measuring means is adapted to measure the data storage amount at intervals of an integral multiple of the data writing or data reading unit to the receiving buffer.

The control signal generating means determines the control signal based on the ratio of the difference between the data storage amount reference value and the storage amount reference value with respect to the storage amount reference value.

Further, input timing storing means for storing the input timing time of the packet to the packet decomposing means is further provided, and the packet decomposing means delays a predetermined time from the input timing time based on the output from the input timing storing means. It is designed to be written in the reception buffer after a lapse of time.

Further, the packet disassembling means, when a signal is inputted from the input timing storing means, outputs the data disassembled from the packet previously inputted to the packet disassembling means in accordance with this signal and writes it in the receiving buffer. It was done.

Further, the reception buffer outputs data having a data capacity equal to the written data capacity.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 is a block diagram of a line connection device according to the first embodiment. In FIG. 1, as a new configuration to the above-mentioned conventional example, in the source clock reproducing means 200, 205 is a data storage amount (storage amount reference value 216) of the reception buffer 201 which becomes a reference when starting reading of data from the reception buffer 201. ) Is set as the storage amount reference value setting means, and 206 is an average storage amount 2 indicating the average value of the data storage amount which is the data storage amount reference value based on the storage amount 212
It is an average accumulated amount calculation means for calculating 15.

On the other hand, 100b decomposes the data divided into packets and sent out from the line connecting device on the transmitting side (not shown) to take out various media data,
It is a packet decomposing means for performing error correction processing for transmission errors and the like. The packet disassembling means 100b performs the same processing operation as the cell disassembling means 100a shown in the conventional example, and is the size of the data to be processed in packet units in comparison with the cell disassembling means 100a? The only difference is whether it is a cell unit, which is a unit smaller than a packet.

The operation of the line connecting device thus configured will be described. Similar to the conventional example, in the line connection device on the data transmission side (not shown), various media data such as video, audio, and other data are divided into packets, and each packet is directed to the line connection device on the data reception side. It is output at equal intervals at the communication speed.

In the line connecting device on the receiving side, like the conventional example, first, each packet received by the packet decomposing means 100b is decomposed to extract various media data. Here, in the line connection device on the transmission side, when a check byte or the like for error correction processing for a transmission error or the like is added to each packet, data check is performed and error correction processing is also executed.

Next, the various media data 211 extracted by the packet disassembling means 100b are written in the reception buffer 201 in synchronization with the network clock 11 of the communication network on the receiving side. The accumulated amount measuring means 202 measures the accumulated amount of the data accumulated in the reception buffer 201 and outputs the accumulated amount 212 to the average accumulated amount calculating means 206.

The average storage amount calculating means 206 calculates the average value of the storage amount of the receiving buffer 201 from the latest plurality (for example, m pieces) of data in the storage amount 212 measured by the storage amount measuring means 202 in the past. , And outputs the average accumulated amount 215 to the control signal generating unit 203. Where the average accumulated amount is 2
15 is calculated according to the equation (1).

A (m) = [S (1) + S (2) + ... + S (m-1) + S (m)] / m (1) where A (m) is in the past The accumulated amount measuring means 202 measures and outputs the accumulated amount 212, which is the average accumulated amount 215 that is the average value of the latest m pieces of data, and S (m) is the m-th time that the accumulated amount measuring means 202 has performed in the past. The accumulated amount 212 is the measured data of the accumulated amount measurement. The average accumulated amount 215 thus calculated is output to the control signal generating means 203.

On the other hand, the accumulated amount reference value setting means 205 includes
The read start accumulation amount from the reception buffer 201 and the range for accumulating the data in the reception buffer 201 are set in advance. The accumulation reference value setting unit 205 outputs the accumulation amount reference value 216, which is a reference for starting data reading from the reception buffer 201, to the reception buffer 201 and the control signal generation unit 203.

Further, the reading of various media data from the reception buffer 201 is performed based on the storage amount standard in which the storage amount 212 measured by the storage amount measuring means 202 is the read start storage amount preset in the storage amount reference value setting means 205. Value 21
It starts when 6 is reached (equal to). This read process is based on the VCXO control signal 213,
This is performed in synchronization with the reproduction clock 214 generated by O204.

Then, the control signal generating means 203 averages the received data accumulated in the receive buffer 201 so as not to cause overflow or underflow in comparison with the preset data accumulation range in the receive buffer 201. Based on the quantity 215, the VCXO control signal 213 similar to that of the conventional example is generated to control the VCXO 204.

The VCXO control signal 2 is thus calculated based on the average accumulated amount 215 calculated by the average accumulated amount calculating means 206.
13 is set, and feedback control is performed so that the reproduction clock 214 output from the VCXO 204 matches the original source clock before the data is sent to the communication network.

Therefore, according to the first embodiment, the packet decomposing means 100b for decomposing the input packet to extract the data and the data taken out by the packet decomposing means 100b are synchronized with the network clock 11 of the communication network on the packet receiving side. Reception buffer 201 and reception buffer 20
1. A storage amount reference value setting unit 205 in which a storage amount reference value 216 serving as a reference for starting the reading process of the data stored in 1 is preset, and a storage amount measuring unit for measuring the data storage amount in the reception buffer 201. 202 and a VCXO control signal 21 for controlling the voltage controlled crystal oscillator 204 based on the data storage amount 212 measured by the storage amount measuring means 202.
Storage amount average value calculating means 206 for calculating the data storage amount reference value 215 when determining 3 and storage amount reference value setting means 2
Control signal generating means 203 for generating a VCXO control signal 213 based on the accumulated amount reference value 216 preset in 05 and the accumulated amount average value 215 calculated by the accumulated amount average value calculating means 206; and a control signal generating means. V output by 203
Since the VCXO 204 for generating the reproduction clock 214 when the data is read from the reception buffer 201 based on the CXO control signal 213 is provided, the temporary reception buffer 201 in the reception buffer 201 due to the influence of delay variation in the communication network is provided. The stable source clock can be recovered and obtained by eliminating the influence of the fluctuation of the data storage amount.

Further, the average accumulated amount calculating means 206 has an average value 21 of the accumulated amount of data measured by the accumulated amount measuring means 202.
Since 5 is obtained and used as the data storage amount reference value, the temporary reception buffer 201 caused by the influence of delay variation in the communication network
A stable source clock can be recovered and obtained by eliminating the influence of fluctuations in the amount of accumulated data.

Embodiment 2 In the first embodiment, instead of the average accumulated amount 215 calculated using the equation (1),
You may use the approximated value calculated using the following formula (2). A (m) = A (m-1) × (m-1) / m + S (m) / m (2)

Therefore, according to the second embodiment, the average accumulated amount calculating means 206 is configured so that the average amount of accumulated data measured by the accumulated amount measuring means 202 in the past and the accumulated amount measuring means 20.
Since the value 2 obtained based on the newly measured data storage amount is used as the data storage amount reference value, the average storage amount calculation means 20 can be used, for example, the memory circuit can be reduced.
6 can be easily configured.

Embodiment 3 In addition, in the first and second embodiments, the accumulated amount reference value 216 is used as the initial value of the average value of the accumulated amount 212 (the initially calculated average value), and the value is calculated by the formula (1) or the formula (2). You may

Therefore, according to the third embodiment, the accumulated amount reference value 216 is the accumulated amount average value first obtained from the data accumulated amount measured by the accumulated amount measuring means 202. It is possible to eliminate the abrupt fluctuation of the average accumulated amount 215 from the time to the steady state, and further to eliminate the abrupt fluctuation of the reproduction clock 214.

Embodiment 4 In the first embodiment, the accumulated amount reference value 216 output by the accumulated amount reference value setting means 205 is
Although a fixed value (for example, 50% of the capacity of the reception buffer 12) which is once set in the accumulated amount reference value setting means 205 is used, the accumulated amount reference value 216 is variable according to the communication status. The value may be variable according to the communication speed so that the value becomes large during high-speed communication and becomes small during low-speed communication.

Therefore, according to the fourth embodiment, since the storage amount reference value 216 is variable according to the communication speed, the reception data is not stored in the reception buffer 201 unnecessarily, and the storage is not performed. The delay time due to can be minimized.

Embodiment 5. In addition, in the first to fourth embodiments, the accumulated amount measuring means 202 is the reception buffer 201.
The measurement of the accumulated amount may be periodically performed at regular time intervals.

Therefore, according to the fifth embodiment, the accumulated amount measuring means 202 measures the accumulated data at regular intervals, so that the accumulated amount measuring means 202 measures the accumulated data. The accumulated amount 212, that is, the average accumulated amount 215 calculated by the average accumulated amount calculating means 206 is less affected by a packet reception delay variation or the like that temporarily occurs in the communication network.

Embodiment 6 FIG. Further, in the first to fifth embodiments, the reception buffer 20 performed by the accumulated amount measuring means 202.
In the measurement of the storage amount of 1, the a-byte (a is a natural number) which is a writing unit to the reception buffer 201 and the b-byte (b is a natural number) which is a reading unit are compared, and the least common multiple thereof is c-byte (c = A × k = b × l, where k and l are both natural numbers and n times (n is a natural number) may be periodically written at any time of writing or reading. That is, it may be periodically performed at any time interval when writing or reading n × c bytes of data.

FIG. 2 is a time chart showing an example of the measurement intervals that the accumulated amount measuring means 202 periodically performs.
Medium, a = 3 bytes, b = 4 bytes, k = 4, l = 3, c
= 12 bytes and n = 1. In this case, for example, while reading data n × c (= 12) bytes, k ×
Since n (= 4) pieces of data are written, when the storage amount measuring means 202 regularly measures the storage amount at this cycle interval, the storage amount in the reception buffer 201 does not change.

Therefore, according to the sixth embodiment, the storage amount measuring means 202 measures the data storage amount at intervals of an integral multiple of the data writing or data reading unit to the receiving buffer 201. Since it is sufficient to count and grasp the number of write units and read units instead of the actual buffer accumulated amount, the accumulated amount measuring means 202
Can be simply configured.

Embodiment 7 FIG. In the first to sixth embodiments, the control signal generating means 203 uses the VCXO control signal 21.
3, the control signal 21 is a value obtained by relativizing the difference between the accumulated amount reference value 216 and the average accumulated amount 215 with the accumulated amount reference value 216.
It may be adopted as 3 and output to the VCXO 204.

FIG. 3 is an explanatory diagram of the processing performed by the control signal generating means 203 in the seventh embodiment. In FIG. 3, the data storage capacity of the reception buffer 201 is variable according to the communication speed in order to eliminate the processing delay in the source clock reproduction means 200, and the storage amount reference value 216 is set to the reception buffer 201. The storage amount reference value 216 is set to a value of a predetermined ratio to the capacity capable of storing data in
The value k (−1 <k <1) obtained by making the difference between the average storage amount 215 and the average storage amount 215 relative by the storage reference value 216 is adopted as the VCXO control signal 213. Therefore, when -1 <k <0, there is a tendency for underflow, and when 0 <k <1, there is a tendency for overflow.

Therefore, according to the seventh embodiment, the control signal generating means 203 outputs the control signal 213 based on the ratio of the difference between the data storage amount reference value and the storage amount reference value 216 with respect to the storage amount reference value 216. Since the determination is made, the control signal generating means 203 has a simple structure even when the amount of data that can be stored in the receiving buffer 201 is changed according to the communication speed. By grasping the tendency of data fluctuation in 201, it is possible to generate the VCXO control signal 213 which eliminates underflow and overflow in the reception buffer 201 and makes the amount of data accumulated in the reception buffer 201 constant.

Embodiment 8 FIG. For example, the first to seventh embodiments
In order to efficiently perform the data writing process in the reception buffer 201, the influence of the processing delay in the packet decomposing unit 100b may be eliminated. The eighth embodiment will be described as a modification of the first embodiment for convenience of description.

FIG. 4 is a block diagram of a line connection device according to the eighth embodiment. 4, as a new configuration to the configuration shown in FIG. 1, 207 is an input timing storage means for storing the input timing time at which the packet is input to the packet disassembling means 100b, and 217 is the packet disassembling means 100.
The write timing signal is a timing signal for writing data from b to the reception buffer 201. The write timing signal 217 is output from the input timing storage means 207 to the packet disassembling means 100b.

The operation of the line connecting apparatus according to the eighth embodiment configured as described above will be described with reference to the time chart for explaining the operation shown in FIG. When packets (for example, four) are sequentially input to the packet disassembly unit 100b, the input packets are disassembled in the same manner as in the first embodiment, various media data are extracted, and data error correction processing is performed. These input timing times, for example, times t0, t0 + t1, t0 + t2, t0 + t3 are also input to the input timing storage means 207 and stored therein.

Here, although the time required for the packet disassembling means 100b to actually perform the packet disassembling and the error correcting process differs depending on each packet, each media data 211 extracted from each packet is output and written in the receiving buffer 201. The delay time up to is uniformly set to time tn regardless of the packet. Here, the delay time tn is set to a time sufficiently larger than the maximum value of the time actually required for the packet decomposing means 100b to perform the processing.

Next, the input timing storage means 207
Since the extracted data is written in the reception buffer 201, the delay time tn is set at each input timing time.
The write timing signal 217 is output to the packet disassembling means 100b at the time of adding.

That is, the various media data 211 extracted from the packets respectively inputted at the times t0, t0 + t1, t0 + t2, and t0 + t3 to the packet disassembling means 100b take the delay time tn of the processing in the packet disassembling means 100b into consideration. Then, the data input time t0, t0 + t
Times t0 + tn, t0 + t1 + tn, t0 + t2 + tn obtained by adding delay time tn to 1, t0 + t2, t0 + t3.
, T0 + t3 + tn, write timing storage means 2
In accordance with the write timing signal 217 output from 07 to the packet disassembling means 100b, the packet disassembling means 10
It is output from 0b and written in the reception buffer 201.

Therefore, according to the eighth embodiment, the input timing storing means 207 for storing the input timing time of the packet to the packet decomposing means 100b is further provided, and the packet decomposing means 100b receives from the input timing storing means 207. The reception buffer 20 receives a predetermined delay time from the input timing time based on the output.
Since it is written to 1, the influence of the packet delay variation can be eliminated by the adjustment in which the write timing to the reception buffer 201 is delayed, and the influence of the processing delay of the packet disassembling unit 100b can be eliminated.

Embodiment 9 For example, in the eighth embodiment, according to the packet input timing to the packet decomposing unit 100b, various media data 211 extracted from the packet already input to the packet decomposing unit 100b before that are written to the reception buffer 201. May be.

The operation of the line connection device according to the ninth embodiment will be described below with reference to the time chart for explaining the operation shown in FIG. When packets (for example, 10th data to 13th data) are sequentially input to the packet disassembling unit 100b, the input packet is disassembled in the same manner as in the first embodiment, and various media data is taken out or data error occurs. The correction processing is performed, and their input timing times t0, t0 + t1, t0 + t2, t0 + t3.
Is also input to and stored in the input timing storage means 207.

Then, the input timing storage means 207
Are input timing times t0, t0 + t1,
That is, as soon as the input timing time is input to t0 + t2 and t0 + t3, the data write timing signal 217 to the receiving buffer 201 is sent to the packet disassembling means 10.
Output to 0b.

When the write timing signals 217 are sequentially input from the input timing storage means 207 to the packet disassembling means 100b, the packet disassembling means 10 has already been received.
Various media data 211 extracted from a packet input to 0b, which is n packets before the packet corresponding to the input timing signal (n is a natural number of n <10), and extracted to the reception buffer 201. Are written according to the timing signal of.

In other words, time t0, t0 + t1, t0 + t2
, T0 + t3, 10th, 11th, 12th, 13th
The second packet is sequentially input to the packet disassembling means 100b and the input timing time is input timing storing means 2
If the write timing signal 217 is sequentially stored in the packet decomposing means 100b from the input timing storing means 207 at the same time, it is 10-n.
Various media data 211 respectively extracted from the 11th-nth, 12-nth, 13-nth input packets are written in the reception buffer 201 according to these write timing signals 217.

That is, when a packet is input to the packet disassembling means 100b, the various media data 211 already input to the packet disassembling means 100b and disassembled and extracted from the packet n packets before the packet are input as the packet input. The data is written in the reception buffer 201 in synchronization.

Therefore, according to the ninth embodiment, the packet disassembling means 100b has the input timing storing means 20.
When there is a signal input from No. 7, the data decomposed from the packet previously inputted to the packet decomposer 100a according to this signal is outputted and written into the reception buffer 201. Therefore, the effect shown in the eighth embodiment is obtained. In addition to,
The memory circuit of the input timing storage means 24 can be reduced.

Tenth Embodiment In the ninth embodiment, the data capacity of the packet input to the packet disassembling means 100b is equal to the data capacity of the media data written in the receiving buffer 201 by the packet disassembling means 100b according to the write timing signal 217 and further read from the receiving buffer 201. You may do it.

FIG. 7 is a block diagram of a line connection device according to the tenth embodiment. In FIG. 7, the input timing storage means 20
The write timing signal 217 from the No. 7 is not only output to the packet disassembling means 100b, but also the receiving buffer 2
It is also output to 01.

The operation of the line connecting apparatus according to the tenth embodiment configured as described above will be described with reference to the time chart for explaining the operation shown in FIG. Similar to the ninth embodiment, the packet decomposing means 100b stores packets (for example, 10 packets).
If there is a sequential input of (third data to thirteenth data), the input packet is disassembled in the same manner as in the ninth embodiment, and various media data is taken out and data error correction processing is performed. The input timing times t0, t0 + t1, t0 + t2, t0 + t3 are also input to and stored in the input timing storage means 207.

Then, the input timing storage means 207
Are input timing times t0, t0 + t1,
As soon as the input timing time is input at t0 + t2 and t0 + t3, the write timing signal 217 indicating the data writing to the reception buffer 201 is output to the packet decomposing unit 100b and the reception buffer 201.

When the write timing signal 217 is sequentially input from the input timing storage means 207 to the packet disassembling means 100b, the write timing signal 217 is the packet already input to the packet disassembling means 100b as in the ninth embodiment. The various media data 211 decomposed and taken out from the packet n packets before the packet corresponding to are written in the reception buffer 201 from the packet decomposition unit 100b according to the write timing signal 217.

Further, the write timing signal 217 is input from the input timing storage means 207 to the reception buffer 201.
Are input in sequence, the packet decomposing means 100b has already performed 10-sth, 11-sth, 12-sth, 13th.
Of the various media data 211 extracted from the −sth (n <s) input packet and written in the receiving buffer 201 from the packet decomposing unit 100b, it corresponds to the capacity written in the receiving buffer 201 from the packet decomposing unit 100b. Data is write timing signal 217
Accordingly, the data is sequentially output from the reception buffer 201 in synchronization with the reproduction clock 214 as data that can be output to the upper layer, and is transferred to the upper layer.

That is, at times t0, t0 + t1, t0 + t2.
, T0 + t3, 10th, 11th, 12th, 13th
The second packet is sequentially input to the packet disassembling means 100b and the input timing time is input timing storing means 2
If the time is stored in 07, and those times are sequentially output from the input timing storage means 207 as the write timing signal 217 to the packet disassembling means 100b, 10-n.
Various media data 211 extracted from the 11th, 11-nth, 12-nth, 13-nth input packets
Are sequentially written in the reception buffer 201 in accordance with these write timing signals.

Further, in parallel, when the write timing signal 217 is sequentially output from the input timing storage means 207 to the reception buffer 201, the 10-sth and 11-sth positions are output.
Data corresponding to the capacity written in the reception buffer 201 from the packet decomposing means 100b of various media data 211 extracted from the 12th, 12th, and 13th s input packets can be sequentially read according to these write timing signals. Data is output from the reception buffer 201 in synchronization with the reproduction clock 214 and transferred to the upper layer.

Therefore, according to the tenth embodiment, the receiving buffer 201 outputs the data having the same data capacity as the written data capacity, so that the receiving buffer 201 can cope with the fluctuation of the received packet amount. The amount of data stored in the reception buffer 201 is stabilized by changing the amount of reading from the 201, and a stable source clock can be reproduced even when communication is performed with a variable communication speed.

[0080]

According to the present invention, a packet decomposing means for decomposing an input packet to extract data, and a receiving buffer for writing the data extracted by the packet decomposing means in synchronization with the network clock of the communication network on the packet receiving side. A storage amount reference value setting means for presetting a storage amount reference value which is a reference for starting the reading process of the data stored in the reception buffer; and a storage amount measuring means for measuring the data storage amount in the reception buffer. A data storage amount reference value calculating means for calculating a data storage amount reference value when determining a control signal for controlling the voltage controlled crystal oscillator based on the data storage amount measured by the storage amount measuring means, and a storage amount reference value setting A control signal is generated to generate a control signal based on the storage amount reference value preset in the means and the data storage amount reference value calculated by the data storage amount reference value calculation means. Means and a voltage-controlled crystal oscillator that generates a reproduction clock when data is read from the receiving buffer based on the control signal output by the control signal generating means, so that delay variation in cell transmission in the communication network, etc. It is possible to recover the stable source clock and obtain the stable source clock by eliminating the effect of the temporary fluctuation of the data storage amount in the receiving buffer due to the effect of 1.

Further, since the data storage amount reference value calculating means uses the average value of the data storage amount measured by the storage amount measuring means as the data storage amount reference value, the influence of the delay variation of cell transmission in the communication network or the like is affected. It is possible to eliminate the influence of the temporary fluctuation of the data storage amount in the reception buffer and reproduce and obtain a stable source clock.

Further, the data storage amount reference value calculation means calculates the value obtained based on the average value of the data storage amount measured in the past by the storage amount measurement means and the data storage amount newly measured by the storage amount measurement means. Since the data storage amount reference value is used, the data storage amount reference value calculation means can be easily configured.

Further, since the data storage amount reference value calculation means uses the storage amount reference value set in the storage amount reference value setting means as the first data storage amount reference value, the average from the start of communication to the steady state is obtained. It is possible to eliminate abrupt changes in the accumulated amount, and also abrupt changes in the reproduced clock.

Further, since the setting of the storage amount reference value is variable according to the communication speed, the reception data is not stored in the reception buffer unnecessarily, and the delay time due to the storage can be minimized.

Further, since the accumulated amount measuring means measures the accumulated data at regular intervals, the accumulated amount measured by the accumulated amount measuring means, that is, the average accumulated amount calculating means. The average storage amount calculated by is less affected by fluctuations caused by packet reception delays that occur temporarily in the communication network.

Further, the storage amount measuring means measures the data storage amount at intervals of integer multiples of the data writing or data reading unit to the receiving buffer.
Since it is sufficient to count and grasp the number of write units and read units instead of the actual buffer storage amount, the storage amount measuring means can be simply configured.

Further, since the control signal generating means determines the control signal based on the ratio of the difference between the data storage amount reference value and the storage amount reference value with respect to the storage amount reference value, the control signal is received according to the communication speed. Even if the amount of data that can be stored in the buffer is changed, underflow and overflow in the receiving buffer can be prevented by using a simple configuration of the control signal generation means and grasping the tendency of data fluctuation in the receiving buffer. It is possible to generate a control signal that eliminates and keeps the data storage amount in the reception buffer constant.

Further, input timing storing means for storing the input timing time of the packet to the packet decomposing means is further provided, and the packet decomposing means delays a predetermined time from the input timing time based on the output from the input timing storing means. Since the writing is performed in the reception buffer after the elapse of time, the influence of the packet transmission delay can be eliminated by the adjustment in which the writing timing in the reception buffer is delayed, and the influence of the processing delay in the packet disassembly can be eliminated.

Further, when a signal is input from the input timing storage means, the packet disassembling means outputs the data disassembled from the packet previously input to the packet disassembling means according to this signal and writes it in the receiving buffer. Therefore, the memory circuit of the input timing storage means can be reduced.

Further, since the receiving buffer outputs the data having the same data capacity as the written data capacity, the read amount from the receiving buffer is also changed in response to the change in the received packet amount. Even when the amount of data stored in the buffer is stable and communication is performed with variable speed communication, a stable source clock can be reproduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a line connection device according to a first embodiment.

FIG. 2 shows a storage amount measuring means 202 in the sixth embodiment.
It is a time chart figure which shows the example of the measurement interval which is performed.

FIG. 3 is a control signal generating means 20 according to the seventh embodiment.
It is explanatory drawing of the process which 3 performs.

FIG. 4 is a configuration diagram of a line connection device according to an eighth embodiment.

FIG. 5 is a time chart for explaining the operation of the line connection device according to the eighth embodiment.

FIG. 6 is a time chart for explaining the operation of the line connection device according to the ninth embodiment.

FIG. 7 is a configuration diagram of a line connection device according to a tenth embodiment.

FIG. 8 is a time chart explaining the operation of the line connection device according to the tenth embodiment.

FIG. 9 is a configuration diagram of a conventional line connection device.

[Explanation of symbols]

100b Packet disassembling means, 205 accumulated quantity reference value setting means, 206 average accumulated quantity calculation means, 207 input timing storage means, 215 accumulated quantity reference value, 216 average accumulated quantity, 217 write timing signal.

Claims (11)

[Claims] 1. A packet decomposing means for decomposing an input packet to extract data, a receiving buffer for writing the data extracted by the packet decomposing means in synchronization with a network clock of a communication network on the packet receiving side, and the receiving buffer. An accumulation amount reference value setting unit that presets an accumulation amount reference value that is a reference for starting the reading process of accumulated data; an accumulation amount measuring unit that measures the amount of data accumulated in the reception buffer; Data storage amount reference value calculation means for calculating a data storage amount reference value when determining a control signal for controlling the voltage controlled crystal oscillator based on the data storage amount measured by the amount measurement means, and the storage amount reference value setting means A control signal for generating the control signal based on the storage amount reference value preset in the above and the data storage amount reference value calculated by the data storage amount reference value calculation means. A circuit connection comprising control signal generating means and a voltage controlled crystal oscillator for generating a reproduction clock when data is read from the receiving buffer based on the control signal output by the control signal generating means. apparatus. 2. The line connection according to claim 1, wherein the data storage amount reference value calculation unit uses an average value of the data storage amount measured by the storage amount measurement unit as a data storage amount reference value. apparatus. 3. The data storage amount reference value calculation means obtains the data storage amount reference value based on an average value of the data storage amount measured in the past by the storage amount measurement means and a data storage amount newly measured by the storage amount measurement means. The line connection device according to claim 1, wherein the value set as the reference value is a data storage amount reference value. 4. The data storage amount reference value calculation means sets the storage amount reference value set in the storage amount reference value setting means to a first value.
The line communication connection circuit according to any one of claims 1 to 3, wherein the data storage amount reference value for the second time is used. 5. The line connection device according to claim 1, wherein the storage amount reference value setting unit makes setting of the storage amount reference value variable according to a communication speed. 6. The line connection device according to claim 1, wherein the accumulated amount measuring means periodically measures accumulated data at regular time intervals. 7. The storage amount measuring means measures the data storage amount at intervals of an integer multiple of a data writing or data reading unit with respect to the reception buffer. The line connection device described. 8. The control signal generation means determines the control signal based on a ratio of a difference between the data storage amount reference value and the storage amount reference value with respect to the storage amount reference value. Item 7. The line connection device according to items 1 to 7. 9. An input timing storage means for storing an input timing time of a packet to the packet disassembly means is further provided, and the packet disassembly means is preliminarily calculated from the input timing time based on an output from the input timing storage means. 9. The line connection device according to claim 1, wherein data is written in the reception buffer after a lapse of a predetermined delay time. 10. The packet disassembling means, when a signal is input from the input timing storage means, outputs the data disassembled from the packet previously input to the packet disassembling means in accordance with this signal to output the receive buffer. The line connection device according to claim 9, wherein the line connection device is written in. 11. The line connection device according to claim 10, wherein the reception buffer outputs data having a data capacity equal to the written data capacity.