JPH09223746A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises a PiN type photodiode having high frequency characteristics, a bipolar transistor and a CMOS transistor formed on an identical substrate. SOLUTION: In the semiconductor device comprising a PiN type photodiode, vertical and horizontal bipolar transistors formed on a P type substrate 1; a collector region of a vertical NPN bipolar transistor and a base region of a horizontal PNP bipoalr transistor are made up of an N<+> type buried layer 2 formed with use of antimony, an N<-> type buried layer 4 formed on the buried layer 2 with use of phosphorus larger in diffusion coefficient than antimony, and an N type diffusion layer 8 formed to be connected to the N-type buried layer 4. Therefore, a thermal step of connecting the N<-> type buried layer 4 and N type diffusion layer 8 can be shortened, diffusion of the N<+> type buried layer 2 of the PiN type photodiode into a low-concentration epitaxial layer 6 can be made small, and thus high frequency characteristics can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a PiN type photodiode having high frequency characteristics and a bipolar transistor or a CMOS transistor are formed on the same substrate.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device in which a PiN type photodiode, a vertical NPN bipolar transistor, and a horizontal PNP bipolar transistor are formed on the same substrate is constructed as shown in FIG. In FIG. 9, 101 is a P-type semiconductor substrate, 102 is an N ⁺ -type buried layer, 103 is an N ⁻ epitaxial layer, 104 is a P-type element isolation diffusion layer, and 105 is N-type.
Type collector diffusion layer, 106 N type base diffusion layer, 107 N type
Type cathode extraction layer, 108 is a P type base diffusion layer, 109
Is a P ⁺ -type anode layer, 110 is an N ⁺ -type emitter layer, 111 is a P ⁺ -type emitter layer, and 112 is a P ⁺ -type collector layer.
The collector region of the vertical NPN bipolar transistor has an N ⁺ type buried layer 102 and an N type collector diffusion layer 105.
And the base region of the lateral PNP bipolar transistor is composed of the N ⁺ type buried layer 102 and the N type base diffusion layer.
It is formed by 106. In the figure, Pi
The N-type photodiode region is abbreviated as PD, the vertical NPN bipolar transistor region is abbreviated as NPN, and the lateral PNP bipolar transistor region is abbreviated as LPNP.

A PiN type photodiode and a vertical N type
Conventionally, a semiconductor device in which a PN bipolar transistor, a lateral PNP bipolar transistor, an NMOS transistor and a PMOS transistor are formed on the same substrate is shown in FIG.
It is configured as shown in FIG. In FIG. 10, 201 is P
Type semiconductor substrate, 202 is an N ⁺ type buried layer, 203 is a P type buried layer, 204 is an N ⁻ epitaxial layer, 205 is a P type element isolation diffusion layer, 206 is an N type collector diffusion layer, and 207 is an N type base diffusion layer. , 208 is an N-type cathode extraction layer, 209 is an N-type well diffusion layer, 210 is a P-type well layer, 211 is a P-type base diffusion layer, 212 is a gate oxide film, 213 is a gate electrode, and 214 is P.
⁺ Type anode layer, 215 is N ⁺ type emitter layer, 216 is P ⁺
A type emitter layer, 217 is a P ⁺ type collector layer, 218 is a P ⁺ source / drain layer, and 219 is an N ⁺ source / drain layer. The collector region of the vertical NPN bipolar transistor includes an N ⁺ type buried layer 202 and an N type collector diffusion layer.
The base region of the lateral PNP bipolar transistor formed by 206 is formed by the N ⁺ type buried layer 202 and the N type base diffusion layer 207, and the well region of the PMOS transistor is formed by the N ⁺ type buried layer 202 and the N type well diffusion layer 209. It is formed by. The N-type collector diffusion layer 206 and the N-type well diffusion layer 209 are formed in the same process. In the figure, the NMOS transistor is an NMOS,
The PMOS transistor is abbreviated as PMOS.

[0004]

By the way, FIG. 9 and FIG.
In the conventional example shown in FIG. 10, N ⁺ type buried layers 102 and 202
Uses antimony to reduce parasitic resistance 1
It is formed at a high concentration of E18 cm ^-3 or more. This antimony has a small diffusion coefficient. Further, in the conventional example shown in FIG. 9, the vertical NPN bipolar transistor of the N ⁺ -type buried layer 102 and the N-type collector diffusion layer 105, N ⁺ -type buried layer of the lateral PNP bipolar transistor 102 and the N-type base diffusion layer 106 In order to connect each of them, a diffusion process at high temperature for a long time is required. Similarly, in the conventional example shown in FIG. 10, the N ⁺ type buried layer 202 and the N type collector diffusion layer 206 of the vertical NPN bipolar transistor, and the N ⁺ type buried layer 202 and the N type base diffusion layer 207 of the lateral PNP bipolar transistor are provided. Since the N ⁺ type buried layer 202 of the PMOS transistor and the N type well diffusion layer 209 are connected to each other, a diffusion process at high temperature for a long time is required. By this high temperature and long diffusion process, as shown in the impurity profile of the photodiode region in FIG. 11 (the impurity profile along the line AA ′ in FIGS. 9 and 10), the N ⁺ type buried layer in the photodiode region is formed. 102 and 202 are diffused to the N ^- epitaxial layer side and become an i-layer N ^- epitaxial layer 103,
The area X of 204 becomes narrow. In the operating state of the photodiode, the region X of the N ⁻ epitaxial layers 103 and 204 is formed.
Is depleted, and the carriers generated in the depletion layer move due to drift, so the carriers move at high speed.
Since the carriers generated in the N ⁺ type buried layers 102 and 202 move due to diffusion, the carrier moving speed is slow. Therefore, if the region X of the N ^- epitaxial layers 103 and 204 is narrow, the frequency characteristic of the photodiode is deteriorated and high speed operation cannot be performed. Further, in the conventional example shown in FIG. 10, in order to secure the breakdown voltage of the PMOS transistor, it is necessary to set the concentration of the N-type well diffusion layer 209 to 1E16 cm ⁻³ or more. Since the diffusion layer 209 is formed in the same process, the concentration of the N-type collector diffusion layer 206 is also 1E16 cm ⁻³ or more, which is a vertical N-type.
There is a drawback that the breakdown voltage of the PN bipolar transistor is as small as 10 V or less.

The present invention has been made to solve the above-mentioned problems in the conventional semiconductor device, and the photodiode having high frequency characteristics, the bipolar transistor for forming the analog circuit, and the CMOS transistor are also the same. An object is to provide a semiconductor device configured on a substrate. The purpose of each invention described in each claim is as follows. That is, the invention according to claim 1 aims to provide a semiconductor device in which a photodiode having a high frequency characteristic, a vertical NPN bipolar transistor, and a lateral PNP bipolar transistor are formed on the same substrate. An object of the present invention is to provide a semiconductor device in which a photodiode having a high frequency characteristic, a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, and a CMOS transistor are formed on the same substrate. In the invention of claim 1 or 2, the purpose is to provide appropriate impurities for efficiently forming the first and second buried layers, and the invention of claim 4 is the invention of claim 2. , And an appropriate impurity concentration of the first and second diffusion layers.

[0006]

In order to solve the above problems, the invention according to claim 1 provides at least a semiconductor device having a PiN type photodiode, a vertical bipolar transistor and a horizontal bipolar transistor on the same substrate. The collector region of the vertical bipolar transistor and the base region of the horizontal bipolar transistor are formed on a first buried layer of a first conductivity type and on the first buried layer,
A second buried layer of the first conductivity type formed of an impurity having a diffusion coefficient larger than that of the impurity forming the first buried layer, and a first buried layer of the first conductivity type formed so as to be connected to the second buried layer. One diffusion layer. As a result, the heat process for connecting the second buried layer and the first diffusion layer can be shortened, the diffusion of the first conductivity type first buried layer of the PiN type photodiode toward the low concentration epitaxial layer side can be reduced, and PiN To realize a semiconductor device in which a region of an i-layer composed of a low-concentration epitaxial layer of a p-type photodiode can be enlarged, and a PiN-type photodiode having a high frequency characteristic, a vertical bipolar transistor, and a horizontal bipolar transistor are formed on the same substrate. You can

According to a second aspect of the present invention, in a semiconductor device having a PiN photodiode, a vertical bipolar transistor, a lateral bipolar transistor and a CMOS transistor on the same substrate, at least the collector region of the vertical bipolar transistor and the lateral bipolar transistor. Is formed on the first buried layer of the first conductivity type and an impurity having a diffusion coefficient larger than that of the impurities forming the first buried layer. Of the second buried layer and a first diffusion layer of the first conductivity type formed so as to be connected to the second buried layer, and at least the well region of the second conductivity type MOS transistor is The first buried layer and the second buried layer
The buried layer and the second diffusion layer of the first conductivity type formed so as to be connected to the second buried layer. As a result, a PiN type photodiode having high frequency characteristics as in the first aspect of the present invention can be obtained, and the first conductivity type second diffusion layer forming the well region of the second conductivity type MOS transistor can be obtained. Since the concentration and the concentration of the first diffusion layer of the first conductivity type forming the collector region of the vertical bipolar transistor and the base region of the horizontal bipolar transistor can be formed to be different from each other,
The characteristics of the second conductivity type MOS transistor, the vertical bipolar transistor, and the horizontal bipolar transistor can be set separately, and the breakdown voltage of the vertical bipolar transistor can be increased to 10 V or more. Therefore, it is possible to realize a semiconductor device in which a PiN type photodiode having high frequency characteristics, a high breakdown voltage vertical bipolar transistor, a horizontal bipolar transistor, and a CMOS transistor are formed on the same substrate.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first buried layer is formed by using antimony as an impurity, and the second buried layer is formed by using phosphorus as an impurity. To do. As a result, it is possible to efficiently realize a semiconductor device in which a PiN photodiode, a vertical bipolar transistor, a horizontal bipolar transistor, and further a CMOS transistor having high frequency characteristics are formed on the same substrate. According to a fourth aspect of the present invention, in the semiconductor device according to the second aspect, the impurity concentration of the first diffusion layer is 1E16 cm.
^-3 or less, and the impurity concentration of the second diffusion layer is 1E16 cm ^-3
The above is the description. As a result, it is possible to efficiently realize a semiconductor device in which a PiN photodiode having a high frequency characteristic, a vertical bipolar transistor having a high breakdown voltage, a lateral bipolar transistor, and a CMOS transistor are formed on the same substrate.

[0009]

Next, an embodiment will be described. First, a first embodiment will be described based on the manufacturing process diagrams shown in FIGS. In this embodiment, a PiN type photodiode, a vertical NPN bipolar transistor, a horizontal PNP bipolar transistor and a vertical PNP bipolar transistor are formed on the same substrate, and they correspond to the inventions of claims 1 and 3. is there. First, as shown in FIG. 1, antimony is diffused into the PiN type photodiode region, the vertical NPN bipolar transistor region, the horizontal PNP bipolar transistor region, and the vertical PNP bipolar transistor region of the P type substrate 1 to diffuse the N ⁺ buried layer 2 To form. The N ⁺ for buried layer 2 is reduction of parasitic resistance, formed on 1E19 cm ^-3 or more at a surface concentration, and is finally formed on the high concentration of more than 1E18 cm ^-3. Next, P
In order to form the N ⁻ buried layer 4 in the cathode pull-up region, the vertical NPN bipolar transistor region, and the lateral PNP bipolar transistor region of the iN type photodiode, phosphorus is added at an acceleration voltage of 50 to 150 KeV and a dose amount of 1E13 to 1
Ion-implant at E15cm ^-2 . Next, ion implantation is performed to form a P-type element isolation buried layer 3 in the element isolation region and a P-type buried layer 5 to be a collector buried layer in the vertical PNP bipolar transistor region. In the figure, the vertical PNP bipolar transistor region is abbreviated as VPNP.

Thereafter, as shown in FIG. 2, an N ^- epitaxial layer 6 is formed with a concentration of 1E12 to 1E14 cm ^-3 and a film thickness of 8 to 12 μm.
Formed. This N ^- epitaxial layer 6 is formed in a low concentration and finally becomes the i layer of the PiN type photodiode. Next, the P-type element isolation diffusion layer 7 is provided in the element isolation region.
An N-type diffusion layer 8 is formed in the vertical NPN bipolar transistor region and the horizontal PNP bipolar transistor region, and
P type collector diffusion layer 9 in the P bipolar transistor region
, The N-type cathode extraction layer 10 in the cathode extraction region of the PiN-type photodiode, the N-type collector extraction layer 11 in the collector extraction region of the vertical NPN bipolar transistor, and the N-type base extraction region in the base extraction region of the lateral PNP bipolar transistor. Layer 12, vertical P
Ion implantation is performed to form the P-type collector extraction layer 13 in the collector extraction region of the NP bipolar transistor. Here, phosphorus is used for the ion implantation for forming the N-type diffusion layer 8, and finally the concentration is 1
E16cm ^{-3 It} is formed so as to be less than. Further, boron is used for the ion implantation of the P-type collector diffusion layer 9, and is finally formed so that the concentration becomes 1E16 cm ⁻³ or less. Also,
N-type cathode extraction layer 10 and N-type collector extraction layer 11
The N-type base lead layer 12 may be formed by performing ion implantation at the same time.

Thereafter, as shown in FIG. 3, thermal diffusion is performed to form an N ⁺ burying layer 2, an N ⁻ burying layer 4, a P-type element isolation burying layer 3, a P-type burying layer 5, a P-type element isolation diffusion. A layer 7, an N type diffusion layer 8, a P type collector diffusion layer 9, an N type cathode extraction layer 10, an N type collector extraction layer 11, an N type base extraction layer 12 and a P type collector extraction layer 13 are formed. Here, the N ⁻ buried layer 4 and the N type diffusion layer 8, the N ⁻ buried layer 4, the N type cathode extraction layer 10, the P type element isolation buried layer 3, the P type element isolation diffusion layer 7, the P type buried layer 5 and the P type The type collector diffusion layers 9 are formed so as to be connected to each other, but since the N ⁻ buried layer 4 is formed of phosphorus,
The diffusion coefficient is larger than that of antimony and the time for thermal diffusion can be shortened. For example, what used to require thermal diffusion of 1000 to 1150 ° C for 2000 to 3000 minutes is now 1000 to 1150 ° C and 600 to 1200 ° C.
A minute of thermal diffusion is sufficient. For this reason, the diffusion of the N ⁺ buried layer 2 in the PiN type photodiode region toward the N ⁻ epitaxial layer 6 side becomes small, and the region of the i layer (N ⁻ epitaxial layer 6) of the PiN type photodiode can be formed large. it can. Thereby, the frequency characteristic of the PiN type photodiode can be improved. Also, N
The type diffusion layer 8 and the P type collector diffusion layer 9 have a concentration of 1E16 cm ^-3.
The N ⁺ buried layer 2 is formed below and has a thickness of 1E18 cm ^-3 or more.

Then, as shown in FIG. 4, after forming a field oxide film 14, a P ⁺ type anode layer 17 is formed in the PiN type photodiode region and a P type base layer 15 is formed in the vertical NPN bipolar transistor region. N ⁺ type emitter layer 18
To form N in the vertical PNP bipolar transistor region.
The type base layer 16 is formed, the P ⁺ type emitter layer 19 is formed in the lateral PNP bipolar transistor and vertical PNP bipolar transistor regions, and the P ⁺ type collector layer 20 is formed in the lateral PNP bipolar transistor region. Also, P ⁺
The type anode layer 17, the P ⁺ type emitter layer 19, the P ⁺ type collector layer 20, and the P ⁺ layer of the external base region (not shown) of the vertical NPN bipolar transistor may be formed simultaneously.
The N ⁺ type emitter layer 18 and the N ⁺ layer in the external base region (not shown) of the vertical PNP bipolar transistor may be simultaneously formed. As a result, a semiconductor device in which the PiN type photodiode, the vertical NPN bipolar transistor, the horizontal PNP bipolar transistor, and the vertical PNP bipolar transistor are formed on the P type substrate is completed.

Next, a second embodiment will be described with reference to the manufacturing process diagrams of FIGS. In this embodiment, Pi
N-type photodiode, vertical NPN bipolar transistor, horizontal PNP bipolar transistor, vertical PNP
Bipolar transistor, PMOS transistor and NM
An OS transistor is formed on the same substrate,
The invention corresponds to the invention described in claims 2 and 4. First, as shown in FIG. 5, the PiN type photodiode region, the vertical NPN bipolar transistor region, the horizontal PNP bipolar transistor region, and the vertical PN of the P type substrate 21.
P bipolar transistor region, PMOS region and NM
Antimony is diffused in the OS region to form the N ⁺ buried layer 22. The N ⁺ buried layer 22 is formed to have a surface concentration of 1E19 cm ^-3 or more to reduce parasitic resistance, and finally 1E18 cm ^-3.
It is formed at the above high concentration. Next, in order to form the N ⁻ buried layer 24 in the cathode pull-up region, the vertical NPN bipolar transistor region, the lateral PNP bipolar transistor region, and the PMOS transistor region of the PiN type photodiode, phosphorus is added at an accelerating voltage of 50 to 150 KeV and at a dose. Ion implantation is performed at a dose of 1E13 to 1E15 cm ^-2 . Next, ion implantation is performed to form a P-type element isolation buried layer 23 in the element isolation region and a P-type buried layer 25 serving as a collector buried layer and a well buried layer in the vertical PNP bipolar transistor region and the NMOS transistor region, respectively. To do.

Thereafter, as shown in FIG. 6, an N ^- epitaxial layer 26 having a concentration of 1E12 to 1E14 cm ^-3 and a film thickness of 8 to 12 μm is formed.
Formed. This N ^- epitaxial layer 26 is formed in a low concentration, and finally becomes the i layer of the PiN type photodiode. Next, the P-type element isolation diffusion layer 27 is formed in the element isolation region,
An N-type diffusion layer 28 is formed in the vertical NPN bipolar transistor region and the horizontal PNP bipolar transistor region, and the vertical PN
P type collector diffusion layer 29 in the P bipolar transistor region
, The N-type cathode extraction layer 30 in the cathode extraction region of the PiN-type photodiode, the N-type collector extraction layer 31 in the collector extraction region of the vertical NPN bipolar transistor, and the N-type base extraction region in the base extraction region of the lateral PNP bipolar transistor. Layer 32 to vertical P
Ion implantation is performed to form a P-type collector extraction layer 33 in the collector extraction region of the NP bipolar transistor, an N-type well diffusion layer 34 in the PMOS transistor region, and a P-type well diffusion layer 35 in the NMOS transistor region. Here, phosphorus is used for the ion implantation for forming the N-type diffusion layer 28, and finally the concentration is 1E16.
The ion implantation for forming the N-type well diffusion layer 34 is made to be not more than cm ^−3, and phosphorus is used so that the final concentration is not less than 1E16 cm ⁻³ . Also, P
Boron is used for ion implantation of the type collector diffusion layer 29,
Finally formed to a concentration of 1E16 cm ^-3 or less,
Boron is used for the ion implantation for forming the P-type well diffusion layer 35, and is finally formed to have a concentration of 1E16 cm ^-3 or more. In addition, the N-type cathode lead layer 30 and N
The type collector extraction layer 31 and the N type base extraction layer 32 are
It may be formed by performing ion implantation at the same time.

Thereafter, as shown in FIG. 7, thermal diffusion is performed to form an N ⁺ burying layer 22, an N ⁻ burying layer 24, a P-type element isolation burying layer 23, a P-type burying layer 25, and a P-type element isolation diffusion. Layer 27, N type diffusion layer 28, P type collector diffusion layer 29, N type cathode extraction layer 30, N type collector extraction layer 31, N type base extraction layer 32, P type collector extraction layer 33, N type well diffusion layer 34. , P-type well diffusion layer 35 is formed. Here, the N ⁻ buried layer 24 and the N type diffusion layer 28, the N ⁻ buried layer 24 and the N type
Type cathode extraction layer 30, N ⁻ buried layer 24, N type well diffusion layer 34, P type element isolation buried layer 23, P type element isolation diffusion layer 27, P type buried layer 25, P type collector diffusion layer 29, P type The buried layer 25 and the P-type well diffusion layer 35 are formed so as to be connected to each other, but since the N ⁻ buried layer 24 is formed of phosphorus, the diffusion coefficient is larger than that of antimony, and the thermal diffusion time is longer. Can be shortened. For example, the conventional 1000 ~ 1150 ℃, 20
What required heat diffusion for 00 to 3000 minutes was 1000 to 1150
Thermal diffusion at 600 ° C for 1200 to 1200 minutes is sufficient. Therefore, P
The diffusion of the N ⁺ buried layer 22 in the iN type photodiode region toward the N ⁻ epitaxial layer 26 side is reduced, and the region of the i layer (N ⁻ epitaxial layer 26) of the PiN type photodiode can be formed large. This allows the PiN
The frequency characteristics of the photodiode can be improved. The N-type diffusion layer 28 and the P-type collector diffusion layer 29 are formed to have a concentration of 1E16 cm ^-3 or less, and the N ⁺ buried layer 2 has a concentration of 1E.
Formed over 18 cm ^-3 . The N-type well diffusion layer 34 and the P-type well diffusion layer 35 are formed to have a concentration of 1E16 cm ^-3 or more.

After that, as shown in FIG. 8, after forming a field oxide film 36, a gate electrode 38 is formed in the CMOS transistor region by a gate oxide film 37, Poly Si and the like. Next, a P ⁺ type anode layer 41 is formed in the PiN type photodiode region, and a P type base layer 39 and an N ⁺ type emitter layer 42 are formed in the vertical NPN bipolar transistor region.
N-type base layer in the vertical PNP bipolar transistor area
40 to form a P ⁺ type emitter layer in the lateral PNP bipolar transistor and vertical PNP bipolar transistor regions.
43 is formed, a P ⁺ -type collector layer 44 is formed on the lateral PNP bipolar transistor region to form a P ⁺ type source and drain layer 45 in the PMOS transistor region, the N ⁺ type source and drain layer 46 in the NMOS transistor region Form. Further, the P ⁺ type anode layer 41, the P ⁺ type emitter layer 43, the P ⁺ type collector layer 44, the P ⁺ type source / drain layer 45, and the P ⁺ layer in the external base region (not shown) of the vertical NPN bipolar transistor. May be formed at the same time. The N ⁺ type emitter layer 42, the N ⁺ type source / drain layer 46 and the vertical P type
The N ⁺ layer in the external base region (not shown) of the NP bipolar transistor may be simultaneously formed. This gives P
iN photodiode, vertical NPN bipolar transistor, horizontal PNP bipolar transistor, vertical PN
P bipolar transistor, PMOS transistor and N
A semiconductor device in which a MOS transistor and a P-type substrate are formed is completed.

[0017]

As described above based on the embodiments, according to the invention described in claim 1, the collector region of the vertical bipolar transistor and the base region of the lateral bipolar transistor are provided with the diffusion coefficient of the first conductivity type. Since it is composed of the first and second buried layers and the first diffusion layer of the first conductivity type which are different from each other, the heat process for connecting the second buried layer and the first diffusion layer can be shortened, and the PiN-type photo First of the diode
The diffusion of the conductive type first buried layer toward the low-concentration epitaxial layer side can be reduced, which increases the region of the i-layer (low-concentration epitaxial layer) of the PiN-type photodiode, and the PiN-type with high frequency characteristics. It is possible to realize a semiconductor device including a photodiode, a vertical bipolar transistor, and a horizontal bipolar transistor on the same substrate.

According to the second aspect of the present invention, the collector region of the vertical bipolar transistor, the base region of the lateral bipolar transistor, and the well region of the second conductivity type MOS transistor are formed in the first conductivity type having different diffusion coefficients. 1
And the second buried layer and the first conductive type first or second diffusion layer, the second buried layer and the first conductive type first layer.
Alternatively, the heat step for connecting the second diffusion layer can be shortened,
Since the diffusion of the first buried layer of the first conductivity type of the PiN type photodiode to the low concentration epitaxial layer side can be reduced, the width of the i layer (low concentration epitaxial layer) of the PiN type photodiode can be increased. Furthermore, the second
The second diffusion layer of the first conductivity type forming the well region of the MOS transistor of the conductivity type has the same concentration as the first diffusion layer of the first conductivity type forming the collector region of the vertical bipolar transistor and the base region of the lateral bipolar transistor. Can be formed differently, so that the second conductivity type MOS
The characteristics of the transistor, the vertical bipolar transistor, and the horizontal bipolar transistor can be set separately, and the breakdown voltage of the vertical bipolar transistor can be increased to 10 V or more. As a result, PiN with high frequency characteristics
It is possible to realize a semiconductor device in which a type photodiode, a high withstand voltage vertical bipolar transistor, a horizontal bipolar transistor, and a CMOS transistor are formed on the same substrate.

According to the third aspect of the invention, since the first and second buried layers are formed by using antimony and phosphorus, the Pi having an efficient and high frequency characteristic can be obtained.
It is possible to realize a semiconductor device in which an N-type photodiode, a vertical bipolar transistor, a horizontal bipolar transistor, and further a CMOS transistor are formed on the same substrate. According to the invention described in claim 4, there is provided a semiconductor device in which a PiN type photodiode having a high frequency characteristic, a vertical bipolar transistor having a high breakdown voltage, a lateral bipolar transistor and a CMOS transistor are efficiently formed on the same substrate. Can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process for explaining a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a view showing a manufacturing process subsequent to the manufacturing process shown in FIG. 1;

FIG. 3 is a view showing a manufacturing process following the manufacturing process shown in FIG. 2;

FIG. 4 is a view showing a manufacturing process following the manufacturing process shown in FIG. 3;

FIG. 5 is a diagram showing a manufacturing process for explaining the second embodiment of the present invention.

FIG. 6 is a view showing a manufacturing process subsequent to the manufacturing process shown in FIG. 5;

FIG. 7 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 6;

FIG. 8 is a view showing a manufacturing process subsequent to the manufacturing process shown in FIG. 7;

FIG. 9 is a cross-sectional view showing a configuration example of a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing another configuration example of the conventional semiconductor device.

11 is a Pi along the line AA ′ of the conventional example shown in FIG. 9.
It is a figure which shows the impurity profile of an N-type photodiode.

[Explanation of symbols]

1 P-type substrate 2 N ⁺ buried layer 3 P-type element isolation buried layer 4 N ^- buried layer 5 P-type buried layer 6 N ^- epitaxial layer 7 P-type element isolated diffusion layer 8 N-type diffusion layer 9 P-type collector diffusion layer 10 N-type cathode extraction layer 11 N-type collector extraction layer 12 N-type base extraction layer 13 P-type collector extraction layer 14 Field oxide film 15 P-type base layer 16 N-type base layer 17 P ⁺ -type anode layer 18 N ⁺ -type emitter layer 19 P ⁺ type emitter layer 20 P ⁺ -type collector layer 21 P-type substrate 22 N ⁺ buried layer 23 P-type isolation buried layer 24 N ^- buried layer 25 P-type buried layer 26 N ^- epitaxial layer 27 P-type isolation diffusion layer 28 N type diffusion layer 29 P type collector diffusion layer 30 N type cathode extraction layer 31 N type collector extraction layer 32 N type base extraction layer 33 P type collector extraction layer 34 N type well diffusion layer 35 P type well diffusion layer 36 Field oxide film 37 Gate oxide film 38 Gate electrode 39 P-type base layer 40 N-type base layer 41 P ⁺ -type anode layer 42 N ⁺ -type emitter layer 43 P ⁺ -type emitter layer 44 P ⁺ -type collector layer 45 P ⁺ -type source layer Drain layer 46 N ⁺ type source / drain layer

Claims (4)

[Claims] 1. A semiconductor device having a PiN photodiode, a vertical bipolar transistor and a horizontal bipolar transistor on the same substrate, wherein at least a collector region of the vertical bipolar transistor and a base region of the horizontal bipolar transistor have a first conductivity type. A first buried layer, a second buried layer of a first conductivity type formed on the first buried layer, the second buried layer formed of an impurity having a diffusion coefficient larger than that of an impurity forming the first buried layer, Second first conductivity type first formed to be connected to the buried layer
A semiconductor device comprising a diffusion layer. 2. A PiN type photodiode, a vertical bipolar transistor, a lateral bipolar transistor, and a CM.
In a semiconductor device having an OS transistor on the same substrate, at least the collector region of the vertical bipolar transistor and the base region of the horizontal bipolar transistor are
A first buried layer of a first conductivity type and a second buried layer of a first conductivity type formed on the first buried layer and having an diffusion coefficient larger than that of the impurities forming the first buried layer.
The buried region and a first diffusion layer of a first conductivity type formed so as to be connected to the second buried layer, and at least a well region of a second conductivity type MOS transistor has the first buried region. A semiconductor device comprising a layer, the second buried layer, and a second diffusion layer of the first conductivity type formed so as to be connected to the second buried layer. 3. The semiconductor device according to claim 1, wherein the first buried layer is formed by using antimony as an impurity, and the second buried layer is formed by using phosphorus as an impurity. . 4. The impurity concentration of the first diffusion layer is 1E16 cm.
^-3 or less, and the impurity concentration of the second diffusion layer is 1E16 cm
^-3 or more, The semiconductor device of Claim 2 characterized by the above-mentioned.