JPH0922978A - Semiconductor device and lead frame used for its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device of an LOC structure, which uses a semiconductor chip on which electrodes are formed along the peripheral edge by a method wherein holes to which a wire bonding operation can be performed are formed in lead parts on the electrodes. SOLUTION: Holes 9 through which wires 10 are passed are made in respective inner leads 6 at a lead 2. The holes 9 are situated just above electrodes (bonding pads) 4 which are arranged along both sides of a semiconductor chip 3. Tip ends of the wires 10 are fixed to the electrodes 4 under the holes 9 which have been formed in the inner leads 6. Thereby, the electrodes 4 at the semiconductor chip 3 can be connected to the lead 2, and a semiconductor device of an LOC structure which uses the semiconductor chip 3 comprising the electrodes 4 along the peripheral edge can be obtained. Consequently, the area of the semiconductor chip 3 can be made large, and a package 1 can be miniaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, especially LOC.
The present invention relates to a semiconductor device called "lead on chip" and a lead frame used for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art As one of the structures of a semiconductor device using a lead frame, inner ends of leads are mounted on a semiconductor chip via an insulating tape (insulator), and the inner ends of the leads and the semiconductor chip are connected to each other. A semiconductor device having a LOC structure has been developed in which electrodes (bonding pads; pads) provided on the upper surface are connected by wires, and the semiconductor chip, wires, and inner ends of leads are sealed with a resin package. Regarding the LOC structure, Nikkei BP's "Nikkei Microdevice" February 1991 issue, February 1st,
P89 to P97 and JP-A-2-246125.

In the LOC structure, bonding pads are arranged along the center of the semiconductor chip, and bus bar leads as power supply lines and ground lines are arranged on both sides of this bonding pad row via insulating tapes. ing. Also, the inner end portions of the leads, which will be signal lines, are aligned on the semiconductor chip outside the bus bar leads, and are fixed to the semiconductor chip with an insulating tape. The bonding pad is connected to the bus bar lead and the inner end of the lead by a conductive wire.
The bus bar leads and other inner ends of the leads are adhered to the upper surface of the semiconductor chip via an insulating tape.

[0004]

Most of the semiconductor devices using a lead frame fix a semiconductor chip on a central support plate and make the tip (inner end) of the lead face near the semiconductor chip. The portion and the electrode of the semiconductor chip are electrically connected with a wire, and then the support plate, the semiconductor chip, the wire and the inner end portion of the lead are covered with a package made of a resin. For this reason, the electrodes of the semiconductor chip extend along the peripheral edge of the semiconductor chip, and the package becomes large.

The semiconductor device having the LOC structure has a structure in which the tip portions of the leads are stacked on the semiconductor chip via an insulating tape in order to cope with the miniaturization of the package.

However, when the conventional LOC lead frame is adopted for the semiconductor chip in which the electrodes are arranged along the periphery of the semiconductor chip, most of the electrodes of the semiconductor chip are located under the leads, and wire bonding is impossible. Will be.

On the other hand, a conventional LO having electrodes arranged in the center
In the C structure semiconductor device, the number of electrodes and leads is limited. For example, in manufacturing a multi-pin (multi-lead) semiconductor device such as a one-chip microcomputer, there is a problem that the degree of freedom in design cannot be obtained.

It is an object of the present invention to provide a semiconductor device having a LOC structure using a semiconductor chip having electrodes provided along the periphery.

Another object of the present invention is to provide a semiconductor device having a LOC structure, which has a high degree of freedom in designing the electrode arrangement position on a semiconductor chip.

Another object of the present invention is to provide a semiconductor device having a LOC structure which can cope with an increase in the number of pins.

[0011] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, (1) a semiconductor chip having an electrode on the main surface, a plurality of leads attached to the main surface of the semiconductor chip via an insulator, and a connection for electrically connecting the lead and the electrode of the semiconductor chip. A semiconductor device comprising a means (wire) and a semiconductor chip, an inner end portion of the lead, and a sealing body made of a resin covering the wire, excluding the outer end of the lead, at least a part of the lead being above the electrode. And a hole through which a wire passes is provided in the lead portion just above the electrode. The electrodes of the semiconductor chip are provided along at least two peripheral edges of the semiconductor chip.

(2) A lead frame which is attached to the main surface of a semiconductor chip having an electrode on the main surface via an insulator, wherein at least a part of the leads located on the semiconductor chip of the lead frame has the above-mentioned structure. A hole through which a wire electrically connecting the electrode of the semiconductor chip and the lead extends is provided at a position corresponding to the electrode of the semiconductor chip.

[0014]

According to the above means (1), even if the lead (a) is located on the electrode of the semiconductor chip, the lead portion on the electrode is provided with a hole for wire bonding. Since the electrodes of the semiconductor chip and the leads can be connected, it is possible to provide a semiconductor device having a LOC structure using the semiconductor chip having electrodes along the periphery.

(B) Since the electrode position of the semiconductor chip may be directly under the lead, it is possible to provide a semiconductor device having a LOC structure with a high degree of freedom in designing the electrode arrangement position.

(C) Since the electrode position of the semiconductor chip may be directly under the lead or at another position, it is possible to provide a semiconductor device having a LOC structure which can cope with the increase in the number of pins.

(D) Since the holes provided in the leads are provided along the peripheral edges of two facing sides of the semiconductor chip, a semiconductor device having a dual line structure can also be provided as an LOC structure.

According to the above-mentioned means (2), since the lead portion corresponding to the electrode is provided with the hole through which the wire passes,
A lead frame for assembling a semiconductor device having electrodes along the periphery of the semiconductor chip.

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

[0020]

1 is a cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing a semiconductor device of the present embodiment with a part cut away, and FIG. FIG. 4 is a perspective view showing a wire bonding portion of an example semiconductor device, FIG. 4 is a plan view of a lead frame used for manufacturing the semiconductor device of this embodiment, and FIG. 5 is a lead frame showing a manufacturing state of the semiconductor device of this embodiment. FIG.

In the present invention, for example, a DRAM (Dynami
A semiconductor device having a LOC structure in which a c Random Access Memory) is incorporated will be described.

As shown in FIGS. 1 and 2, the semiconductor device of the present invention has a structure in which a plurality of leads 2 are respectively projected from both sides of a rectangular-shaped sealing body (package) 1 made of a resin. There is. A semiconductor chip 3 having a rectangular shape is sealed inside the package 1. Although not shown, a DRAM is formed on the semiconductor chip 3. As shown in FIG. 3, the semiconductor chip 3 is provided with a plurality of electrodes (bonding pads; pads) 4 (only one is shown in FIG. 3) arranged side by side along the periphery. Although not shown, the surface of the electrode 4 is silver-plated in order to improve the wire bonding performance.

The leads 2 extend on both sides of the package 1 as shown in FIGS. The part of the lead 2 protruding from the package 1 is the outer lead 5.
And has a J-bend structure.

The portions of the leads 2 (the inner leads 6) that enter the package 1 have their tip portions extending in parallel, and an insulator, that is, an adhesive insulating tape 7 is provided.
It is attached to the semiconductor chip 3 via.

The inner leads 6 are structured to extend over the respective electrodes 4 of the semiconductor chip 3. Then, as shown in FIG. 3, a hole 9 having the same size as that of the electrode 4 is provided in the lead portion just above the electrode 4. That is, the semiconductor chip 3 used in this embodiment is
It is not a general semiconductor chip for LOC structure but a conventional semiconductor chip in which electrodes 4 are arranged along both sides of the semiconductor chip 3.

The lead 2 is formed by etching or precision pressing an iron-nickel alloy plate or a copper alloy plate.
For example, the width of the lead 2 is 200 μm and the size of the hole 9 is about 90 μm, which is a size capable of wire bonding by the thermocompression bonding method.

Further, as shown in FIG. 3, the electrode 4 of the semiconductor chip 3 and the lead 2 portion on the insulating tape 7 are connected by an electrical connecting means, that is, a wire 10.
One end of the wire 10 is fixed to the electrode 4 made of hard Al or the like, and the other end is the lead 2 on the insulating tape 7.
Since it is fixed to the tip portion of the (inner lead 6), the reliability of wire bonding is increased. Wire 10
Even if it bends at the hole 9 portion and comes into contact with the lead 2, there is no problem because it is a lead portion that is wire-bonded.

Next, a method of manufacturing (assembling) the semiconductor device having the LOC structure of this embodiment will be described with reference to FIGS.

First, the lead frame 1 as shown in FIG.
5 is prepared. This lead frame 15 is 0.1 m
It is formed by etching or patterning a metal plate made of a Fe-Ni alloy or Cu alloy having a thickness of about m by etching or precision pressing. The lead frame 15 has a shape in which a plurality of unit lead patterns are arranged in series in one direction. The unit lead pattern includes a pair of outer frames 16 extending in parallel with each other, and a pair of inner frames 1 connecting the pair of outer frames 16 and extending in a direction orthogonal to the outer frame 16.
It is formed in a frame 18 formed by 7 and 7.

On the other hand, a plurality of leads 2 extend from the inside of the inner frame 17 of the frame 18 toward the center of the frame 18.
These leads 2 extend in parallel to each other partway and most of them form outer leads, but they are bent from the middle in the direction of the center line of the frame 18 to form the inner leads 6 of a cantilever structure. doing.

Each inner lead 6 has a hole 9 through which a wire passes. The hole 9 is the semiconductor chip 3
Electrodes (bonding pads) arranged along both sides of
It is located just above 4. This hole 9 has a side of 90 μm
Through hole. The width of the lead 2 is about 200 μm.
The side of the electrode 4 of the semiconductor chip 3 is also 90 μm.

The outer leads 5 are connected to each other by a dam 19 extending in parallel with the inner frame 17. The dam 19 functions as a dam that prevents the melted resin from flowing out at the time of resin molding in a later step and also as a strength member. The outer frame 16 is provided with guide holes 20 and 21. These guide holes 20 and 21 are used as guides for transferring and positioning the lead frame 15.

Next, the lead frame 15
As shown in FIG. 5, is superposed on the main surface of the semiconductor chip 3 and attached via an insulating tape (insulator) 7.
The insulating tape 7 is, for example, a double-sided adhesive tape having a thickness of about 80 μm, and the tips of the leads 2 extending from both inner frames 17, that is, the tips of the inner leads 6 are attached to the semiconductor chip 3. In this case, the assembly is performed such that the center of the hole 9 provided in each lead 2 is located at the center of the electrode 4 of the semiconductor chip 3.

Next, the tip of the wire 10 is fixed to the electrode 4 below the hole 9 provided in the lead 2 by the thermocompression bonding device. After that, the bonding tool holding the wire rises while pulling out the wire 10 from the tip of the bonding tool and comes out of the hole 9. The bonding tool removed from the hole 9 moves to the tip side of the inner lead 6 and descends, and the wire 10 is thermocompression bonded to the lead portion on the insulating tape 7 to cut the wire (see FIG. 3). The wire bonding may be performed by an ultrasonic thermocompression bonding device.

After the connection between each electrode 4 and the tips of the inner leads 6 is completed, the package 1 is formed by transfer molding as shown by the two-dot chain line and the solid line in FIG.

Next, unnecessary lead frame portions such as the dam 19 are cut and removed, and the lead 2 portions protruding from the package 1, that is, the outer leads 5 are formed into a desired shape. For example, as shown in FIG. A semiconductor device is manufactured as a J-bend structure.

The LOC structure semiconductor device manufactured using the lead frame of this embodiment has the following effects.

(1) Even if the lead 2 is located on the electrode (bonding pad) 4 of the semiconductor chip 3, the electrode 4
A hole 9 for wire bonding is provided on the upper lead portion.
Since the electrodes are provided, the connection between the electrode 4 of the semiconductor chip 3 and the lead 2 can be realized, and it is possible to provide the semiconductor device of the LOC structure using the semiconductor chip 3 having the electrode 4 along the peripheral edge. it can. Therefore, even in the case of the semiconductor chip 3 having the electrodes 4 along the periphery, L
With the OC structure, the size of the semiconductor chip or the size of the package can be reduced.

(2) Since the position of the electrode 4 of the semiconductor chip 3 may be right under the lead 2, it is possible to provide a semiconductor device of LOC structure having a high degree of freedom in designing the electrode arrangement position.

(3) Since the position of the electrode 4 of the semiconductor chip 3 may be directly under the lead 2 or at another position, it is possible to provide a semiconductor device having a LOC structure capable of coping with an increase in the number of pins. You can

(4) Since the holes 9 provided in the leads 2 are provided along the peripheral edges of two facing sides of the semiconductor chip 3, a semiconductor device having a dual line structure can also be provided as an LOC structure.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

FIG. 6 is a schematic view showing the relationship between the leads and the electrodes of the semiconductor chip in the semiconductor device having the LOC structure which is another embodiment of the present invention. As shown in the figure, some of the leads 2 are not provided with holes 9. Also,
This is an example in which the electrode 4 is arranged between the leads 2 and the electrode 4 is arranged along the center of the semiconductor chip 3.

That is, in this embodiment, the semiconductor chip 3 having the electrode 4 on the main surface thereof and a plurality of semiconductor chips 3 mounted on the main surface of the semiconductor chip 3 via an insulator (insulating tape 7 shown by dots) are attached. The lead 2, the connecting means (the wire 10) for electrically connecting the lead 2 and the electrode 4 of the semiconductor chip 3, and the semiconductor chip 3, the inner end portion of the lead 2 except the outer end of the lead 2. , Wire 10
And a sealing body (package) 1 made of a resin for covering at least some of the leads 2 above the electrode 4, and the wire 10 is provided on the lead 2 portion directly above the electrode 4. Is provided with a hole 9 through which In this embodiment, the same effect as the above embodiment can be obtained.

Further, as another embodiment, the same effect as the above embodiment can be obtained even if the hole through which the wire passes has another shape such as a circle.

The holes may be filled with a conductive substance such as solder to electrically connect the electrodes of the semiconductor chip to the leads.

Further, in the above-described embodiment, the structure is such that the leads are projected from the two opposite sides of the package. However, the same effect as in the above-described embodiments can be obtained by another example, for example, the structure in which the leads are projected from four sides of the package. can get.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the case of application to M has been described, the present invention is not limited to this, and can be applied to, for example, another IC manufacturing technology. The present invention can be applied at least to a technique for connecting electrodes and leads of a semiconductor chip by an electrical connection means such as wire bonding.

[0049]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Even if the lead is located on the electrode of the semiconductor chip, the lead portion on the electrode is provided with a hole for wire bonding, so that the electrode of the semiconductor chip is connected to the lead. Will be realized,
LO using a semiconductor chip having electrodes along the periphery
A semiconductor device having a C structure can be provided. Therefore, it is possible to cope with the large area of the semiconductor chip and the miniaturization of the package.

(2) Since the electrode position of the semiconductor chip may be right under the lead, it is possible to provide a semiconductor device having a LOC structure with a high degree of freedom in designing the electrode arrangement position.

(3) Since the electrode position of the semiconductor chip may be directly under the lead or may be at another position, it is possible to provide a semiconductor device having a LOC structure capable of coping with an increase in the number of pins.

(4) Since the holes provided in the leads are provided along the peripheral edges of two facing sides of the semiconductor chip, a semiconductor device having a dual line structure can be provided as the LOC structure.

(5) Since the lead portion corresponding to the electrode is provided with the hole through which the wire passes, it is possible to provide a lead frame for assembling a semiconductor device having the electrode along the periphery of the semiconductor chip.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a state in which a part of the semiconductor device of this embodiment is cut away.

FIG. 3 is a perspective view showing a wire bonding portion of the semiconductor device of this embodiment.

FIG. 4 is a plan view of a lead frame used for manufacturing the semiconductor device of this embodiment.

FIG. 5 is a plan view of a lead frame or the like showing a manufacturing state of the semiconductor device of this embodiment.

FIG. 6 is a schematic view showing a relationship between leads and electrodes of a semiconductor chip in a semiconductor device having a LOC structure which is another embodiment of the present invention.

[Explanation of symbols]

1 ... Package, 2 ... Lead, 3 ... Semiconductor chip, 4 ...
Electrodes, 5 ... Outer leads, 6 ... Inner leads, 7 ...
Insulating tape, 9 ... Hole, 10 ... Wire, 15 ... Lead frame, 16 ... Outer frame, 17 ... Inner frame, 18 ... Frame, 19 ... Dam, 20, 21 ... Guide hole.

Claims (5)

[Claims] 1. A semiconductor chip having an electrode on a main surface, a plurality of leads attached to the main surface of the semiconductor chip via an insulator, and a connection for electrically connecting the lead and the electrode of the semiconductor chip. And a semiconductor encapsulant excluding the outer ends of the leads and covering the semiconductor chip, the inner end portions of the leads, and a connecting means, wherein at least some of the leads are above the electrodes. A semiconductor device characterized in that a hole through which a connecting means passes is provided in a lead portion directly above the electrode. 2. The semiconductor device according to claim 1, wherein the hole is provided with a hole through which a conductive wire passes. 3. The semiconductor device according to claim 1, wherein the electrodes of the semiconductor chip are provided along at least two peripheral edges of the semiconductor chip. 4. A lead frame which is attached to a main surface of a semiconductor chip having an electrode on the main surface via an insulator, wherein at least some of the leads located on the semiconductor chip of the lead frame have the semiconductor. A lead frame, characterized in that a hole is provided at a position corresponding to the electrode of the chip, and a connecting means for electrically connecting the electrode of the semiconductor chip and the lead is provided. 5. The semiconductor device according to claim 4, wherein the hole is provided with a hole through which a conductive wire passes.