JPH09213808A - Clock distribution circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the wiring area by employing a small-area structure of a clock wiring which has a forward wiring extending from one end point to a loop point and a backward wiring extending backward from the loop point to a free end, and then driving the end point of the forward wiring by a clock buffer. SOLUTION: A clock wiring has a forward wiring 3 extending from an output terminal A of a clock buffer 1 via the vicinity of flip-flops 11, 12, 13 to a loop point B, and a backward wiring 4 extending from the loop point B along the forward wiring 3 to a free end C. A clock branch circuit 21 receives clock signals from a point P1 on the forward wiring 3 and a point P2 on the backward wiring 4. When the sum of time integral values of both clock signals is equal to a time integral value for one pulse of one of the clock signals, the clock branch circuit 21 supplies the transitive clock signal to the flip-flop 11. Similarly, a clock branch circuit 22 receives clock signals from a point P1' and a point P2', and supplies the transitive clock signal to the flip-flops 12, 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit for distributing a clock signal to a plurality of storage elements in a synchronous sequential circuit.

[0002]

2. Description of the Related Art A synchronous sequential circuit is a logic circuit having storage elements such as flip-flops and delay elements which operate in synchronization with a clock signal. In an LSI (Large Scale Integrated Circuit) equipped with such a synchronous sequential circuit, a clock signal must be distributed to all storage elements distributed on a chip with a minimum time difference. The time difference between clock signals is called clock skew, and a clock distribution circuit with zero clock skew is required.

A well-known grid type clock distribution circuit is mainly used in a gate array. Clock wiring is laid in a mesh shape on the entire surface of the chip, and the mesh wiring is driven by a clock buffer arranged around the chip or in the center of the mesh. However, there is a problem in that the electrostatic capacitance attached to the clock wiring becomes large. Further, a well-known tree-type clock distribution circuit forms a clock wiring having a tree structure in which a clock buffer is used as a starting point, that is, a root, and each flip-flop is used as an end point of a branch. The auxiliary buffer is inserted so that the delays are balanced, but there is a problem that it is difficult to design and adjust.

In Japanese Patent Laid-Open No. 4-229634, as a clock distribution circuit that solves the problems of the above-mentioned methods, two clock wirings adjacent to each other are laid in parallel on a chip so as to draw a loop, and one of them is laid in parallel. A circuit is disclosed in which one end of a clock wiring is driven by one clock buffer and the other end of the other clock wiring is driven by another clock buffer. 2 at any position
A clock branch circuit is connected to the clock wiring of the book, and the clock branch circuit mixes and buffers the clock signals on both wirings. It is said that clock skew can be reduced by supplying a clock signal obtained by mixing two clock signals having a delay difference to the flip-flop. The disclosed clock branch circuit is composed of two resistors for obtaining an intermediate voltage of a clock signal on both wirings, and a PMOS transistor and an NMOS transistor each having a gate to which the intermediate voltage is applied. CMO consisting of both transistors
The mixed clock signal is taken out from the S inverter.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the clock distribution circuit disclosed in Japanese Patent No. 634, since two clock wirings form a double loop, there is a problem that the area occupied by the wirings becomes large. Further, in the clock branch circuit, the clock signals on the two wires are respectively connected to the PMOS transistor and the NM via the resistors.
Since it is applied to the common gate of the OS transistor, there is a problem that it is easily affected by noise.

An object of the present invention is to provide a clock distribution circuit having a reduced wiring area.

Another object of the present invention is to provide a clock distribution circuit resistant to noise.

[0008]

According to a first clock distribution circuit of the present invention, a forward wiring that reaches from one end point to a turning point and a return wiring that goes backward from the turning point along the forward wiring and reaches a free end. The small area structure of the clock wiring having the above is adopted, and the end point of the outgoing wiring is driven by the clock buffer. Moreover, when the sum of the time integrated value of the first clock signal on the forward wiring and the time integrated value of the second clock signal on the backward wiring becomes equal to the time integrated value of one pulse of one clock signal. A clock branch circuit having a function of transiting the third clock signal is adopted.

According to the first clock distribution circuit of the present invention, the clock buffer supplies the original clock signal to the end point of the outgoing line. The first clock signal on the forward wiring has a delay with respect to the original clock signal, and the second clock signal on the backward wiring has a delay larger than that of the first clock signal. The clock branch circuit transitions the third clock signal in response to the time integration value of each of the first and second clock signals having the delay difference. Therefore, the delay of the third clock signal with respect to the original clock signal is constant no matter where the first and second clock signals are taken out from on the clock wiring. That is, the clock skew is reduced. Moreover, the noise resistance performance is improved by using the time integral value of the signal.

A second clock distribution circuit of the present invention is a clock wiring having a main wiring of the longest path that reaches the farthest storage element from the output terminal of the clock buffer, and a plurality of branch wirings that reach other storage elements. Adopting a small area structure, a part of each of the plurality of branch wirings has a high resistance wiring layer or a high capacitance so that the delay of the clock signal of the main wiring is equal to the delay of each clock signal of the plurality of branch wirings. It is composed of a wiring layer.

According to the second clock distribution circuit of the present invention, by selecting the wiring impedance of each branch wiring so that each branch wiring has the same delay as the delay of the main wiring which is the longest path, the clock skew is reduced. Will be reduced. In addition, in designing an LSI, there is an advantage that the wiring impedance can be adjusted after the placement and wiring of the storage element, the clock wiring, etc. are completed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the clock distribution circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a clock distribution circuit of the present invention. In FIG. 1, reference numeral 1 denotes a layout area having a large number of flip-flops that form a synchronous sequential circuit. In order to simplify the explanation, three flip-flops 1 are provided in the layout area 1.
1, 12, 13 are shown. Reference numeral 2 is a clock buffer for introducing the external clock signal CLK as it is into the layout area 1 as an original clock signal.
The clock wiring includes a forward wiring 3 that reaches the turning point B from the output terminal A of the clock buffer 1 via the vicinity of the flip-flops 11, 12, and 13, and a free end that runs backward from the turning point B along the forward wiring 3. It has a return wiring 4 which reaches to C. Reference numeral 21 is a clock branch circuit arranged near one flip-flop 11, and 22 is a clock branch circuit arranged near the other two flip-flops 12 and 13. One clock branch circuit 21 receives clock signals from both the point P1 on the forward wiring 3 and the point P2 on the return wiring 4, and the sum of the time integrated values of both clock signals is the sum of one clock signal. A clock signal that transitions when it becomes equal to the time integrated value for one pulse is supplied to the flip-flop 11. The other clock branch circuit 22 receives clock signals from both the point P1 'on the forward wiring 3 and the point P2' on the return wiring 4, and the sum of the time integrated values of both clock signals is one clock. The clock signal that transitions when it becomes equal to the time integrated value of one pulse of the signal is supplied to the flip-flops 12 and 13.

In FIG. 1, points P1 and P2 are close to the output terminal A of the clock buffer 1, and points P1 'and P2' are close to the folding point B. The clock signal at the point P1 has a delay with respect to the original clock signal at the output terminal A of the clock buffer 1. Points P1, P1 ',
The delay of the clock signal with respect to the original clock signal increases in the order of P2 ′ and P2.

FIG. 2 is a circuit diagram showing an internal configuration example of the clock branch circuit 21 in FIG. In FIG. 2, IN1
Is a first input terminal for inputting a clock signal (first clock signal) at a point P1 on the forward wiring 3, IN
2 is a clock signal at the point P2 on the return wiring 4 (second
Second input terminal for inputting the clock signal
UT is an output terminal for supplying a clock signal (third clock signal) to the flip-flop 11. The first clock signal is supplied to the internal node (whose voltage is VIN) via the buffer 31 and the diode 32 for preventing backflow. The second clock signal is supplied to the internal node via the buffer 33 and the backflow prevention diode 34. Another buffer 35 is interposed between the internal node and the output terminal OUT. Further, a capacitor 36 and an NMO are provided between the internal node and the ground.
The S transistor 37 is interposed in parallel. The gate of the NMOS transistor 37 is connected to the output terminal OUT via the resistor 38. The internal configuration of the other clock branch circuit 22 in FIG. 1 is also the same.

FIG. 3 is a timing chart showing the operation of the clock branch circuit 21 of FIG. The first clock signal supplied to the first input terminal IN1 has a pulse width T
And a delay DLP1 with respect to the original clock signal. The time integrated value of one pulse of the first clock signal is S1 + S2. Further, the second clock signal supplied to the second input terminal IN2 has a delay DLP2 with respect to the original clock signal. Here, DLP1 <DLP2. When the first clock signal rises from the "L" level to the "H" level, charging of the capacitor 36 starts via the buffer 31 and the diode 32, and the voltage VIN of the internal node starts to rise from 0V. After that, when the second clock signal rises from the "L" level to the "H" level, the capacitor 36 is charged through the buffer 33 and the diode 34, and the voltage VIN at the internal node starts to rise rapidly. Then, when the time integration value of the second clock signal reaches S2, the voltage VIN of the internal node exceeds the threshold voltage Vt of the buffer 35. That is, at time TS, the sum of the time integrated value S1 of the first clock signal and the time integrated value S2 of the second clock signal reaches the time integrated value S1 + S2 of one pulse of one clock signal, and the output terminal OUT
The third clock signal output from the output terminal transits from the "L" level to the "H" level. When the third clock signal rises in this way, the "H" level voltage is applied to the gate of the NMOS transistor 37 via the resistor 38, so that the NMOS transistor 37 turns on. As a result, the discharge of the capacitor 36 starts. However, since the capacitor 36 is continuously charged while one of the first and second clock signals holds the “H” level, the voltage VIN of the internal node immediately increases the threshold voltage of the buffer 35. It does not fall below the value voltage Vt.
In FIG. 3, at time TE, the voltage VIN of the internal node
Falls below the threshold voltage Vt of the buffer 35, and the third clock signal output from the output terminal OUT transits from "H" level to "L" level. The pulse width of the third clock signal can be adjusted by changing the characteristics of the NMOS transistor 37.

As can be seen from FIG. 3, in one clock branch circuit 21, the third clock signal for the original clock signal is used.
The delay DL of the clock signal is expressed by DL = DLP2 + {T- (DLP2-DLP1)} / 2 (1). Similarly, in the other clock branch circuit 22, the delay DL 'of the output clock signal with respect to the original clock signal is represented by DL' = DLP2 '+ {T- (DLP2'-DLP1')} / 2 (2). . Here, DLP1 'is the delay of the clock signal at the point P1' on the forward wiring 3 with respect to the original clock signal, and DLP2 'is the delay of the clock signal at the point P2' on the return wiring 4 with respect to the original clock signal. .

In FIG. 1, the length of the outgoing wiring 3 from the output terminal A of the clock buffer 2 to the turning point B is 10 m.
m, return wiring 4 from the turning point B to the free end C of the return wiring 4
Is 10 mm, the length of each of the forward wiring 3 and the return wiring 4 from the turning point B to the points P1 and P2 is 8 mm, and the forward wiring 3 and the returning wiring 4 from the turning point B to the points P1 ′ and P2 ′ The length of each is 2 mm. Further, each of the forward wiring 3 and the backward wiring 4 is an aluminum wiring having a line width of 0.8 μm, and the resistance per unit length thereof is 120Ω.
/ Mm, the capacitance per unit length is 0.1 pF /
mm (that is, 10 ⁻⁴ nF / mm). At this time,
Approximately, DLP1 = (120 × 2) × (10 ⁻⁴ × 20) = 0.4
8 ns DLP1 ′ = (120 × 8) × (10 ⁻⁴ × 20) = 1.
92 ns DLP2 ′ = (120 × 12) × (10 ⁻⁴ × 20) =
2.88 ns DLP2 = (120 × 18) × (10 ⁻⁴ × 20) = 4.
32 ns. If T = 6.0 ns, then from the above equations (1) and (2), DL = 4.32 + {6.0− (4.32−0.48)}
/2=5.4 ns DL '= 2.88 + {6.0- (2.88-1.9)
2)} / 2 = 5.4 ns.

As is clear from the above description of the numerical examples,
A clock having the configuration shown in FIG. 2 is provided with a first clock signal extracted from the forward wiring 3 and a second clock signal extracted from the return wiring 4 at an arbitrary distance L (0 <L <10 mm) from the turning point B. When input to the branch circuit, a third clock signal having a constant delay of 5.4 ns with respect to the original clock signal is obtained. That is, according to the clock distribution circuit of FIG. 1, approximately zero clock skew can be realized. Further, since the folded structure of the clock wiring is adopted, the wiring area is reduced as compared with the case of the conventional double loop. Moreover, capacitors are provided in the clock branch circuits 21 and 22 so as to reduce the clock skew by using the time integral value of the clock signal on the forward wiring 3 and the time integral value of the clock signal on the backward wiring 4. Since 36 is introduced, a clock distribution circuit that is resistant to noise can be realized.

The forward wiring 3 and the backward wiring 4 in FIG.
This is easily obtained by dividing one wide clock wiring reaching the point B via the vicinity of the plurality of flip-flops 11, 12, 13 into two in the longitudinal direction thereof.

The circuit of FIG. 4 is constructed by inserting an auxiliary buffer 41 on the clock wiring in the vicinity of the turning point B of the clock distribution circuit of FIG. By inserting the auxiliary buffer 41, the capacitance of the clock wiring is halved. That is, the delay in the auxiliary buffer 41 is set to 0.5 ns.
Then, approximately, DLP1 = (120 × 2) × (10 ⁻⁴ × 10) = 0.2
4 ns DLP1 ′ = (120 × 8) × (10 ⁻⁴ × 10) = 0.
96 ns DLP2 ′ = (120 × 10) × (10 ⁻⁴ × 10) +
0.5+ (120 × 2) × (10 ⁻⁴ × 10) = 1.94
ns DLP2 = (120 × 10) × (10 ⁻⁴ × 10) +0.
5+ (120 × 8) × (10 ⁻⁴ × 10) = 2.66 ns. If T = 6.0 ns, then from the above equations (1) and (2), DL = 2.66 + {6.0− (2.66−0.24)}
/2=4.5 ns DL '= 1.94 + {6.0- (1.94-0.9)
6)} / 2 = 4.5 ns.

That is, according to the clock distribution circuit of FIG. 4, an arbitrary distance L (0 <L <10 m from the turning point B is obtained.
At the position m), the use of the first clock signal extracted from the forward wiring 3 and the second clock signal extracted from the return wiring 4 causes a constant delay of 4.5 n with respect to the original clock signal.
A third clock signal with s is obtained. Moreover, the delay of the third clock signal is 5.4 ns in the case of FIG.
It is reduced compared to.

An arbitrary distance D (0
At the position of <D <10 mm)
Even if the second auxiliary buffers are inserted on the sub-wiring 4 respectively, the same effect as in the case of FIG. 4 can be obtained.

The circuit shown in FIG. 5 comprises a ground wire 5 sandwiched between the forward wiring 3 and the backward wiring 4 of the clock distribution circuit shown in FIG. Even if the frequency of the external clock signal CLK is high, due to the shielding effect of the ground wire 5, the forward wiring 3
It is possible to prevent the interference of the clock signal between the return wiring 4 and the return wiring 4.
The ground wire 5 also has the effect of reducing the influence of noise and suppressing the increase of wiring impedance at high frequencies.

The forward wiring 3, the return wiring 4 and the ground wire 5 in FIG. 5 are composed of a plurality of flip-flops 11, 12, 13.
It can be easily obtained by dividing one wide clock wiring reaching the point B via the vicinity of to the three in the longitudinal direction and grounding the central wiring.

The circuit of FIG. 6 has a frequency divider 45 for supplying a clock signal having a reduced frequency of the external clock signal CLK to the clock buffer 2 and each clock branch circuit 2.
Frequency up converters 51 and 52 for increasing the frequency of the output clock signals 1 and 22 to the same frequency as the external clock signal CLK are added to the clock distribution circuit of FIG.

FIG. 7 is a circuit diagram showing an internal configuration example of the frequency divider 45 in FIG. In FIG. 7, CIN1 is an input terminal for inputting an external clock signal CLK, COUT
Reference numeral 1 is an output terminal for supplying a clock signal whose frequency is divided by ½ to the clock buffer 2. Frequency divider 45 of FIG.
Is composed of one JK flip-flop 60,
The J input terminal and the K input terminal are connected to the power supply VDD, the clock input terminal is connected to the input terminal CIN1 of the frequency divider 45,
The Q output terminals are respectively connected to the output terminals COUT1 of the frequency divider 45.

FIG. 8 is a timing chart showing the operation of the frequency divider 45 of FIG. The external clock signal CLK supplied to the input terminal CIN1 changes from "H" level to "L"
The clock signal supplied from the output terminal COUT1 to the clock buffer 2 makes a transition each time the level changes to the level. That is, the clock signal obtained by reducing the frequency of the external clock signal CLK by half is supplied to the clock buffer 2.
Therefore, the clock signal whose frequency is divided by ½ is applied to the forward wiring 3
And it will be transmitted on the return wiring 4.

FIG. 9 is a circuit diagram showing an internal configuration example of the frequency up converter 51 in FIG. In FIG.
CIN2 is an input terminal for inputting a clock signal supplied from the clock branch circuit 21, and COUT2 is an output terminal for supplying a clock signal having a frequency multiplied to the flip-flop 11. The clock signal supplied to the input terminal CIN2 is the first signal of the exclusive OR gate 61.
And the second input terminal of the exclusive OR gate 61 via the resistor 62. Further, a capacitor 63 is interposed between the second input terminal of the exclusive OR gate 61 and the ground. The output terminal of the exclusive OR gate 61 is connected to the output terminal COUT2 of the frequency up converter 51. The internal configuration of the other frequency up-converter 52 in FIG. 6 is also the same.

FIG. 10 is a timing chart showing the operation of the frequency up converter 51 shown in FIG. When the voltage of the input terminal CIN2 is “L” level and the charging voltage of the capacitor 63 is 0V, the output terminal COUT
The voltage of 2 is "L" level. When the voltage of the input terminal CIN2 rises from "L" level to "H" level,
Charging of the capacitor 63 starts via the resistor 62. However, since the terminal voltage of the capacitor 63 rises slowly, the voltage of the output terminal COUT2 rises from "L" level to "H" level. When the charging voltage of the capacitor 63 reaches the “H” level, the output terminal COUT
The voltage of 2 falls from "H" level to "L" level. Next, when the voltage of the input terminal CIN2 falls from the "H" level to the "L" level, the capacitor 63 starts discharging through the resistor 62. However, the capacitor 63
The output voltage of the output terminal CO
The voltage of UT2 rises from "L" level to "H" level. When the terminal voltage of the capacitor 63 eventually reaches the “L” level, the voltage of the output terminal COUT2 falls from the “H” level to the “L” level and returns to the original state.
By repeating the above-described operation, the clock signal obtained by doubling the frequency of the clock signal supplied from the clock branch circuit 21, that is, the clock signal having the same frequency as the frequency of the external clock signal CLK becomes the flip-flop 1.
1 is supplied.

According to the clock distribution circuit of FIG. 6, since the high frequency clock signal does not spread over a wide range,
This has the effect of reducing the power consumption of the circuit.

FIG. 11 is a block diagram showing another configuration example of the clock distribution circuit of the present invention. In FIG. 11, 1
Shows a layout area having a large number of flip-flops that form a synchronous sequential circuit. In order to simplify the description, four flip-flops 11, 12, 13, 14 are shown in the layout area 1. 2
Is a clock buffer for introducing the external clock signal CLK as it is into the layout area 1 as an original clock signal. Clock wiring is clock buffer 1
Furthest from the output terminal A of the flip-flops 12, 13
It has a main wiring 6 of the longest path reaching to and a plurality of branch wirings 7 and 8 branched from the main wiring 6 to reach the other flip-flops 11 and 14, respectively. The main wiring 6, for example, is entirely formed of an aluminum wiring layer. The branch wirings 7 and 8 are arranged so that the delay of the clock signal on the main wiring 6 and the delay of the clock signal on the branch wirings 7 and 8 are equal.
Part of each of the above is formed of high resistance wiring layers 73 and 76 made of, for example, polysilicon, and the other is formed of an aluminum wiring layer. Reference numerals 71, 72, 74 and 75 in FIG. 11 denote aluminum wiring layers and high resistance wiring layers 73, 7 respectively.
6 shows a contact for connection with 6.

FIG. 12 is a flow chart for automatic design of the clock distribution circuit of FIG. Step 10
1, the clock buffer 2 in the layout area 1,
Flip-flops 11, 12, 13, 14 and the like are arranged, and the route of the clock wiring having the main wiring 6 and the branch wirings 7, 8 is determined. At this point, the clock wiring is treated as if it is entirely composed of an aluminum wiring layer. In step 102, the main wiring 6 of the longest route from the output terminal A of the clock buffer 1 to the furthest flip-flops 12 and 13 of the routes of the clock wiring is searched. In step 103, the delay of the clock signal of the searched main wiring 6, that is, the maximum clock delay Tm is calculated. This maximum delay Tm depends on the length of the main wiring 6, the resistance per unit length, and the electrostatic capacitance per unit length. Then, the required resistance value of each branch wiring 7 and 8 is obtained so that the delay of the clock signal of each branch wiring 7 and 8 becomes equal to the maximum delay Tm. In step 104, each branch wiring 7, so as to realize the obtained resistance value,
A process of changing a part of 8 to the high resistance wiring layers 73 and 76 is performed. Specifically, in the branch wiring 8 near the output terminal A of the clock buffer 1, the long high resistance wiring layer 76 is selected,
Moreover, contacts 74 and 75 for connecting the original aluminum wiring layer and the high resistance wiring layer 76 are formed. Further, the branch wiring 7 far from the output terminal A of the clock buffer 1
Then, the short high resistance wiring layer 73 is selected, and the contacts 71 and 72 for connecting the original aluminum wiring layer and the high resistance wiring layer 73 are generated. In step 105, the placement and routing result obtained as described above is output.

According to the clock distribution circuit of FIG. 11, zero clock skew can be easily realized with the small area structure of the clock wiring having the main wiring 6 and the plurality of branch wirings 7 and 8. The high resistance wiring layers 73 and 76 in FIG. 11 may be replaced with high capacitance wiring layers so that the delay of the clock signal of the main wiring 6 and the delay of the clock signal of the branch wirings 7 and 8 become equal. Good.

FIG. 13 is a plan view showing a high capacity wiring layer which replaces the high resistance wiring layer 73 in FIG. FIG. 14 shows a cross-sectional structure of the high capacity wiring layer 81 in FIG. In FIG. 14, 91 is a semiconductor substrate, 92 is a high dielectric constant 4.
SiO ₂ film having 0, 93 has a low dielectric constant of 3.3 to 3.8.
Is a SiOF film having Si on the semiconductor substrate 91
The O ₂ film 92 is formed on the SiO ₂ film 92 by the high-capacity wiring layer 8
The aluminum wiring layers that form the element 1 are formed. Further, the SiOF film 93 is formed on the semiconductor substrate 91.
However, aluminum wiring layers that form the branch wiring 7 are formed on the SiOF film 93. SiO ₂ film 9
2 is formed thinner than the SiOF film 93. The branch wiring 7 and the high capacity wiring layer 81 are connected by contacts 71 and 72.

According to the structure shown in FIGS. 13 and 14, the capacitance per unit length between the high capacity wiring layer 81 and the semiconductor substrate 91 is equal to the unit length between the branch wiring 7 and the semiconductor substrate 91. It is larger than the capacitance per hit. Moreover, the former capacitance value can be adjusted by adjusting the thickness of the SiO ₂ film 92. Specifically, the closer the branch wiring is to the output terminal of the clock buffer, the smaller the thickness of the SiO ₂ film below the high capacity wiring layer is set.

[0037]

As described above, according to the clock distribution circuit of the present invention, since the folded structure of the clock wiring is adopted, the wiring area can be reduced. Moreover, since the clock skew is reduced by using the time integration value of the clock signal on the forward wiring and the time integration value of the clock signal on the backward wiring, it is possible to provide a clock distribution circuit resistant to noise.

Further, according to another clock distribution circuit of the present invention, a clock wiring having a tree structure having a main wiring and a plurality of branch wirings is adopted, and a part of each branch wiring is provided with a high resistance wiring layer or Since the clock skew is reduced by using the high capacity wiring layer, the wiring area is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a clock distribution circuit of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration example of a clock branch circuit in FIG.

FIG. 3 is a timing chart showing the operation of the clock branch circuit of FIG.

FIG. 4 is a block diagram showing another configuration example of the clock distribution circuit of the present invention.

FIG. 5 is a block diagram showing still another configuration example of the clock distribution circuit of the present invention.

FIG. 6 is a block diagram showing still another configuration example of the clock distribution circuit of the present invention.

7 is a circuit diagram showing an internal configuration example of a frequency divider in FIG.

FIG. 8 is a timing chart showing the operation of the frequency divider of FIG.

9 is a circuit diagram showing an internal configuration example of the frequency up-converter in FIG.

10 is a timing chart showing the operation of the frequency upconverter shown in FIG.

FIG. 11 is a block diagram showing still another configuration example of the clock distribution circuit of the present invention.

12 is a flow chart diagram for automatic design of the clock distribution circuit of FIG.

13 is a plan view showing a high-capacity wiring layer which replaces the high-resistance wiring layer in FIG.

14 is a sectional view taken along the line XIV-XIV of FIG.

[Explanation of symbols]

1 layout area 2 clock buffer 3 forward wiring (clock wiring) 4 return wiring (clock wiring) 5 ground wire 6 main wiring (clock wiring) 7, 8 branch wiring (clock wiring) 11-14 flip-flop (storage element) 21, 22 clock branch circuit 31, 33, 35 buffer 32, 34 diode 36 capacitor 37 NMOS transistor 38 resistance 41 auxiliary buffer 45 frequency divider 51, 52 frequency up-converter 71, 72, 74, 75 contact 73, 76 high resistance wiring layer 81 High-capacity wiring layer 91 Semiconductor substrate 92 SiO ₂ film 93 SiOF film

Claims (9)

[Claims] 1. A clock distribution circuit for distributing a clock signal to a plurality of storage elements in a synchronous sequential circuit, wherein the clock signal reaches from one end point to a turnaround point via the vicinity of the plurality of storage elements. A clock wiring having a wiring and a return wiring that goes backward from the folding point along the forward wiring and reaches a free end, and supplies an original clock signal to an end point of the forward wiring according to a supplied clock signal Clock buffer, a first clock signal on the forward wiring, which is arranged in the vicinity of a corresponding storage element of the plurality of storage elements and has a delay with respect to the original clock signal; A second clock signal on the return line having a delay greater than a clock signal, respectively, and each of the first clock signal
Corresponding to the third clock signal which transits when the sum of the time integrated value of the clock signal and the time integrated value of the second clock signal becomes equal to the time integrated value of one pulse of one clock signal. And a plurality of clock branch circuits for supplying the clock elements to the storage element. 2. The clock distribution circuit according to claim 1, wherein each of the plurality of clock branch circuits charges one capacitor, and charges the capacitor according to a first clock signal on the outgoing line. Means for charging the capacitor in response to the second clock signal on the return wiring, and for transitioning the third clock signal when the charging voltage of the capacitor reaches a predetermined voltage. And a clock distribution circuit. 3. The clock distribution circuit according to claim 2, wherein each of the plurality of clock branch circuits further includes means for discharging the capacitor in response to the transitioned third clock signal. Characteristic clock distribution circuit. 4. The clock distribution circuit according to claim 1, further comprising an auxiliary buffer inserted on the clock wiring in the vicinity of a turning point of the clock wiring. 5. The clock distribution circuit according to claim 1, further comprising a ground wire sandwiched between the forward wiring and the backward wiring of the clock wiring. 6. The clock distribution circuit according to claim 1, wherein a frequency divider for supplying a clock signal having a reduced frequency of the supplied external clock signal to the clock buffer, and a plurality of clock branch circuits, respectively. A clock distribution circuit further comprising a plurality of frequency up-converters interposed between corresponding storage elements for increasing the frequency of the third clock signal to the same frequency as the external clock signal. 7. A clock distribution circuit for distributing a clock signal to a plurality of storage elements in a synchronous sequential circuit, the clock buffer having an output terminal for supplying the clock signal, and the output of the clock buffer. A main wiring of the longest path reaching a farthest storage element from the terminals to the farthest storage element; and a clock wiring having a plurality of branch wirings each reaching other storage elements, the clock signal of the main wiring A clock distribution circuit, wherein a part of each of the plurality of branch wirings is configured by an impedance adjusting layer so that the delay and the delay of the clock signal of each of the plurality of branch wirings become equal. 8. The clock distribution circuit according to claim 7, wherein the impedance adjustment layer is composed of a layer having a higher resistance value than other portions. 9. The clock distribution circuit according to claim 7, wherein the impedance adjustment layer is composed of a layer having a higher capacitance value than other portions.