JPH09219698A - Error correction method for high speed communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an error correction system extended simply by allowing a transmitter side to add an output of an adder circuit and an output of a parity check circuit as redundant bits and allowing a receiver side to compare parity bits and redundant bits of a received signal. SOLUTION: At the transmitter side, an input signal is received and distributed to a coder circuit 2, an arithmetic circuit 3, and a multiplexer circuit 5. The output of the circuit 2 is given to a 2-element sum arithmetic circuit 4, in which a 2-element sum is calculated and the result is multiplexed by the circuit 5 and the result is inserted as the redundant bits in an SOH. Simultaneously the parity bits calculated by the circuit 3 are multiplexed by the circuit 5 and the result is written in the SOH. The output of the circuit 5 is demultiplexed by a demultiplexer circuit 6 to extract error correction coding bits and parity bits and they are given to a syndrome calculation circuit 8, a parity calculation circuit 9 and a memory 7. A comparator circuit 11 compares the output of the circuit 9 with the received parity check bits to locate an error frame. Then the stored signal in a memory 7 is corrected by a correction circuit 17 and the result is outputted. Thus, the correction system with simple and high extension performance is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simple error correction system in a high-speed backbone transmission system.

[0002]

2. Description of the Related Art Conventionally, SONET (Synchronous Opti)
cal Network; Synchronous Optical Network / SDH (Synchrono)
US Digital Hiereachy (Synchronous Digital Hierarchy) describes an error correction method in the literature (WD Gro.).
over and TE Moore, "Design and characteriza
tion of an error-correcting code for the SONE
TSTS-1 tributary ", IEEE Trans., COM-3
8, (4), pp. 467-476, 1990).

FIG. 5 shows a transmission format to which the conventional error correction method is applied. In the conventional example, the SON
Using a Hamming code for the 6264 bits of the payload portion of the STS-1 frame of the ET, 13
A redundant bit is added to a POH (Path Over Head) section. That is, Z3 of the POH portion in FIG.
Redundant bits are added to the Z4 byte. Thereby, one bit in the frame is corrected. In FIG. 5,
FEC stands for Forward Error Correction (Forward Error Correction).
n), SPE (Synchronous Payload Envelope).

[0004]

In the above-mentioned method, when a large-capacity signal is transmitted in the backbone transmission, a new encoding is required, the expandability is poor, and the high-speed operation of the circuit is required. There is a problem that it is done.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide an error correction method which can be easily extended to a large-capacity transmission signal.

[0006]

In order to achieve the above object, the present invention provides an N-multiplexed frame for accommodating an M-bit signal to transmit an (N × M) -bit signal. Error correction coding is performed on each of the signals in each of the frames by a Hamming code, the sum of the redundant bits at the time of coding is added as a redundant bit, and the parity bit for each frame is further added. Is provided to correct an error of 1 bit in the signal in the N-multiplexed frame, and an error correction method is provided.

The present invention calculates a redundant bit and a parity bit by a Hamming code for each cell in cell relay communication for transmitting an M-bit signal as one cell, and after transmitting N arbitrary cells, The feature is that an error of 1 bit in N cells can be corrected by sending the sum of N parity bits and redundant bits of each cell.

According to the present invention, in packet communication in which a signal of maximum M bits is transmitted as one packet, redundant bits by a Hamming code with M bits and parity bits of each packet are calculated for each packet, and the arbitrary bits are calculated. After N packets have been transmitted, the sum of the parity bits of N bits and the redundant bits of each packet is sent to correct a 1-bit error in the N packets.

The encoding circuit of the present invention includes at least two or more Hamming encoding circuits, an adder circuit for calculating the sum of binary operations of outputs from the Hamming encoding circuits, and a parity. A calculation circuit, and the output from the adder circuit and the output from the parity calculation circuit are added as redundant bits.

The decoding circuit of the present invention comprises at least two or more syndrome calculation circuits, an addition circuit for calculating the sum of binary operations of outputs from the syndrome calculation circuits, and a parity calculation circuit. It is characterized in that it is constituted by a comparison circuit for comparing the output from the circuit and the output of the parity calculation circuit with the parity bit and the redundant bit of the received signal.

[0011]

A case will be described in which a signal of M bits per frame is N-multiplexed. The signal of the payload portion of a certain ith frame is converted into an M-dimensional vector A _i = (a _{(i, 1)} ,
a _{(i, 2)} ,... a _{(i, M)} ). At this time, the number of error correction bits for the M-bit signal is set to k, and is represented by a vector B _i = (b _{(i, 1)} , b _{(i, 2)} ,..., B _{(i, k)} ).

Here, when the generator matrix G is decomposed into a unit matrix I and a matrix J for calculating error correction bits, B _i is expressed by the following equation (1) using J and A _i . As is well known, a matrix having a relation of H · G ^T = 0 with the parity check matrix H is called a generator matrix G, and an irreducible trapezoid canonical H matrix (H =
[P Im], where P is, for example, a matrix of m × k, Im is m × m
G = [− P ^T Ik] (where P ^T is a transposed matrix of P and I k is a unit matrix).

B _i = J · A _i (1)

Since the above equation (1) holds for all i, the sum of them is calculated. That is, the following equation (2) holds.

[0015]

[Equation 1]

Signals to be transmitted are redundant with all signals in the payload, the sum of binary operations of error correction bits in all frames (two elements of 0 and 1 and an additive operation modulo 2). Bits, and the parity sum for each frame is inserted as redundant bits.

When one bit error occurs in the transmitted signal, it is possible to recognize which frame is wrong by the parity check bit.

Here, the signal of the payload portion of the signal of the j-th frame of the received signal is represented by C _j = (c _{j, 1,.}
c _{j, 2} , ..., C _{j, m} ), and the received error correction bit is D
= (D ₁ , d ₂ ,..., D _k ). Assuming that an error bit occurs at the p-th bit of the I frame and is represented by a vector E = (0,0,..., 0,1,0,..., 0), the following equation (3) holds. I do.

[0019]

[Equation 2]

From this, by calculating the right side of the above equation (3), it is possible to correct the error of the frame specified by the parity check bit.

[0021]

FIG. 1 is a view for explaining a first embodiment of the present invention. FIG. 2 shows a configuration example of the first embodiment of the present invention.

In the SONET frame format, error correction is performed based on STS-1. S
Since the number of bits in the payload portion of the signal transmitted in TS-1 is 6264 bits, 13 redundant bits are required. At this time, STS-48 is used as a transmission signal.
Is transmitted, and together with the parity check bit, 61
The bit is inserted as a redundant bit into the Z2 byte in the SOH (Section Over Head). As shown in FIG.
TM (Synchronous Transport Module) -0 Performs error correction coding on a signal in a frame by a Hamming code, adds a binary operation sum of redundant bits at the time of coding as a redundant bit, and parity for each frame By adding a bit, the signal is written in the SOH portion of the signal in the N-multiplexed frame (STM-N frame).

Referring to FIG. 2, FIG. 2A shows the transmitting side, and FIG. 2B shows the receiving side. In FIG. 2, 1 is an elastic memory, 2 is an encoded bit calculation circuit, 3 is a parity bit calculation circuit, 4 is a binary sum operation circuit, 5 is a multiplexing circuit, 6 is a separation circuit, 7 is a memory, and 8 is a syndrome. A calculation circuit, 9 is a parity calculation circuit, 10 is an error bit calculation circuit, 11 is a comparison circuit, and 12 is a correction circuit.

On the transmitting side, each of the 48 STS-1 signals is branched into three, one of which is input to an encoding circuit 2 for calculating an error correction code, and one for calculating a parity bit. One is input to the arithmetic circuit 3 and one is
Is input to The output of the error correction coding circuit 2 of 48 calculates the sum by binary sum for each bit, inputs it to the multiplexing circuit 5, and writes it in the SOH section of the STS-48 to be multiplexed. At the same time, the parity bits calculated by the parity bit calculation circuit 3 are input to the multiplexing circuit 5 and written into the SOH of the STS-48 to be multiplexed.

On the receiving side, STS-
48, and separates error-correction coded bits and parity bits. The 48 separated STS-1 signals are input to the syndrome calculation circuit 8, the parity calculation circuit 9, and the memory 7, respectively. Comparing the output of the 48 parity calculation circuit with the received parity check bit,
Identify erroneous frames. At the same time, the sum of the binary operation of the outputs of the 48 syndrome calculation circuits 8 is calculated and compared with the received error correction coded bits to specify the error correction position. Thereafter, the error bit of the received signal written in the memory 7 is corrected and output.

Thus, the error rate of 1E-9 (10 ^-9 ) in the case where no error correction is performed is corrected to 2E-
13 (2 × 10 ⁻¹³ ).

FIG. 3 shows a diagram for explaining a second embodiment of the present invention. AT with 48 byte payload
In M (Asynchronous Transfer Mode) cells, the number of cells in a certain sequence is assumed to be 100. At this time, since 9 bits are required as redundant bits for one cell, an error correction bit and a parity check bit are added to 109 bits of the 101st cell. As a result, 100
Error correction of one bit in a cell becomes possible, and the error rate of the data part is increased from 1E-9 (10 ^-9 ) to 4E-14 (4 × 10
^-14 ) was improved.

FIG. 4 shows a diagram for explaining the third embodiment of the present invention. In a variable length packet in the fiber channel, the payload portion is a maximum of 2112 bytes. When calculating the error correction bit of a packet, the maximum number of payloads of the packet is calculated and
If less than 2 bytes, all missing signal length parts are set to 0
Is calculated as Assuming that the number of packets in a certain sequence is 100, 15 bits are required as redundant bits for one packet. Therefore, 115 bits of redundant bits are added to the 101st packet. This makes it possible for the receiving side to correct a 1-bit error that has occurred in 100 packets, and to increase the error rate of the data section by 1E.
It was improved from −9 (10 ⁻⁹ ) to 2E−12 (2 × 10 ⁻¹² ).

It goes without saying that the method of the present invention can be realized in all communications using packets of variable length other than Fiber Channel.

[0030]

As described above, according to the present invention,
In a large-capacity digital transmission system, a simple and highly expandable error correction method can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a diagram for explaining a second embodiment of the present invention.

FIG. 4 is a diagram for explaining a third embodiment of the present invention.

FIG. 5 is a diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Elastic memory 2 Encoding bit calculation circuit 3 Parity bit calculation circuit 4 Binary sum operation circuit 5 Multiplexer 6 Separation circuit 7 Memory 8 Syndrome calculation circuit 9 Parity calculation circuit 10 Error bit calculation circuit 11 Comparison circuit 12 Correction circuit

Claims (5)

[Claims] 1. A frame accommodating an M-bit signal is represented by N
In a transmission system that multiplexes and transmits a (N × M) -bit signal, Hamming (Hammi
ng) error-correction coding with a code, adding the sum of the redundant bits at the time of coding by binary operation as a redundant bit, and further adding a parity bit for each frame, thereby N multiplexed frames An error correction method characterized in that a 1-bit error in the internal signal can be corrected. 2. In cell relay communication for transmitting an M-bit signal as one cell, redundant bits and parity bits by a Hamming code for each cell are calculated, and after transmission of arbitrary N cells,
An error correction method characterized in that an error of 1 bit in N cells can be corrected by sending a sum of N parity bits and redundant bits of each cell. 3. In packet communication for transmitting a signal of maximum M bits as one packet, Hamming with M bits for each packet.
By calculating the redundant bit by the code and the parity bit of each packet, and after transmitting any N packets, by sending the sum of the N parity bits and the redundant bit of each packet,
An error correction method characterized in that a 1-bit error in N packets can be corrected. 4. At least two Hammings
g) an encoding circuit, an adder circuit that calculates the sum of binary operations of the outputs from the Hamming encoding circuit, and a parity calculation circuit, and the output from the addition circuit and the parity calculation circuit An encoding circuit characterized in that the output of the above is added as a redundant bit. 5. An output circuit comprising: at least two or more syndrome calculation circuits; an adder circuit for calculating the sum of binary operations of outputs from the syndrome calculation circuits; and a parity calculation circuit. A decoding circuit comprising a comparison circuit for comparing an output of the parity calculation circuit with a parity bit and a redundant bit of a received signal.