JPH09218247A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize quick measurement using an output level measuring pattern without increasing the number of test signal input terminals. SOLUTION: Under a state where output butters 22, 24 are fixed to output mode by an output Q from a flip-flop circuit 32 being set by the start of input of test signal and reset by the end of input of test signal, a test signal and an output level measuring pattern generated from the output Q of flip-flop circuit 32 are fed to the output butters 20, 22, 24 and the operation of output butter is inspected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a normal output buffer in a large scale integrated circuit,
The present invention relates to a semiconductor integrated circuit capable of efficiently inspecting operations of a 3-state output buffer and an input / output (I / O) buffer.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, a fault detection or operation test pattern (vector) is diverted in order to measure and test the output levels of its ordinary output buffer, 3-state output buffer and I / O buffer. However, the output level is measured using a pattern that expects an H or L level for the output.

However, in this method, since the vector used for another test is diverted, it takes time until the expected value is output. Further, since the output buffer receives the output of the internal logic circuit, the level change of H and L of the internal node is small, the change of H and L level of the output buffer is small, and the fault detection rate is low. In some cases, there is a problem that an output pin in which the output level of the output buffer cannot be measured occurs.

In order to solve such a problem, Japanese Patent Laid-Open No. 3-226686 discloses a 3-state output buffer and an I / O.
Two kinds of test signals, a control signal for controlling the enable signal of the buffer and an inversion signal for forcibly inverting each output buffer, are prepared, and the three-state output buffer and the three-state output buffer are provided by the control signal. I / O buffer is forced to output mode, and normal output buffer,
The output of the 3-state output buffer and I / O buffer is set to H
There is proposed a semiconductor integrated circuit in which each buffer is forcibly inverted by the inversion signal while being fixed to the level or the L level.

[0005]

However, in the semiconductor integrated circuit proposed in Japanese Patent Laid-Open No. 3-226686, it is necessary to independently input the control signal and the inversion signal to the semiconductor integrated circuit, which is for testing. Since two terminals are required, there is a problem in that the usage efficiency of the terminals is reduced and the circuit area may be increased.

The present invention has been made to solve the above-mentioned conventional problems, and it is possible to increase the number of test terminals without increasing the number of terminals.
The purpose is to enable efficient measurement of the output level of the output buffer.

[0007]

According to the present invention, in a semiconductor integrated circuit capable of inspecting the operation of an output buffer, a means for inputting a test signal, set by the start of the input of the test signal, and reset by the end of the input. A flip-flop circuit, the output buffer is fixed to the output mode by the output of the flip-flop circuit, the output level measurement pattern is input to the output buffer, and the operation of the output buffer is inspected. It has achieved its purpose.

That is, in the present invention, the output buffer is fixed to the output mode by the output of the flip-flop circuit which is set by the start of the input of the test signal and reset by the end of the input. It is not necessary to separately input a control signal or the like and there is no need to provide an independent test terminal therefor.

In particular, the output level measurement pattern is
When it is generated from the test signal and the flip-flop circuit output, the output level measurement pattern can be generated internally.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, as shown in FIG. 1, an internal logic circuit 10 and a normal output buffer 20 for outputting an output OUT1 of the logic circuit 10 to an output pad P1.
And a 3-state output buffer for outputting or not outputting the output OUT2 of the logic circuit 10 to the output pad P2 according to the state of the enable signal EN1 output from the logic circuit 10 as well. 22
And the output OUT3 of the logic circuit 10 is output to the input / output pad P3 in accordance with the state of the enable signal EN2 similarly output from the logic circuit 10, or
The present invention is applied to a semiconductor integrated circuit including an input / output buffer 24 for internally capturing a signal input from the pad P3, and a terminal 30 for inputting a test signal,
A flip-flop (FF) circuit 32, which is set when the input of the test signal input from the test signal input terminal 30 is started and reset when the input of the test signal is completed, and an output level measurement from the output Q of the test signal and the flip-flop circuit 32. OR circuits 40 and 4 for generating patterns
2, 44 and exclusive OR circuits 50, 52, 5
4 and the output Q of the flip-flop circuit 32,
The 3-state output buffer 22 and the input / output buffer 2
4 is provided in the output mode.

The operation of this embodiment will be described below with reference to FIG.

Prior to the start of the test, first, at time t0, a clear signal is input to the clear (CLR) terminal of the flip-flop circuit 32 to initialize the flip-flop circuit 32. This clear signal may be input from the outside,
It is also possible to divert a signal that becomes L level once in the logic circuit 10.

Next, at time t1, the test signal input terminal 3
When the test signal input from 0 rises, the output Q of the flip-flop circuit 32 also changes from L level to H level.
Change to a level. The output Q of the flip-flop circuit 32 maintains the H state until the time t3 when the test signal changes for one cycle and the test is completed and rises again. The test signal is fixed to the H level or the L level in the normal mode other than during the output buffer test, and in this state, the output Q of the flip-flop circuit 32 does not change and remains at the L level.

When the output Q of the flip-flop circuit 32 is at the H level, 3 is output via the OR circuits 60 and 62.
Since the enable signals input to the state output buffer 22 and the input / output buffer 24 are fixed to the H level in the output mode, both the tri-state output buffer 22 and the input / output buffer 24 are fixed to the state where the buffer output can be measured. It In the figure, the 3-state output buffer 2
2 and the input / output buffer 24 are high enable output buffers that serve as output buffers when the enable signal is at the H level.
In the case of a low enable output buffer which becomes an output buffer when it is at a level, for example, the outputs of the OR circuits 60 and 62 are inverted by an inverter or the like, and then the output buffer 22,
Enter it in 24.

In this way, the output buffer is fixed in the output mode during the test from time t1 to time t3 when the test signal changes by one cycle. In this state, first, an L level test is performed between time t1 and time t2 when the test signal is at the H level, and it is determined whether all the outputs of the output buffers are at the L level. Next, between time t2 and time t3 when the test signal changes to L level, an H level test is performed to determine whether all the outputs of the output buffers change to H level.

After time t3, the test signal and the output Q of the flip-flop circuit 32 are both fixed, so that normal operation is possible.

In this embodiment, the OR circuits 40, 4
2, 44 and exclusive OR circuits 50, 52, 5
Since the output level measurement pattern is generated by using 4, it is possible to measure the output level without inputting the output level measurement pattern from the outside. The method of generating the output level measurement pattern is not limited to this.

[0019]

As described above, according to the present invention,
The output level of the output buffer in the output level measurement pattern can be measured without adding a separate test signal input terminal for inputting the enable signal of the input / output buffer or the 3-state output buffer. Therefore, not only the time required for the test can be shortened, but also output pins that cannot be measured such as when the pattern is diverted are eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of respective parts in the embodiment.

[Explanation of symbols]

 10 ... Internal logic circuit 20 ... Output buffer 22 ... 3-state output buffer 24 ... Input / output buffer P1, P2, P3 ... Pad 30 ... Test signal input terminal 32 ... Flip-flop circuit

Claims (2)

[Claims] 1. A semiconductor integrated circuit capable of inspecting the operation of an output buffer, comprising means for inputting a test signal, and a flip-flop circuit set by the start of inputting the test signal and reset by the end of inputting the test signal. A semiconductor integrated circuit characterized in that an output level measurement pattern is input to the output buffer while the output buffer is fixed in the output mode by the output of the flip-flop circuit to inspect the operation of the output buffer. 2. The semiconductor integrated circuit according to claim 1, wherein the output level measuring pattern is generated from the test signal and a flip-flop circuit output.