JPH09214568A - Driver and communication lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the noise of a driver. SOLUTION: Timing control logic CONT1 and CONT2 start the supply of current to load by p-channel type MOS transistors MA3 and MB3 faster than the supply of current to a transformer 31 by p-channel type MOS transistors MA1 and MB1. Since the capacitive component of load is charged, sudden current at the time of driving load is relieved and therefore the occurrence of noise is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver for outputting a signal, and more particularly to a technique for reducing a through current in the driver, and more particularly to a technique effectively applied to a communication LSI (semiconductor integrated circuit) for wired communication.

[0002]

2. Description of the Related Art In response to an increase in demand for non-telephone communication services such as data and facsimile (fax), plans for digitalization of communication networks, so-called ISDN (Integrated Services Digital Network), are being pursued. These digitally link the subscriber terminals, and the digitalization of the subscriber system is essential.

[0003] The existing metallic pair cable is 0.3
It is primarily intended for voice band transmission of .about.3.4 KHz, and there are various difficulties when trying to pass high speed digital signals, such as 320 Kb / S, over such cables. For example, waveform distortion of a digital pulse due to a route f characteristic of a line, a level difference of 50 db caused by commercialization of a subscriber line length, and a bridge tap (B
Error-free digital communication must be performed under severe conditions such as a complicated echo generated by a branch line with an open end called T). In order to correct such deterioration and reproduce the original signal, it is necessary to install high-performance line equalizers at both ends of the subscriber line.

[0004] Examples of documents describing ISDN include "A paper by the Institute of Electronics and Communication Engineers of NTT ('89 / 10 Vo
l.J72-BI No. 10) "and JP-A-62-287793.

[0005]

An equalizer LSI for ping-pong transmission, which is one of the communication LSIs, is an LT (Lin.
Termination) and CT (Circuit)
Termination) unit, a driver for signal input / output, a receiver, and the like. The driver includes a MOS transistor for driving the transformer.
In order to increase the driving capability of the transformer, it is necessary to increase the ratio of the gate width and the gate length of the transistor (abbreviated as W / L).

However, if the W / L of the transformer driving MOS transistor is increased, the through current increases and a steep current flows, so that the noise becomes large, and the noise hinders the transmission of the digital signal. It has been found by the inventor that there is a fear.

An object of the present invention is to reduce driver noise.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, since it is considered that the noise generation in the driver is caused by the rapid current supply to the load (31) and the through current in the driver, the first transistors (MA1, MB1) for driving the load are generated. ), The ratio of the gate width to the gate length is smaller than that of the second transistor (MA3, M3
B3) and timing control logic (CONT1, CONT2) for starting the current supply to the load by the second transistor at a timing earlier than the current supply to the load by the first transistor. (47) is formed.

Further, the first conductivity type transistor (MA
1, MB1) and a second conductivity type transistor (MA2, MB2) connected in series to the load, when a drive stage for driving the load is formed, the drive stage is coupled to the load to form the drive stage. The second transistor (MA3, MB3) having a smaller gate width to gate length ratio than the transistor
3), the current supply to the load by the second transistor is started at a timing earlier than the current supply to the load by the drive stage, and the first conductivity type transistor and the second conductivity type transistor And timing control logic (CONT1, CONT2) that forms a period (DT2) in which both the first conductivity type transistor and the second conductivity type transistor are turned off immediately before the timing of turning on either of them. It is provided.

Further, when a communication LSI is formed including an output section for driving the transformer by supplying a current to the transformer in response to an input signal, the driver can be applied to the output section. .

According to the above means, the timing control logic causes the current supply to the load by the second transistor to start at a timing earlier than the current supply to the load by the first transistor. This alleviates a sudden current when driving the load to achieve noise reduction.

Further, immediately before the timing at which either the first conductivity type transistor or the second conductivity type transistor is turned on, both the first conductivity type transistor and the second conductivity type transistor are turned on. By forming a period for turning off the transistor, the simultaneous ON period of the transistor of the first conductivity type and the transistor of the second conductivity type is eliminated to suppress the through current, thereby achieving a further effect of noise reduction. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows a ping-pong transmission equalizer LSI which is an embodiment of the present invention. This ping-pong transmission equalizer LSI is called a digital pulse waveform distortion due to the line f characteristic of the ISDN, a level difference of 50 db caused by the commercialization of the subscriber line length, and a bridge tap (BT). It is one of the communication LSIs for correcting the signal deterioration caused by the complicated echo generated by the branch path for releasing the tip and reproducing the original signal. , Formed on one semiconductor substrate such as a single crystal silicon substrate.

The ping-pong transmission equalizer LS shown in FIG.
Although I40 is not particularly limited, LT (Line · Te)
rmination) unit 41, CT (Circuit
Termination) unit 46, driver 47, loop switch 48, and receiver 49.

AMI (Alterna) from the subscriber line side
ted / Mark / Inversion) signal is LT
The signal is input to the unit 41 and output to the terminal via the CT unit 46 and the driver 47. In addition, A input from the terminal side
The MI signal is received by the receiver 49,
6 and output to the subscriber line side via an external line driver. The loop switch 48 is provided for the loopback test.

The LT unit 41 is not particularly limited, but may be AG
C (automatic gain adjustment) circuit, pre-filter 42, ADC
(Analog-to-digital converter) 43, decimator, roll-off filter 44, route f filter, BT
A (bridge tap) circuit, a DSP 45, a PLL (phase locked loop) 50, and a reference voltage generation circuit 51 are included.

The AGC circuit is provided to keep the signal level of the input AMI signal constant. The pre-filter 42 is provided to remove out-of-band noise and prevent aliasing at the ADC 43. AGC circuit, pre-filter 42
An ADC 43 for converting the output signal into a digital signal is arranged in the subsequent stage. The ADC 43 is of an oversampling type, and a decimator for converting a digital signal obtained by oversampling into standard sampling data and a roll-off filter 44 for removing out-of-band noise are arranged in the subsequent stage.
In addition, a route f filter is provided to amplify the in-band signal attenuated by the subscriber line, and a BT (bridge tap) is provided.
, Which is a dedicated processor for processing other signals, is provided with a BT circuit for restoring a signal attenuated by an open-ended branch subscriber line referred to as
A (digital signal processor) 45 is provided. Such root f filter, BT circuit, DSP4
The operation clock 5 is supplied from the PLL 50.

FIG. 2 shows a detailed structure of the driver 47.

The load of the driver 47 is the transformer 31. When the transformer 31 is driven, noise may occur due to a rapid current flowing into the transformer 31 or a through current in the internal circuit of the driver 47. In this embodiment, however, the rapid current flowing into the transformer is The noise is reduced by mitigating or suppressing the through current.

First, the circuit coupled to one terminal on the primary side of the transformer 31 will be described.

An inverter INV1 for delaying a signal input via the input terminal VIN1 and an inverter INV2 are arranged at the subsequent stage thereof. This inverter I
A NAND circuit NAND1 for obtaining a NAND logic of the output signal of NV2 and the input signal from the input terminal VIN1 is arranged, and the output signal of the NAND circuit NAND1 causes the p-channel MOS transistor MA1 in the subsequent stage to operate. It is designed to be driven. Further, the output signal of the inverter INV2 and the input terminal VIN
A NOR circuit NOR1 for obtaining a NOR logic with the input signal from 1 is arranged, and the output signal of the NOR circuit NOR1 drives the n-channel type MOS transistor MA2 in the subsequent stage. here,
Inverters INV1, INV2, NAND circuit NAND
1. A p-channel type MOS including the NOR circuit NOR1
Transistors MA1, MA3, and n-channel MO
Timing control logic CONT1 for controlling the operation timing of S transistor MA2 is formed. This timing control logic CONT1, as will be described later,
The above timing control exerts a function of reducing noise.

The p-channel MOS transistor M
A1 and the n-channel MOS transistor MA2 are connected in series, and they function as an inverter. The source electrode of the p-channel type MOS transistor MA1 and the source electrode of the n-channel type MOS transistor MA2 are respectively coupled to the high potential side power source V1 and the low potential side power source V2. Drain electrode of p-channel MOS transistor MA1 and n-channel MO
The drain electrode of the S-transistor MA2 has an output terminal 17
Via the transformer 31 which is the load of the driver 47
Coupled to the primary side terminal of. In addition, the inverter IN
P-channel MO driven by the output signal of V1
An S transistor MA3 is provided. The source electrode and the drain electrode of the p-channel MOS transistor MA3 are the high-potential-side power source V1 and the transformer 3, respectively.
1 primary side terminal. On the secondary side of the transformer 31, a closed loop is formed in the communication path typified by the load resistor 32.

Next, a circuit coupled to the other terminal on the primary side of the transformer 31 will be described.

An inverter INV3 for delaying the signal from the input terminal VIN2 and an inverter INV4 are arranged in the subsequent stage. A NAND circuit NAND2 for obtaining a NAND logic between the output signal of the inverter INV4 and the input signal from the input terminal VIN2.
Are arranged, and the output signal of the NAND circuit NAND2 causes the p-channel type MOS transistor MB1 in the subsequent stage.
Is driven. Further, a NOR circuit NO for obtaining a NOR logic of the output signal of the inverter INV4 and the input signal from the input terminal VIN2.
R2 is arranged, and the output signal of the NOR circuit NOR2 causes the n-channel MOS transistor MB2 of the subsequent stage to be arranged.
Is driven. Here, the timing control logic CONT2 for controlling the operation timing of the p-channel type MOS transistors MB1 and MB3 and the n-channel type MOS transistor MB2 is formed by including the inverters INV3 and INV4, the NAND circuit NAND2 and the NOR circuit NOR2. To be done. The timing control logic CONT2 exhibits a noise reducing function similarly to the timing control logic CONT1.

The p-channel type MOS transistor M
B1 and the n-channel MOS transistor MB2 are connected in series, and they function as an inverter. The source electrode of the p-channel type MOS transistor MB1 and the source electrode of the n-channel type MOS transistor MB2 are respectively coupled to the high potential side power source V1 and the low potential side power source V2. Drain electrode of p-channel MOS transistor MB1 and n-channel MO
The drain electrode of the S transistor MB2 is coupled to the secondary side terminal of the transformer 31 via the output terminal 27. Further, a p-channel type MOS transistor MB3 driven by the output signal of the inverter INV3 is provided. The source electrode and the drain electrode of the p-channel type MOS transistor MB3 are coupled to the high potential side power source V1 and the secondary side terminal of the transformer 31, respectively.

To drive the transformer 31, a p-channel type MOS transistor MA1 and an n-channel type M are used.
The OS transistor MA2, the p-channel type MOS transistor MB1, and the n-channel type MOS transistor MB2 have large W / L (gate width / gate length) so that a relatively large current can be supplied to the transformer 31. It has become. On the other hand, p-channel type MOS transistor MA3 and n-channel type M
The W / L of the OS transistor MB3 is the p-channel MOS transistor MA1 and the n-channel MO.
It is set smaller than the S transistor MA2, the p-channel MOS transistor MB1, and the n-channel MOS transistor MB2.

FIG. 2 shows signal waveforms of the input and output of the driver 47 in the above configuration.

In this driver 47, the input terminal VIN
NRZ (Non / Return
A AMI (Alternate) represented by a ternary code by inputting a signal in a to-Zero code format
An output signal in the d.Mark.Inversion) code format can be obtained. In the AMI code, a logical value "1" is indicated by a zero level and a logical value "0" is indicated by a positive or negative level. Further, the logical value "0" is realized by alternately changing the positive or negative pulse so that no DC component is generated.

FIG. 3 shows the operation timing of the driver 47.

When the signal level of the input terminal VIN1 changes from the low level to the high level, the p-channel type MOS transistor MA1 changes from the off state to the on state.
However, at this time, the inverters INV1 and IV1
Due to the signal delay at NV2, the turning on of the p-channel MOS transistor MA1 causes a delay of two inverter stages, as indicated by DT2. Also, the input terminal VIN
When the signal level of 1 changes from the high level to the low level, the n-channel type MOS transistor MA2 is turned on. At this time, however, the signal delay of the inverters INV1 and INV2 causes the n-channel type MOS transistor M2.
The turn-on of A2 turns on the inverter 2 as indicated by DT2.
There is a step delay. Due to the delay of such on-timing, the p-channel type MOS transistors MA1 and n
Since it is avoided that the channel type MOS transistor MA2 is turned on at the same time, the p-channel type MO transistor
Through-current flowing from the high potential side power source V1 to the low potential side power source V2 can be suppressed via the S transistor MA1 and the n-channel type MOS transistor MA2. Since a through current, particularly a through current of a transistor which is a transformer driving stage, becomes relatively large, noise is likely to occur. Therefore, suppressing the shoot-through current by delaying the on-timing is very effective in reducing noise.

The same thing as above applies to the p-channel MO
The same applies to the S transistor MB1 and the n-channel MOS transistor MB2. That is, the input terminal VI
When the signal level of N2 changes from low level to high level, the p-channel MOS transistor MB1 shifts from the off state to the on state. At this time, the inverter I
Due to the signal delay at NV3 and INV4, the turning on of the p-channel MOS transistor MB1 causes a delay of two inverter stages. Further, when the signal level of the input terminal VIN2 changes from the high level to the low level, the n-channel type MOS transistor MB2 is turned on. At this time, however, the signal delay in the inverters INV3 and INV4 causes the n-channel type MOS transistor MB2. Turning on causes a delay of two inverter stages. Due to the delay of such on-timing, the p-channel type MOS transistor MB1 and the n-channel type MOS transistor MB
Since it is avoided that 2 and 2 are turned on at the same time, p
Through-current flowing from the high potential side power source V1 to the low potential side power source V2 can be suppressed via the channel type MOS transistor MB1 and the n channel type MOS transistor MB2.

The p-channel MOS transistor MA controlled by the output signal of the inverter INV1
As shown by DT1 in FIG. 3, the ON / OFF operation of 3 causes a delay of one inverter stage with respect to the change in the signal level of the input terminal VIN1. That is, the on-timing of the p-channel type MOS transistor MA1 is delayed from the on-timing of the p-channel type MOS transistor MA3 by a time corresponding to a signal delay of one stage of the inverter. Therefore, the p-channel MOS transistor MA1 is turned on earlier than the p-channel MOS transistor MA1 is turned on.
The transistor MA3 is turned on, and a current flows into the transformer 31. The p-channel MOS transistor MA3 is the p-channel MOS transistor MA1.
Since the W / L is set to be smaller than that, the current supplied to the transformer 31 via the p-channel MOS transistor MA3 is higher than the current supplied to the transformer 31 when the p-channel MOS transistor MA1 is turned on. Few. In other words, after the signal level of the input terminal VIN1 becomes high level, first the p-channel MO
The S transistor MA3 is turned on, and a relatively small current is supplied to the transformer 31 to charge the capacitive component of the load, and thereafter the p-channel MOS transistor M
A1 is turned on, and current is supplied to the transformer 31. In this way, the p-channel MOS transistor M
Since the p-channel type MOS transistor MA3 is turned on before A1 is turned on, a relatively small current is supplied. In other words, the current is supplied to the transformer 31 stepwise. As compared with the case where the p-channel type MOS transistor MA3 does not exist, it is possible to prevent a sudden current from flowing through the transformer 13. And p
After the channel-type MOS transistor MA1 is turned off, only a time corresponding to a signal delay of one stage of the inverter,
Since the off-timing of the p-channel MOS transistor MA3 is delayed, abrupt current change in the transformer 31 is avoided for the same reason as above. Transformer 3
Since a rapid change in the current flowing through the switch 1 causes noise, it is necessary to suppress the rapid current change by changing the current flowing through the transformer 31 stepwise as described above.
It is effective in reducing noise.

Similarly, when the signal level of the input terminal VIN2 changes from low level to high level, the p-channel type M
The OS transistor MB1 shifts from the off state to the on state, but at this time, due to the signal delay in the inverters INV3 and INV4, the p-channel type MOS transistor M
Turning on B1 causes a delay of two inverter stages. Further, when the signal level of the input terminal VIN2 changes from the high level to the low level, the n-channel MOS transistor MB2 is turned on. At this time, the inverter IN
Due to signal delay at V3 and INV4, n channel type M
Turning on the OS transistor MB2 causes a delay of two inverter stages. Such a delay in the on timing prevents the p-channel type MOS transistor MB1 and the n-channel type MOS transistor MB2 from being turned on at the same time, so that the p-channel type MOS transistor MB1 and the n-channel type MOS transistor MB2 are Through, it is possible to suppress the through current flowing from the high potential side power source V1 to the low potential side power source V2.

Further, a p-channel type MOS transistor M controlled by the output signal of the inverter INV3
The on / off operation of B3 causes a delay of one inverter stage with respect to the change in the signal level of the input terminal VIN2. That is, the on-timing of the p-channel MOS transistor MB1 is determined by the p-channel MOS transistor MB3.
The ON timing is delayed by a time corresponding to the signal delay of one stage of the inverter. Therefore, the p-channel MOS transistor MB3 is turned on earlier than the p-channel MOS transistor MB1 is turned on, and a current is supplied to the transformer 31. Since W / L of the p-channel MOS transistor MB3 is set smaller than that of the p-channel MOS transistor MB1, the current supplied to the transformer 31 via the p-channel MOS transistor MB3 is p-channel M.
It is smaller than the current supplied to the transformer 31 when the OS transistor MB1 is turned on. In other words, the input terminal V
After the signal level of IN2 goes high, first p
The channel type MOS transistor MB3 is turned on,
A relatively small current is supplied to the transformer 31, and then the p-channel MOS transistor MB1 is turned on to supply the current to the transformer 31. Current is supplied by turning on the p-channel type MOS transistor MB3 before turning on the p-channel type MOS transistor MB1. Rapid current flow is avoided. And p
After the channel-type MOS transistor MB1 is turned off, only a time corresponding to a signal delay of one inverter stage,
Since the off-timing of the p-channel MOS transistor MB3 is delayed, abrupt current change in the transformer 31 is avoided for the same reason as above.

According to the above embodiment, the following operational effects can be obtained.

(1) Timing control logic CONT1, C
P-channel MOS transistor M by ONT2
Since the current supply to the load by the p-channel type MOS transistors MA3 and MB3 is started earlier than the current supply to the transformer 31 by A1 and MB1 to charge the capacitive component of the load, the load is rapidly driven. Current is relieved. In this way, the generation of noise can be suppressed by reducing the sudden current when driving the load.

(2) Immediately before the timing when either the p-channel MOS transistor MA1 (or MB1) or the n-channel MOS transistor MA2 (or MB2) is turned on, the p-channel MOS transistor MA1 (or MB1) is turned on. And a n-channel type MOS transistor MA2 (or MB2) are both turned off (indicated by DT2), thereby simultaneously turning on the first conductivity type transistor and the second conductivity type transistor. Are eliminated, the noise can be further reduced.

(3) In the driver for driving the transformer, a transistor having a large W / L is required, which easily causes noise. Therefore, the effects of the above (1) and (2) are particularly remarkable. It

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the timing control logic CONT1,
The logical configuration of CONT2 can be variously modified at the logical design level. That is, the number of inverters connected in series for signal delay, an AND circuit, and an OR circuit.
Other logic circuits such as circuits can be employed. Also,
The drive target may be other than the transformer.

In the above description, the case where the invention made by the present inventor is mainly applied to the ping-pong transmission equalizer LSI which is the field of application which is the background has been described, but the present invention is not limited thereto. Instead, it can be applied to various LSIs that can output signals.

The present invention can be applied on the condition that at least a transistor for driving a load is included.

[0045]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the timing control logic causes the current supply to the load by the second transistor to start earlier than the current supply to the load by the first transistor, so that the abrupt current at the time of driving the load is alleviated. Can reduce noise.

Further, immediately before the timing at which either the first conductivity type transistor or the second conductivity type transistor is turned on, a period in which both the first conductivity type transistor and the second conductivity type transistor are turned off. Since the simultaneous ON period of the first-conductivity-type transistor and the second-conductivity-type transistor is eliminated by forming, the noise can be further reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration example of a driver included in a ping-pong transmission equalizer LSI according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of input / output signals of the driver.

FIG. 3 is an operation timing chart of the driver.

FIG. 4 is a block diagram of an overall configuration example of the ping-pong transmission equalizer LSI.

[Explanation of symbols]

31 transformer 32 load resistance 40 ping-pong transmission equalizer LSI 41 LT section 42 AGC, pre-filter 43 ADC 44 decimator, roll-off filter 45 route f filter, BT circuit, DSP 46 CT section 47 driver 48 loop switch 49 receiver 50 PLL INV1, INV2, INV3, INV4 Inverter NAND1, NAND2 NAND circuit NOR1, NOR2 NOR circuit MA1, MB1, MA3, MB3 p-channel type MO
S-transistor MA2, MB2 n-channel MOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technology display location H03M 5/16 (72) Inventor Takao Okazaki 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center Within

Claims (3)

[Claims] 1. A driver including a first transistor for driving a load, comprising: a second transistor coupled to the load and having a gate width to gate length ratio smaller than that of the first transistor; A timing control logic for starting the current supply to the load by the second transistor at a timing earlier than the current supply to the load by the driver. 2. A driver having a drive stage configured to drive a load, the transistor including a first conductivity type transistor and a second conductivity type transistor connected in series thereto, the driver being coupled to the load, A second transistor having a smaller gate width-to-gate length ratio than the transistor forming the stage, and a timing earlier than the current supply to the load by the drive stage, and the current supply to the load by the second transistor is started. At the same time, immediately before the timing at which either the first conductivity type transistor or the second conductivity type transistor is turned on, both the first conductivity type transistor and the second conductivity type transistor are turned off. A driver comprising: timing control logic for forming a period. 3. A communication LSI including an output section for driving the transformer by supplying a current to the transformer in response to an input signal, and capable of outputting a digital signal to a wired communication path via the transformer. A communication LSI, comprising the driver according to claim 1 or 2 as the output unit.