JPH0918299A - Pulse width correction circuit - Google Patents

Abstract

PURPOSE: To suppress the delay of an output signal to an input signal and to reduce the circuit scale to stably correct the pulse width. CONSTITUTION: One of outputs of one-bit counters 1 and 2 which are operated by the rise and the fall of the input signal is delayed by a delay circuit 3, and the output of this circuit 3 the other which is not delayed are operated in an EXOR 4 to generate the output signal whose pulse width is (pulse width) + (delay width) of the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width correction circuit, and more particularly to a circuit for properly correcting the pulse width of a pulse signal used in a digital logic circuit such as a computer.

[0002]

2. Description of the Related Art In a board on which a conventional digital logic circuit element is mounted, the wiring capacity, the inter-wiring capacity, etc. cannot be ignored, and there is also the wiring capacity, etc. between the mounting boards. The width is often narrowed, and there is a problem in that a pulse waveform for operating the subsequent element normally cannot be secured and, for example, a clock signal with a pulse width required for latching a register cannot be applied.

The narrowing phenomenon which causes such a problem is caused by the fact that the transmission loss of the high frequency component is large as compared with the low frequency component of the pulse waveform.
It is difficult to realize the essential solution with a simple structure.
Therefore, a technique of appropriately interposing a circuit that restores a pulse waveform that has been narrowed to a certain degree to a normal waveform is considered.

Referring to the circuit diagram of FIG. 5 as a first prior art showing such a circuit technique, this circuit takes an input signal as one input and passes this input signal through a delay circuit 10 to the other. It is a simple circuit consisting of an OR gate 11 for inputting.

Referring to FIG. 6A showing the operation of this circuit, the input signal becomes a pulse delayed by a predetermined time through the delay circuit 10, and the output of the OR gate 11 has a pulse width increased by this delay time. The obtained waveform is obtained.

However, as shown in FIG.
When an input signal with a small pulse width comes in, there is no overlap with the delayed output, so the output of the OR gate 11 has two pulse waveforms, which causes the problem that the logic element in the subsequent stage malfunctions. is there.

Referring to the circuit diagram of FIG. 7 as a second prior art, this circuit shows a CMO to which an input signal is applied.
An S inverter 21 is provided, a series circuit of a resistor 24 and a capacitor 25 is connected to this output, the output of the CMOS inverter 22 that receives the signal at this common connection point, that is, the node 26 as an output signal, and the input signal is gated. Input N
Channel enhancement type field effect transistor 2
3 is connected between node 26 and ground.

Referring to FIG. 8A showing the operation of this circuit, first, the input signal is the CMOS inverter 21 and Nch.
It is input to the gate of the enhancement type transistor 23. At the rising edge of the input signal, the output of the CMOS inverter 21 becomes low level and the Nch enhancement type transistor 23 becomes conductive, so that the node 26 tends to change to low level. At this time, the capacitor 25 requires a time td1 for discharging the electric charge stored in the capacitor 25 when the signal at the node 26 is at a high level, in the state before the rise of the input signal. Next, when the input signal falls, the transistor 23 becomes non-conductive, and the output of the inverter 21 tends to change to a high level. At this time, it takes time td2 for the capacitor 25 to be charged with electric charges through the resistor 24. Where node 2
When the signal of 6 changes to low level, not only the output of the inverter 21 becomes low level but also the transistor 23 becomes conductive, so that the discharging time td1 of the capacitor 25 becomes shorter than the charging time td2 by the inverter 21 alone. Therefore, the signal at the node 26 has a waveform in which the falling edge is fast and the rising edge is slow. This signal is shaped by the inverter 22, and the output signal thereof has a pulse width T2≈T1 + (td2-td1) wider than the pulse width T1 of the input signal.

However, as shown in FIG.
When the pulse width T1 of the input signal is smaller than the delay time td1, the electric charge at the node 26 cannot be fully discharged, so that it does not drop to the logic 0 level, and therefore the output signal of the inverter 22 reaches the logic 0 level. As a result, the output signal of the inverter 22 has a waveform of a logic 0 level to a somewhat higher level, and a problem arises in that an output signal having a pulse width of a logic 1 level cannot be obtained.

Further, according to this circuit, as shown in FIG. 8A, the rising edge of the output signal has a delay time td1 larger than that of the input signal by about two stages of the inverter. There is a problem that it ends up. This has the drawback of delaying the operation of the subsequent logic elements.

Further, as a third conventional example, JP-A-2-31
Referring to the block diagram of FIG. 9 shown in Japanese Patent No. 1013,
This circuit is provided with a latch 33 which receives the output of the frequency dividing circuit 31 to which the input signal is input as a data input and the output of the delay circuit 32 as a clock input, and the output of the latch 33 and the output of the frequency dividing circuit are exclusive. Synthesis circuit 3 that takes the logical sum (EXOR)
4 is provided and this output is used as an output signal.

Referring to the timing diagram of FIG. 10A showing the operation of this circuit, the delay circuit 32 delays the input signal by the time td. Further, the frequency dividing circuit 31 changes at the rising edge of the input signal, and its output is divided by two. The signal of the frequency dividing circuit 31 is taken into the latch 33 at the rising timing of the signal of the delay circuit 32, and the signal of the output of the latch 33 is a signal obtained by delaying the signal of the frequency dividing circuit 31 by the delay td of the delay circuit 32. Will be done. Therefore, by inputting the signal of the frequency dividing circuit 31 and the signal of the latch 33 to the combining circuit 5, the pulse width T2 = t.
The output signal of d is obtained.

However, as shown in FIG. 10B, the pulse width T2 of the output signal becomes the same as the delay time td of the delay circuit 32. Therefore, in order to increase the pulse width of the output signal, the delay time of the delay circuit 32 is increased. td must be set to the input pulse width T1 or more. When this circuit is configured on an IC chip, if the delay value is reduced due to manufacturing variations or the like, the pulse width of the output signal becomes smaller than the input pulse width T1.

Further, the delay circuit 32 is usually composed of a resistor and a capacitor as in the conventional example shown in FIG. 7, and in order to obtain a large delay, the resistance value and the capacitance of the capacitor should be large. . Considering that this circuit is configured on an IC chip, the area of the resistance element and the capacitance element becomes large,
This will increase the chip size. FIG.
Similarly to the cause of the signal (B) being crushed, when the input signal has a pulse width smaller than the time td, the delay circuit 3
2 The charging / discharging time of the internal capacitor cannot be fully performed, and
As shown in 0 (C), the signal A of the output of the delay circuit 32 cannot follow the input signal and is crushed, and the latch 33 does not operate normally and malfunctions. As a means for solving this, there is a configuration in which the delay value per delay circuit 32 is reduced and several stages are connected in series. However, the circuit scale naturally increases and I
When it is constructed on the C chip, there is a drawback that it causes an increase in area.

[0015]

In view of the problems of the first to third prior arts as described above, the present invention has the following problems. (1) Even if the pulse width of the input signal changes, an output signal with a predetermined pulse width should be obtained. (2) To be able to cope with changes in the pulse waveform due to the mounting state. (3) To obtain an output signal having a predetermined pulse width and logic level so that the logic element in the subsequent stage does not malfunction. (4) To minimize the delay time of the output signal. (5) An output signal should be obtained so that the pulse width does not become smaller than the input signal, even if the delay value becomes small due to variations in the manufacturing of semiconductor chips.

(6) Do not increase the size of the constituent chips. (7) Minimize the scale of the circuit to be constructed. (8) To be able to cope even when an input signal with a particularly small pulse width is applied.

[0017]

According to a first structure of a pulse width correction circuit of the present invention, a count output changes at a rising edge of an input signal and a count output changes at a falling edge of the input signal. A second counter, a delay circuit having the output of the second or first counter as an input, and an exclusive OR having the output of the first or second counter and the output of the delay circuit as an input And an arithmetic circuit.

A second configuration of the pulse width correction circuit of the present invention is characterized in that the delay circuit is connected to a stage preceding the second or first counter.

In the first and second configurations, in particular, the delay circuit is composed of a plurality of stages of inverters, and particularly the arithmetic circuit is an OR gate output or NO.
It is characterized by having an R gate output.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, which is a circuit diagram of a first embodiment of the present invention, in this embodiment, a 1-bit counter 1 (hereinafter referred to as a counter 1) whose count output changes at a rising edge of an input signal will be described. (Abbreviated as rising counter 1) and the count output changes at the falling edge of the input signal 1
A bit counter 2 (hereinafter abbreviated as falling counter 2), a delay circuit 3 that receives the output of the falling counter 2, and an output of the rising counter 1, that is, a signal A
And an output of the delay circuit 3, that is, the signal C, as an two-input signal, an exclusive OR operation circuit 4 (hereinafter, abbreviated as EXOR4).

Referring to the timing chart of FIG. 3 showing the operation of this embodiment, an input signal having a pulse width T1 is inputted to the rising counter 1 and the falling counter 2 so that the rising and falling edges of the input signal are different from each other. The output of counters 1 and 2 is changed to the rising counter 1
A signal B having a delay time of the input waveform pulse width T1 is generated with respect to the signal A that is the output of.

When the signal B is further input to the delay circuit 3, the output thereof is a signal C having [pulse width T1 + delay td of the delay circuit 3] of the input signal with respect to the signal A. Therefore, by taking the EXOR logic of the signal A and the signal C, the output signal always has a waveform having a pulse width T2 larger than the input signal by the time Td.

In the circuit of this embodiment, the delay from the rising edge of the input signal to the rising edge of the output signal is the setup time of the counters 1 and 2 and EX.
It is only the delay with OR4, which is much smaller than the delay value due to the resistor and the capacitor of the second conventional example described above. Further, since the input signal always passes through the counter 2 and then is input to the delay circuit 3, even if the input pulse width T1 is smaller than the delay value td of the delay circuit 3, the output signal of the EXOR 4 outputs the delay signal of the delay circuit 3. Since the delay value is much larger than the delay value td, there is no fear of the signal being crushed as in the conventional example.

Further, the pulse width T2 of the output signal is equal to the E of the output of the rising counter 1 and the falling counter 2.
Since the XOR is taken, the pulse signal T1 of the input signal is always ensured regardless of the delay value of the delay circuit 3, so the delay circuit 3
The pulse width T2 does not become smaller than the input signal due to the variation in the delay value. For example, if it is attempted to make the output signal 1.5 times the pulse width of the input signal, in the above-mentioned third conventional example, the delay value of the delay circuit 32 is [T1 + 0.5.T].
1], the delay value of the delay circuit 3 is [0.5 · T1] in this embodiment. Therefore, for example, when the delay circuit is composed of a resistance element and a capacitance element, the area is reduced. It takes about 1/3.

FIG. 2 showing a circuit diagram of the second embodiment of the present invention.
In this embodiment, the delay circuit 3 is connected to the output of the rising counter 1, and the EXOR
4 is the same as FIG. 1 except that EXNOR 5 is provided instead of 4.

Referring to the timing diagram of FIG. 4 showing the operation of this embodiment, in this embodiment, unlike the above-described first embodiment, the pulse width T1 of the low level section of the input signal is set.
The case where is small will be described. First, the input signal is input to the rising counter 1 and the falling counter 2,
At each of the rising edge and the falling edge of the input signal, the outputs of the counters 1 and 2 change, and the signal A, which is the output of the falling counter 2, is formed into the signal A having the delay of the input waveform pulse width T1. Contrary to the first embodiment, when the signal A output from the rising counter 1 is input to the delay circuit 3, the output has the input signal [pulse width T1 + delay td of the delay circuit 3] with respect to the signal B. Signal C is generated. By taking the EXNOR of signal B and signal C,
The output signal always has a waveform having a pulse width T2 larger than the input signal by the time td. Also in this embodiment, similarly to the first embodiment, the delay from the falling edge of the input signal to the falling edge of the output signal is only the setup time of the counters 1 and 2 and the delay of EXNOR5, The delay value is smaller than that in the second conventional example, and since the input signal always passes through the counters 1 and 2 before being input to the delay circuit 3, even if the input pulse width T1 is smaller than the delay value td of the delay circuit 3. The output signal of the delay circuit 3
There is no problem because it becomes larger than the delay value td. Since the pulse width T2 of the output signal is EXNOR of the signal from the rising counter 1 and the output of the falling counter 2, the pulse width T1 of the input signal is always ensured regardless of the delay value of the delay circuit 3. The pulse width T2 does not become smaller than the pulse width T1 of the input signal due to the variation of the delay value td of the delay circuit 3, and the area of the resistance element and the capacitance element of the delay circuit 3 on the semiconductor substrate is larger than that of the conventional example. It can be small.

In the first and second embodiments described above, the counters 1 and 2 may not operate when the rising and falling characteristics of the input signal are not steep, but if this is a concern, It is advisable to interpose a differential amplifier, an operational amplifier, etc. for shaping the waveform in the previous stage.

Although the delay circuit 3 has been described in the case of the stage after the counter 1 or 2, it may be connected to the stage before the counter 1 or 2 in addition to this.

Further, since the counters 1 and 2 each use a 1-bit binary counter, a one-pulse output signal corresponding to one pulse of the input signal can be obtained. This is called a 2-bit binary counter. Then, a one-pulse output signal is obtained for the two-pulse input signal, which is used for a specific application requiring a double period.

The EXOR 4 of the first embodiment may use an EXNOR gate as a logic element, but the output signal in this case is an output signal obtained by inverting the waveform shown in FIG. Similarly, an EXOR gate may be used as the EXNOR gate of the second embodiment, but the output signal in this case is an output signal obtained by inverting the waveform shown in FIG.

The delay circuit 3 of the first and second embodiments may be a circuit utilizing the charging / discharging action of a resistor and a capacitor as shown in FIG. 7, but in addition to this, an inverter of another stage configuration is used. Preferably. In this case, the number of inverter stages is appropriately added until the required delay time is reached.

The falling counter 2 is D
Type flip-flops can be used.

It is preferable that the pulse width correction circuit described above is appropriately interposed in the digital logic circuit where the waveform deterioration of the input signal exists or is assumed.

This pulse width correction circuit is preferably incorporated in advance in a semiconductor substrate on which a digital logic circuit is formed. However, when a new waveform deterioration becomes a problem after mounting, this pulse width correction circuit is used. The problem can be solved by interposing a semiconductor element that constitutes only the width correction circuit in that portion.

Further, such a pulse width correction circuit is composed of a logic element composed of a bipolar transistor, but in addition to this, a logic element composed of a complementary electron effect transistor can also be used.

[0036]

As described above, in the present invention, the delay from the first edge of the pulse of the input signal (the rising edge in the first embodiment) to the same edge of the output signal is the exclusive time of the counter and the exclusive logic. Sum operation circuit (first
In the embodiment, the delay time of EXOR4) is suppressed,
By counting the input signal with the counter, it operates even when the pulse width of the input signal becomes smaller than the delay value of the delay circuit compared to the conventional example, and by using the counter that operates with the rising edge and the falling edge, Since the output signal can always secure the pulse width of the input signal or more, the effect can be obtained even if the delay value of the delay circuit does not exceed the pulse width of the input signal, and more stable pulse width correction can be performed. When it is configured on an IC chip, the effect that the delay value can be made small and the area of the delay circuit can be made small is obtained, and each of the above-mentioned problems has been achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a pulse width correction circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a circuit diagram showing a first conventional pulse width correction circuit.

6A and 6B are timing charts showing the operation of the first conventional technique.

FIG. 7 is a timing diagram showing a second conventional technique.

8A and 8B are timing charts showing the operation of the second conventional technique.

FIG. 9 is a circuit diagram showing a third conventional technique.

10 (A), (B) and (C) are timing charts showing the operation of the third prior art.

[Explanation of symbols]

 1 Rising Counter 2 Falling Counter 3, 10, 32 Delay Circuit 4 EXOR 5 EXNOR 11 OR Gate 21, 22 Inverter 24 Resistor 25 Capacitor 26 Node 31 Divider Circuit 33 Latch 34 Combined Circuit A, B, C Signal

Claims (4)

[Claims] 1. A first counter whose count output changes at the rising edge of an input signal, a second counter whose count output changes at the falling edge of said input signal, and said second counter.
Alternatively, a delay circuit having an output of the first counter as an input, and an exclusive OR operation circuit having an output of the first or second counter and an output of the delay circuit as an input are provided. Pulse width correction circuit. 2. The pulse width correction circuit according to claim 1, wherein the delay circuit is connected in front of the second or first counter. 3. The pulse width correction circuit according to claim 1, wherein the delay circuit comprises a plurality of stages of inverters. . 4. The arithmetic circuit outputs an OR gate or N
3. The pulse width correction circuit according to claim 1, which has an OR gate output.