JPH09186288A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which semiconductor chip components disposed at separate positions can be connected without using an insulating board. SOLUTION: When semiconductor chip components 61 to 64 are provided on a plurality of lead frames 81 to 819 electrically insulated from each other without insulating board and the frames 81 to 819 are contained in a package 7 to constitute a multi-chip module 2, a repeating chip component 3 is provided on a lead frame 510 without insulating board, wire bonding with the component 3 as a second bonding side is conducted, and the components 61 to 64 are connected to the chip 3 via the component 3 and repeating wires 41 to 45 . The second bonding is facilitated, and the chips of the separate positions can be electrically connected. When a semiconductor board is used for the chip component, the bondability of the wires 41 to 45 is further improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of semiconductor devices that do not use an insulating substrate, and more particularly to a multi-chip module having a plurality of semiconductor chip components.

[0002]

2. Description of the Related Art In recent years, the size and density of electronic devices have been increasing, and even power devices, which were conventionally used as individual parts, have chip parts in one package together with drive circuits and protection circuits. Shape-embedded multi-chip modules have become popular.

When it is desired to store a power device chip in a multi-chip module, in the prior art, a power device chip is provided on a lead frame made of metal, and an IC chip is provided on the surface of an alumina substrate arranged on the lead frame. While bonding the power chip and the IC chip together, bond the gold wire to the predetermined bonding pad of each chip by using the bonding pad on the alumina substrate to connect the chips to each other or to the chip and the built-in electronic component. A hybrid IC (semiconductor device) was used.

Such prior art hybrid IC
4 will be described specifically with reference numeral 102 in FIGS. 4A to 4C, this hybrid IC 102 has a package 107 formed by transfer molding of epoxy resin, and from a side surface 120 thereof. 6 terminals 1
08 _{1-108 6} is derived. A metal substrate 105 formed in a flat plate shape is electrically and mechanically connected to one of the terminals 108 ₃ so as to be located in the package 107.

Each terminal 1 on the surface of the metal substrate 105
08 ₁ upward position away from to 108 _6, the bottom surface of the power semiconductor chip 106 is fixed by soldering, fixing said downward position close to the terminals 108 ₁ -108 ₆ are insulating substrate 109 by epoxy resin Has been done.

The IC chip 103 is formed on the insulating substrate 109.
An electronic circuit including a bonding pad 121 is provided in the electronic circuit.
Bonding pads on the surface 6 and the bonding pads 121 are connected by a gold wire 116, and other bondings 116 and terminals 108 ₁ , 10 in the electronic circuit are connected.
8 ₂ and 108 _{3 to} 108 ₅ are connected by a gold wire 116, and when the terminals 108 _{1 to} 108 ₆ are inserted into a printed board and the hybrid IC 102 is connected to an external circuit, the power device chip 106 can be controlled. Is configured.

In such a hybrid IC 102,
Since the power device chip 106 is arranged on the metal substrate 105, the heat distribution of the package 107 becomes uniform, and the thermal coupling between the power device chip 106 and the IC chip 103 is good, so that a large current can be generated. Widely used in circuits that handle and generate a large amount of heat.

However, the IC chip 103 made of a semiconductor substrate made of silicon single crystal or the like and the insulating substrate 109 made of alumina or the like have different constituent materials and different thermal expansion coefficients. In that case, hybrid IC
Depending on the state of the thermal cycle applied to 102, the IC
Chip 103 itself, IC chip 103 and insulating substrate 10
A crack is generated in the connection part with 9 and hybrid IC1
There was a problem that 02 would cause a breakdown.

Further, as shown in FIG. 4 (c), the metal substrate 1
As for the height of the surface of the IC chip 103 from 05, the thickness of the insulating substrate 109 is added to the thickness of the chip, so that the step difference with the terminals 108 _{1 to} 108 ₆ becomes large, the wire bonding property deteriorates, and the yield increases. descend. There is also a problem that the hybrid IC 102 becomes thick.

On the other hand, in recent years, a hybrid IC in which a semiconductor chip component such as a power device chip or an IC chip is directly provided on a lead frame arranged so as not to contact each other in a package has been used. Since there is no circuit provided on the insulating substrate, the distance between the semiconductor chip components that should be connected is large, and if the wires are directly connected with gold wires, they may come into contact with the semiconductor chip surface or the lead frame surface due to sagging. However, this has been a cause of lowering the yield such as gold wire breakage during transfer molding. Also, since there is no gold wire ball on the second bonding side of the gold wire, a large bonding area is required. Since it becomes an invalid region that cannot be arranged, the area of the entire chip is increased, and the cost is increased, and a solution is desired.

[0011]

SUMMARY OF THE INVENTION The present invention was created in order to solve the disadvantages of the prior art described above, and an object thereof is to provide a semiconductor device capable of connecting semiconductor chips without using an insulating substrate. It is in.

[0012]

In order to solve the above-mentioned problems, the invention according to claim 1 is arranged such that a relay chip part and a plurality of semiconductor chip parts each having a semiconductor substrate are arranged so as not to come into contact with each other, and are packaged. A semiconductor device having a plurality of lead frames housed inside, wherein the relay chip component and the semiconductor chip component are respectively provided on the lead frame without an insulating substrate, the semiconductor chip A relay wire for electrically connecting a component and the relay chip component is provided, and the invention according to claim 2 is the semiconductor device according to claim 1, wherein the relay wires are connected to each other. , And is electrically connected by a metal thin film.

According to such a configuration of the present invention, the relay chip part and the plurality of semiconductor chip parts each having a semiconductor substrate are provided on the plurality of lead frames arranged so as not to contact each other with the insulating substrate interposed. If a relay wire is provided to electrically connect between the relay chip component and the semiconductor chip component when a lead frame is housed in a package to form a semiconductor device, the semiconductor chip components can be connected to each other. Can be electrically connected to each other. When the relay wire is bonded, the relay chip part, which is low in cost, can be placed on the second bonding side, so that the bonding pad area for the second bonding can be increased.

Further, since the semiconductor chip components are connected by the relay chip component and the relay wire, the length of one relay wire can be shortened, and the yields of the semiconductor chip components at the distant positions do not decrease. It becomes possible to connect.

In this case, since the heights of the lead frames housed in the package are generally equal to each other, the heights of the relay chip component and the semiconductor chip component should be substantially equal to each other. The heights of the first bonding surface and the second bonding surface of the relay wire can be made substantially equal. Therefore, if there is a step, it becomes easier to perform second bonding, which makes positioning difficult,
In addition, the area of the second bonding can be reduced. If the relay chip component and the semiconductor chip component are composed of semiconductor substrates made of the same material, they can be fixed to the lead frame with the same adhesive such as silver solder, so the types of materials used are reduced. The thermal cycle resistance of the semiconductor device is improved.

It is possible to directly form a metal thin film (such as an aluminum thin film) on the semiconductor substrate of the relay chip part and bond the relay wire to the surface thereof.
In that case, the relay wires to be bonded cannot be insulated from each other, so an insulating film is formed on the semiconductor substrate of the relay chip component, a metal thin film is provided on this insulating film, and then etching molding is performed to insulate each other. It is possible to use any number of relay wires by forming the bonded bonding pads and bonding the relay wires on the bonding pads.

In that case, if the bonding pads located at distant positions on the relay chip part are electrically connected by the wiring of the metal thin film formed at the time of the etching molding, the relays located at the distant positions are connected. It is possible to connect wires. In that case, the relay wire can be shortened by the length of the wiring thin film connecting the relay wires, which is preferable because the yield of wire bonding is further improved.

[0018]

Embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, reference numeral 2 is a semiconductor device according to an embodiment of the present invention, which is generally called a multi-chip module.

The multichip module 2 has a package 7 formed by transfer molding of epoxy resin. The package 7 has a thickness of about 4 mm, are to plane a rectangle shape of about 50 mm × 20 mm, the lead frame 5 ₁ therein
~ 5 ₁₉ have been paid. The lead frame 5 ₁ to 5
One end of ₁₉ is arranged on one side surface of the package 7, terminals 8 ₁ to 8 ₁₉ formed in a rod shape are electrically and mechanically connected, and each terminal 8 ₁ to 8 ₁₉ is on one side surface of the long side of the package 7. And can be formed into a ZIP (zigzag inline package) type terminal array in a later step.

The lead frames 5 _{1 to} 5 ₁₉ are formed in advance so as to be separated from each other, and can be integrally handled by a tie bar that connects the terminals 8 ₁ to 8 ₁₉ in series during transfer molding. But package 7
After the formation of the tie bar, the tie bar is cut to disconnect the terminals 8 ₁ to 8 ₁₉
Is separated, the electrical short-circuit state of each of the lead frames 5 _{1 to} 5 ₁₉ is eliminated.

Of the lead frames 5 _{1 to} 5 ₁₉ , the lead frame 5 ₁ located at the left end of the drawing and the lead frame 5 ₁₉ located at the right end of the lead frame 5 ₁ are die formed by molding a planar lead frame material into a large area. Bonding part 13 ₁ , 1
3 ₂ are provided respectively, and power MOS-FET chips 6 ₁ and 6 ₂ which are semiconductor chip components are arranged on the surfaces of the die bonding portions 13 ₁ and 13 ₂ without an insulating substrate, and the bottom surface thereof is provided. The drain region of is directly fixed by soldering. The two die bonding parts 1
3 ₁ and 13 ₂ are arranged so as to be spaced apart from each other,
The two power MOS-FET chips 6 ₁ and 6 ₂ are arranged so as to be separated from each other in the package 7, and the heat generated by the power MOS-FET chips 6 ₁ and 6 ₂ is evenly distributed in the package 7. It is configured for distribution.

A wide tip portion of the lead frames 5 ₁₀ and 5 ₁₉ is located between the _two die bonding portions 13 ₁ and 13 ₂ , and the tip portion of the lead frame 5 ₁₀ is located. And the terminal 5 ₁₀ are between the die bonding portion 1 similar to the die bonding portions 13 ₁ and 13 _2.
3 ₃ are provided. The lead frames 5 ₁₀ and 5 ₁₉
The wider the formed tip surface of the relay chip component 3 having a semiconductor substrate, and the IC chip 6 ₄ is a semiconductor chip component, respectively, are fixed directly by the silver paste not through the insulating substrate Similarly, an IC chip 6 ₃ which is a semiconductor chip component is fixed to the die bonding portion 13 ₃ with a silver paste.
With this arrangement, the IC chip 6 ₄ has
It is located between _two power MOS-FET chips 6 ₁ and 6 ₂ , and the IC chip 6 ₃ is located therebelow.

These lead frames 5 _{1 to} 5 ₁₉ are formed by silver-plating a copper alloy having electrical conductivity, and the drain regions of the power MOS-FET chips 6 ₁ and 6 ₂ are solder and lead frame. 5 ₁ and 5 ₁₉ are electrically connected to the terminals 8 ₁ and 8 ₁₉ respectively, and the substrates of the IC chips 6 ₃ and 6 ₄ are connected to the terminals 8 ₁ through 5 5 and 5 ₁₉ through the silver paste and the lead frames 5 ₁₀ and 5 _19. It is electrically connected to ₁₀ and 8 ₁₉ , respectively.

The bonding pads provided on the gates and the sources of the power MOS-FET chips 6 ₁ and 6 ₂ are connected to the lead frames 5 ₂ and 5 by the gold wire 14 respectively.
5 ₁₆ , 5 ₁₉ , 5 ₁₇ , respectively.

The gold wire 14 is a thin metal wire that connects the bonding pad and the lead frame by ball bonding.
Of the 17 bonding pads provided on the surface of the IC chip 6 ₃ , 15 bonding pads are connected to the lead frames 8 ₃ to 8 ₁₇ respectively, and 5 bonding pads of the 5 bonding pads provided on the surface of the IC chip 6 ₄ are provided. Of these, two bonding pads are connected to the lead frames 8 ₂ and 8 ₁₉ , respectively, and one of the six bonding pads on the relay chip part 3 is connected to the lead frame 5 ₁₈ . .

[0026] At this time the connection gold wires 14, connect easily the first bonding is performed on the bonding pads of the narrow chip surface in area, Connection difficult second bonding is bondable area wide lead frame 5 ₂ - It is being done on May ₁₈ .

Further, the bonding pads of the IC chip 6 _3, 6 _4, the bonding pads of the relay chip components 3 are connected by the relay wires ₄₁ to ₅ is a gold wires for connecting the chips, The relay chip part 3 is shown in FIG. 2 and its structure and connection state will be described.
The relay chip part 3 has a semiconductor substrate 25 made of silicon single crystal similar to the power MOS-FET chips 6 ₁ and 6 ₂ and the IC chips 6 ₃ and 6 _4, and is mounted on the lead frame 5 ₁₀ . The silver paste used is IC chip 6
_The same ones as ₃ and 6 ₄ are used.

In this relay chip part 3, the power MOS
-Unlike the FETs 6 ₁ and 6 ₂ and the IC chips 6 ₃ and 6 ₄ , no electronic parts such as transistors and diodes are provided in the semiconductor substrate 25, and the silicon oxide film 26 is directly formed on the surface thereof. Has been done. Bonding pads 21 _{1 to} 21 ₆ formed by etching a metal thin film (aluminum thin film) are formed on the surface of the silicon oxide film 26. Each of the bonding pads 21 _{1 to} 21 ₄ is located near one side of the chip surface. The remaining bonding pads 21 ₅ and 21 ₆ are arranged near the side orthogonal to the one side.

The bonding pads 21 _{1 to} 21
₆ has a larger area than the bonding pads provided on the IC chips 6 ₃ and 6 ₄ , and the relay wires 4 ₁ to ₄ are provided on the bonding pads 21 _{1 to} 21 _6.
5 , the bonding pads on the IC chips 6 ₃ and 6 ₄ are connected to the first bonding side, and the bonding pads 21 _{1 to} 21 ₅ on the relay chip component 3 are connected to the second bonding side.

In this relay chip part 3, the thickness of the semiconductor substrate is made substantially equal to the thickness of the power MOS-FET chips 6 ₁ , 6 ₂ and the IC chips 6 ₃ , 6 ₄ , and the relay wires 4 ₁ ... Since the height at which the first bonding is performed and the height at which the second bonding is performed are substantially equal when bonding 4 ₅ to each other, each relay wire 4 ₁
To 4 ₃ of the connection is to be easy.

Among the bonding pads on the relay chip part 3, the bonding pad 21 ₃ and the bonding pad 21 ₄ are integrated, and the bonding pad 21 ₂ and the bonding pad 21 ₅ are the metal thin film (aluminum). (Thin film) is electrically connected to each other by a metal thin film wiring 22 ₂ formed by etching molding, and the relay wires 4 ₃ and 4 ₄ and the relay wires 4 ₂ and 4 ₅ connect the IC chips 6 ₃ and 6 ₄ to each other. Two bonding pads are connected to each other. Also, the bonding pad 21 ₁ and the bonding pad 21 ₆ are electrically connected to each other by the metal thin film wiring 22 ₁ .

A protective film (not shown) is formed on the surface of the metal thin film wiring, and a window is formed on the surface portion of each of the bonding pads 21 _{1 to} 21 _{6 of the} protective film so that the aluminum surface is exposed. Since the relay wires 4 ₁ to 4 ₅ can be connected to the exposed portion, the bonding pads 21 _{1 to} 21 ₆ and the metal thin film wiring can be formed without deteriorating the connectivity of the relay wires 4 ₁ to 4 _6. It is configured to protect 22 ₁ and 22 ₂ from corrosion and migration.

[0033] Thus, the IC chip 6 ₃ and the IC chip 6 _4, the bonding pads 21 ₁ to 21 ₅ of the relay chip 3 surface, the power MOS-FET chip 4 _{1-4 5}
, The metal thin film wiring 22 ₂ and the relay wires 4 ₂ to 4 ₅ are electrically connected to each other, and the semiconductor chip components are electrically connected to each other. Therefore, the terminals 8 ₁ to 8 ₁ connected to the respective lead frames 5 _{1 to} 5 ₁₉
When connected to an external circuit mounted by soldering the 8 ₁₉ on the printed circuit board, it is possible to operate the multi-chip module 2.

The case has been described above in which the relay wires are electrically connected to each other by the bonding pad and the metal thin film wiring provided on the relay chip component, and thereby the semiconductor chip components are electrically connected to each other. As shown in FIG. 3, the relay wire 4 ₇ is attached to the bonding pad 31 ₇
Relay wire 4 without cutting when bonding to the surface
₈ or gold wire 14 may be connected by stitch bonding.

Further, the power MOS-FET chip 6 ₁
The gate is connected to the IC chip 6 ₄ by the gold wire 14 via the lead frame 8 ₂ , but a relay chip part different from the relay chip part 3 is provided, and the gate and the IC chip 6 are connected by the relay wire. You may connect ₄ and.

The above semiconductor chip component is not limited to the power MOS-FET chip or the IC chip, but may be a power transistor chip or a thyristor chip. The material of the package is not limited to epoxy resin, and a wide range of materials such as silicon resin that can form a package of a multi-chip module are included. Further, the metal thin film is not limited to the aluminum thin film.

The material for fixing the semiconductor chip to the lead frame is not limited to solder or silver paste as described above. The material of the lead frame is not limited to copper alloy as long as it has electrical conductivity and can mount electronic parts.

The above is the power MOS-FET chip and I
The case where the semiconductor chips such as C chips are electrically connected to each other has been described. However, the bonding pads located at distant positions in one IC chip are connected to each other via the relay chip component and the relay wire. Is also possible,
The degree of freedom in the pattern design of the IC chip can be improved.

[0039]

According to the present invention, it is possible to electrically connect semiconductor chips located at distant positions without using an insulating substrate.
Further, it is not necessary to use parts having different thermal expansion coefficients, and the reliability with respect to the thermal cycle is improved. Second bonding is facilitated, which improves the yield.

[Brief description of the drawings]

FIG. 1 is a plan view of a multi-chip module according to an embodiment of the present invention.

FIG. 2 is an enlarged perspective view of an example of a relay chip component.

FIG. 3 Example of another relay chip component

4A is a perspective view of a conventional hybrid IC, FIG. 4B is an internal plan view thereof, and FIG. 4C is an internal cross-sectional view thereof.

[Explanation of symbols]

2 ...... multichip module 3, 33 ...... relay chip component ₄₁ to _5, 4 _7, 4 ₈ ...... relay wires 5 ₁ to 5 ₁₉ ...... lead frame ₆₁ through ₄ ...... semiconductor chip component 7 ... ... Packages 21 _{1 to} 21 ₆ , 31 ₇ ... Metal thin films 22 ₁ , 22 ₂ ...
… Metal thin film wiring 25 …… Semiconductor substrate 26 …… Insulating film

Claims (2)

[Claims] 1. A relay chip part each having a semiconductor substrate, a plurality of semiconductor chip parts, and a plurality of lead frames arranged so as not to contact each other and housed inside a package. The semiconductor chip component is a semiconductor device provided on the lead frame without an insulating substrate, and a relay wire for electrically connecting the semiconductor chip component and the relay chip component is provided. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the relay wires are electrically connected by a metal thin film.