JPH0917832A - Semiconductor device - Google Patents

Abstract

PURPOSE: To execute the burn in of a plurality of semiconductor devices at the same time in wafer condition. CONSTITUTION: Power voltage wirings 205 and 207 capable of external connection for wafer burn in and earth voltage wirings 206 and 208 are arranged in lattice shape so that they may pass the interior of each of a plurality of semiconductor devices 204 made on one sheet of a wafer. Each semiconductor device 204 has an inner power voltage pad 219 and an inner earth voltage pad 220 each given power voltage for quality inspection and earth voltage, and an inner power voltage wiring 213 connected to the inner power voltage pad 219, an inner earth voltage wiring 214 connected to the inner earth voltage pad 220, and four pieces of n-channel type MOS transistors 223 and 226. In case that the semiconductor device 204 is an article of good quality, the four pieces of transistors 223-226 electrically connect the inner wirings 213 and 214 to the wirings 205 and 206 for wafer burn in.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of simultaneously performing burn-in of a plurality of semiconductor devices in a wafer state.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication (Kokai) No. 3-34555 discloses a method of simultaneously performing burn-in of a plurality of semiconductor devices in a wafer state for efficient screening of latent defects in a manufacturing process, so-called wafer burn-in. A method has been proposed.

FIG. 5 is a diagram showing a structure of a conventional semiconductor device which is a target of wafer burn-in. In FIG. 5, reference numeral 501 is a wafer, 502 and 503 are power supply pads for wafer burn-in, 504 is a semiconductor device, and 50 is a semiconductor device.
Reference numerals 5 to 508 are wafer burn-in power supply wirings.
Two wafer burn-in power supply pads 502, 50
Among them, 502 is an external power supply voltage pad, and 503 is an external ground voltage pad. Of the power supply wirings 505 to 508 for wafer burn-in, 505 is a power supply voltage wiring, and 50
Reference numeral 6 is a ground voltage wiring. The power supply voltage wiring 505 extends from the external power supply voltage pad 502, and the ground voltage wiring 506 extends from the external ground voltage pad 503 so as to face each other and comb-shaped to each semiconductor device 504 on the scribe lane. Part of the power supply voltage wiring is diagonal wiring 507,
It is 508.

According to FIG. 5, the external power supply voltage pad 502 is shown.
When a power supply voltage and a ground voltage for burn-in are applied to the external ground voltage pad 503 and the external ground voltage pad 503, respectively, simultaneous burn-in of a plurality of semiconductor devices 504 can be performed. After the burn-in, when the wafer 501 is diced along the scribe lane so as to be divided into individual semiconductor devices 504, a plurality of semiconductor chips are obtained. At this time, by disconnecting the connection between the wafer burn-in power supply wirings 505 to 508 and the semiconductor device 504 before dicing, or by removing all of the wafer burn-in power supply wirings 505 to 508, a short-circuit failure that occurs during dicing occurs. To be prevented.

[0005]

The above-mentioned conventional semiconductor device capable of wafer burn-in has the oblique wirings 507 and 508 as a part of the power supply wiring for wafer burn-in.
Therefore, there is a problem that a special mask or reticle is required. Further, since the wafer burn-in power supply wirings 505 and 506 are provided on the scribe lane, it is necessary to secure a large scribe lane width.
There is also a problem that the number of semiconductor devices taken per wafer is reduced. Further, there is a problem that the number of short-circuit failure prevention steps during dicing increases.

An object of the present invention is to solve the problems of the conventional semiconductor device related to wafer burn-in.

[0007]

In order to achieve the above object, the present invention forms a power supply wiring for wafer burn-in in a grid shape instead of a comb shape, or passes inside a semiconductor device instead of on a scribe lane. Thus, the power supply wiring for wafer burn-in is formed.

Specifically, the invention of claim 1 is directed to a plurality of semiconductor devices formed on a wafer, and an external power supply voltage pad and an external ground to which a power supply voltage and a ground voltage for burn-in are respectively supplied. A voltage pad; a wafer burn-in power supply voltage wire formed on the wafer in a grid pattern in common with the plurality of semiconductor devices and connected to the external power supply voltage pad; A structure is provided in which common and grid-shaped ground voltage wiring for wafer burn-in is formed on the wafer and connected to the external ground voltage pad.

According to a second aspect of the present invention, a plurality of semiconductor devices formed on a wafer, an external power supply voltage pad and an external ground voltage pad to which a power supply voltage and a ground voltage for burn-in are provided, respectively, Wafer burn-in power supply voltage wirings formed on the wafer so as to be common to a plurality of semiconductor devices and passing through the insides of the plurality of semiconductor devices, and connected to the external power supply voltage pad; A structure including a ground voltage wire for wafer burn-in, which is formed on the wafer so as to pass through the insides of the plurality of semiconductor devices in common to each semiconductor device and which is connected to the external ground voltage pad. Is adopted.

According to a third aspect of the present invention, each of the plurality of semiconductor devices includes an internal power supply voltage pad and an internal ground voltage pad to which a power supply voltage and a ground voltage for the quality inspection of the semiconductor device are supplied, respectively. The internal power supply voltage wiring connected to the internal power supply voltage pad, the internal ground voltage wiring connected to the internal ground voltage pad, the wafer burn-in power supply voltage wiring and the internal when the semiconductor device is non-defective. A connection means is provided for electrically connecting the power supply voltage wiring and electrically connecting the wafer burn-in ground voltage wiring and the internal ground voltage wiring.

Further, in the invention of claim 4, the connecting means electrically connects at least two points of the internal power supply voltage wiring to the wafer burn-in power supply voltage wiring and at least two of the internal ground voltage wirings. A means for electrically connecting the portion to the power supply ground wiring for wafer burn-in is provided.

[0012]

According to the first aspect of the present invention, since the power supply wiring for wafer burn-in is formed in a lattice shape instead of a comb shape, diagonal wiring is not required unlike the conventional case, and as a result, a special mask or reticle is required. Not.

According to the second aspect of the present invention, since the power supply wiring for wafer burn-in is formed so as to pass through the inside of the semiconductor device, not on the scribe lane, the scribe lane has a conventional width in which the wafer burn-in is not performed. As a result, the reduction in the number of semiconductor devices taken per wafer is eliminated. Further, since the power supply wiring for wafer burn-in is arranged in the semiconductor device, dicing can be performed with the power supply wiring for wafer burn-in left.

According to the third aspect of the present invention, only non-defective semiconductor devices can be electrically connected to the power supply wiring for wafer burn-in, and a plurality of non-defective semiconductor devices can be burn-in simultaneously in a wafer state. During a wafer burn-in, if a defective semiconductor device with a short-circuit fault inside is electrically connected to the power supply wiring for wafer burn-in, the application of the burn-in voltage to the good semiconductor device is hindered. . However, according to the third aspect of the invention, a sufficient burn-in voltage for screening can be applied to a non-defective semiconductor device.

According to the present invention, the current flowing from the power supply voltage wiring for wafer burn-in to the power supply voltage wiring inside the semiconductor device shunts on the power supply voltage wiring for wafer burn-in, and the inside of the semiconductor device is The current flowing from the ground voltage wiring for the wafer burn-in to the ground voltage wiring for the wafer burn-in is shunted on the ground voltage wiring for the wafer burn-in. Therefore, the power supply voltage wiring and the ground voltage wiring for wafer burn-in can be made thin.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device capable of wafer burn-in according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 101 is a wafer, 102 and 103 are wafer burn-in power supply pads, 104 is a semiconductor device, and 10 is a semiconductor device.
Reference numerals 5 to 108 denote two-layer wafer burn-in power supply wirings formed in a grid pattern on the scribe lane. Of the two wafer burn-in power supply pads 102 and 103, 102 is an external power supply voltage pad and 103 is an external ground voltage pad. Wafer burn-in power supply wiring 10
Of 5 to 108, 105 and 107 are power supply voltage wirings connected to the external power supply voltage pad 102, and 106 and 108 are ground voltage wirings connected to the external ground voltage pad 103. The vertical power supply voltage wiring 105 and the horizontal power supply voltage wiring 107 are connected to each other on a scribe lane at one corner of the semiconductor device 104 to form a grid-shaped power supply voltage wiring layer. The vertical ground voltage wiring 106 and the horizontal ground voltage wiring 108 are connected to each other on the scribe lane at the other corner of the semiconductor device 104 to form a grid-shaped ground voltage wiring layer.

According to FIG. 1, the external power supply voltage pad 102
When the power supply voltage and the ground voltage for burn-in are applied to the external ground voltage pad 103 and the external ground voltage pad 103, respectively, simultaneous burn-in of a plurality of semiconductor devices 104 can be performed. Moreover, unlike the conventional configuration of FIG. 5, since the diagonal wirings 507 and 508 are not provided, no special mask or reticle is required to form the wafer burn-in power supply wirings 105 to 108. Further, the adoption of the lattice-shaped wafer burn-in power supply wirings 105 to 108 has an effect of equalizing the voltage applied to each semiconductor device 104 at the time of burn-in as compared with the comb-shaped case.

(Embodiment 2) FIG. 2 is a diagram showing a structure of a semiconductor device according to a second embodiment of the present invention. In FIG. 2, 201 is a wafer, 202 and 203 are power supply pads for wafer burn-in, 204 is a semiconductor device, 20
Reference numerals 5 to 208 denote two-layer wafer burn-in power supply wirings formed in a grid shape so as to pass through the inside of the semiconductor device 204. Of the two wafer burn-in power supply pads 202 and 203, 202 is an external power supply voltage pad and 203 is an external ground voltage pad. 20 out of the power supply wirings 205 to 208 for wafer burn-in
5, 207 are power supply voltage wirings connected to the external power supply voltage pad 202, and 206, 208 are external ground voltage pads 20.
3 is a ground voltage wiring connected to the terminal 3. The vertical power supply voltage wiring 205 and the horizontal power supply voltage wiring 207 are connected to each other at one corner inside the semiconductor device 204 to form a grid-shaped power supply voltage wiring layer. In addition, a vertical ground voltage wiring 206 and a horizontal ground voltage wiring 208
Are connected to each other at another corner inside the semiconductor device 204 to form a grid-shaped ground voltage wiring layer.

The internal structure of one semiconductor device 204 shown in FIG. 2 is shown in FIG. 3, the semiconductor device internal circuit 212 includes a substrate bias generation circuit 211 and other circuits (not shown), an internal power supply voltage wiring 213 and an internal ground voltage wiring 2 for supplying power to these circuits.
14. Internal power supply voltage wiring 213 is connected to internal power supply voltage pad 219, internal ground voltage wiring 214 is connected to internal ground voltage pad 220, and output signal wiring 231 of the substrate bias generating circuit is connected to substrate bias pad 221. In FIG. 3, 222 is an assembly pad, and the other internal wiring 215 is the assembly pad 22.
2 are connected. The internal wiring 215 is connected to the wafer burn-in power supply voltage wiring 2 via the fuse 216.
No. 05, a fuse 217 is connected to the wafer burn-in ground voltage wiring 206, and a fuse 218 is connected to the internal ground voltage pad 220. 22
Reference numeral 3 denotes an N-channel type M interposed between the internal power supply voltage pad 219 and the wafer burn-in power supply voltage wiring 205.
The gate electrode of the N-channel MOS transistor 223, which is an OS transistor, is connected to the internal wiring 215. Reference numeral 224 denotes an N-channel MOS transistor interposed between the internal ground voltage pad 220 and the wafer burn-in ground voltage wiring 206. The gate electrode of the N-channel MOS transistor 224 is connected to the internal wiring 215. .

Referring to FIGS. 2 and 3, in order to perform the individual pass / fail test of the semiconductor device 204 prior to the wafer burn-in, the internal power supply voltage pad 219 and the internal ground voltage pad 220 are provided with a power supply for the test. The voltage and the ground voltage are respectively supplied from the outside. At this time, the two N-channel type MOS transistors 223 and 224 are both non-conductive. The voltage supplied to the internal power supply voltage pad 219 and the internal ground voltage pad 220 is supplied to the other circuits of the substrate bias generation circuit 211 and the semiconductor device internal circuit 212 via the internal power supply voltage wiring 213 and the internal ground voltage wiring 214. To be done. Then, if the semiconductor device 204 to be inspected is a non-defective product, the fuses 217 and 218 are cut off, and if a defect such as a short circuit fault is found, the fuses 216 and 218 are cut off.

Next, the power supply voltage and the ground voltage for burn-in are applied to the external power supply voltage pad 202 and the external ground voltage pad 203, respectively. At this time, in the non-defective semiconductor device 204 in which the fuses 217 and 218 are cut, the two N-channel MOS transistors 2
23 to the gate electrodes 23 and 224 of the wafer burn-in power supply voltage wiring 205 and 207 to the fuse 216.
And the power supply voltage is supplied through the internal wiring 215. As a result, the two N-channel MOS transistors 22
3, 224 are all in a conductive state, and the internal power supply voltage wiring 213 is connected to the wafer burn-in power supply voltage wiring 205 via the internal power supply voltage pad 219 and one N-channel type MOS transistor 223, and the internal ground voltage wiring 2
Reference numeral 14 is electrically connected to the wafer burn-in ground voltage wiring 206 via the internal ground voltage pad 220 and the other N-channel MOS transistor 224. On the other hand, in the defective semiconductor device 204 in which the fuses 216 and 218 are cut, two N-channel MO
To the gate electrodes of the S transistors 223 and 224,
A ground voltage is supplied from the wafer burn-in ground voltage wires 206 and 208 through the fuse 217 and the internal wire 215. As a result, the two N-channel type MOS
All of the transistors 223 and 224 are turned off, and the electrical connection between the wafer burn-in power supply voltage wiring 205 and the internal power supply voltage wiring 213 and the wafer burn-in ground voltage wiring 206 and the internal ground voltage wiring 214 are performed.
The electrical connection with is disconnected.

As described above, according to this embodiment, when the power supply voltage and the ground voltage for burn-in are supplied to the external power supply voltage pad 202 and the external ground voltage pad 203 from the outside, respectively, only a plurality of non-defective semiconductor devices 204 are provided. Simultaneous burn-in can be performed. Moreover,
Unlike the conventional configuration shown in FIG. 5, since the diagonal wirings 507 and 508 are not provided, the power supply wirings 205 to 20 for wafer burn-in are used.
No special mask or reticle is required to form 8. Further, the adoption of the lattice-shaped wafer burn-in power supply wirings 205 to 208 has an effect of equalizing the voltage applied to each semiconductor device 204 at the time of burn-in, as compared with the comb-shaped case. Further, since the wafer burn-in power supply wirings 205 to 208 are formed so as to pass through the inside of the semiconductor device 204 instead of on the scribe lane, the number of the semiconductor devices 204 per wafer is not reduced, and the wafer burn-in is not performed. Even if dicing is performed with the power supply wirings 205 to 208 left, the probability of occurrence of a short circuit fault can be suppressed to a low level.

The three fuses 216 to 2 shown in FIG.
18 can be replaced with a switch or a resistor.

The configuration of FIG. 3 can be modified as shown in FIG. In FIG. 4, an N-channel type MOS transistor 225 for electrically connecting the internal power supply voltage wiring 213 to the wafer burn-in power supply voltage wiring 205 at the time of wafer burn-in, and the internal ground voltage wiring 214 at the time of wafer burn-in are also connected to the wafer. An N-channel MOS transistor 226 for electrically connecting to the burn-in ground voltage wiring 206 is added. The gate electrodes of both N-channel type MOS transistors 225 and 226 are connected to the internal wiring 215 similarly to the gate electrodes of the other two N-channel type MOS transistors 223 and 224.

According to FIG. 4, the current flowing from the wafer burn-in power supply voltage wiring 205 to the power supply voltage wiring 213 inside the semiconductor device 204 is on the wafer burn-in power supply voltage wiring 205 and two N channel type MOs.
The current shunting the S transistors 223 and 225 and flowing from the ground voltage wiring 214 inside the semiconductor device 204 to the wafer burn-in ground voltage wiring 206 is 2 times.
The N-channel MOS transistors 224 and 226 and the wafer burn-in ground voltage wiring 206 are shunted. Therefore, the size of each of the N-channel MOS transistors 223 to 226 can be reduced, and the power supply voltage wiring 205 and the ground voltage wiring 206 for wafer burn-in can be thinned, and the area of the semiconductor device 204 can be reduced. It will be possible.

The internal structure of the semiconductor device 204 shown in FIGS. 3 and 4 is the same as that of the semiconductor device 104 shown in FIG. 1 if the wafer burn-in power supply wirings 205 to 208 are taken out of the semiconductor device 204. Can be used as a configuration.

[0028]

As described above, according to the present invention, the power supply wiring for wafer burn-in is formed in a lattice shape, or the power supply wiring for wafer burn-in is formed so as to pass through the inside of the semiconductor device. Therefore, a special mask or reticle is not required, the number of semiconductor devices to be taken per wafer is increased, and the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device in a wafer state according to a first embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device in a wafer state according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing the internal configuration of one semiconductor device in FIG.

FIG. 4 is a circuit diagram showing a modified example of the configuration of FIG.

FIG. 5 is a plan view of a conventional semiconductor device in a wafer state.

[Explanation of symbols]

101, 201, 501 Wafers 102, 202, 502 External power supply voltage pads 103, 203, 503 External ground voltage pads 104, 204, 504 Semiconductor devices 105, 107, 205, 207, 505, 507, 5
08 wafer burn-in power supply voltage wiring 106, 108, 206, 208, 506 wafer
Ground voltage wiring for burn-in 211 Substrate bias generation circuit 212 Semiconductor device internal circuit 213 Internal power supply voltage wiring 214 Internal ground voltage wiring 215 Internal wiring 216 to 218 Fuse 219 Internal power supply voltage pad 220 Internal ground voltage pad 221 Substrate bias pad 222 Assembly pad 223 to 226 N-channel MOS transistor (connection means) 231 Substrate bias generation circuit output signal wiring

Claims (4)

[Claims] 1. A plurality of semiconductor devices formed on a wafer, an external power supply voltage pad and an external ground voltage pad to which a power supply voltage and a ground voltage for burn-in are respectively supplied, and the plurality of semiconductor devices. A wafer burn-in power supply voltage wire formed on the wafer in a common and grid pattern and connected to the external power supply voltage pad; and a common and grid pattern of the wafer for the plurality of semiconductor devices. A wafer burn-in ground voltage wire formed above and connected to the external ground voltage pad. 2. A plurality of semiconductor devices formed on a wafer, an external power supply voltage pad and an external ground voltage pad to which a power supply voltage and a ground voltage for burn-in are respectively supplied, and the plurality of semiconductor devices. A plurality of semiconductor burn-in power supply wirings formed on the wafer so as to pass through the insides of the plurality of semiconductor devices and connected to the external power supply voltage pad; And a ground voltage wiring for wafer burn-in, which is formed on the wafer so as to pass through the plurality of semiconductor devices in common and is connected to the external ground voltage pad. Semiconductor device. 3. The semiconductor device according to claim 1, wherein each of the plurality of semiconductor devices is provided with an internal power supply voltage pad for supplying a power supply voltage and a ground voltage for a quality test of the semiconductor device. And an internal ground voltage pad, an internal power supply voltage wire connected to the internal power supply voltage pad, an internal ground voltage wire connected to the internal ground voltage pad, and the wafer when the semiconductor device is a good product.
A connection means for electrically connecting the burn-in power supply voltage wiring and the internal power supply voltage wiring, and for electrically connecting the wafer burn-in ground voltage wiring and the internal ground voltage wiring. A semiconductor device characterized by: 4. The semiconductor device according to claim 3, wherein the connecting means is at least 2 of the internal power supply voltage wiring.
At least two of the internal ground voltage wirings are electrically connected to the wafer burn-in power supply voltage wirings.
A semiconductor device comprising means for electrically connecting a portion to the power supply ground wiring for wafer burn-in.