JPH0916541A - Information processor - Google Patents

Abstract

PURPOSE: To dispense with the synchronous control of data transfer and interrup tion with software by suppressing passing by the interruption of a data block in DMA transfer from a device to a memory device with hardware. CONSTITUTION: The interruption suppression part 215 of an input/output control part 2 consists of a HAND gate and an AND gate, and it is constituted so as to issue the output of the AND gate to a second system bus as REQ2. When a valid flag V is set in '1', the output of the HAND gate of the interruption suppression part 215 goes to logic '0' when the interruption flag of a buffer register(BUF) 2 shows logic '1' and also, a line execution line 111 shows logic '1' therefore, the output of the AND gate always goes to "0" by masking the valid flag V, and the REQ2 is held in a state of logic '0', and the input/ output control part 2 suppresses the interruption to a SYSBUS (systembus) 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a data transfer / interrupt synchronization method for an information processing apparatus. More specifically, the present invention comprises a duplicated bus,
In a conventional information processing device that transfers data from the input / output control unit to the storage unit and notifies the software of the end of the data transfer by an interrupt, the data structure is reduced due to the redundant bus structure adopted because of the need to improve performance. The present invention relates to an information processing apparatus in which the possibility of an interrupt overtaking a block is controlled by hardware.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus including an arithmetic processing unit, a storage unit, an input / output control unit, and a single bus connecting them, data transfer from the input / output control unit to the storage unit (for example, storage from the device DMA (Direct Memory Ac)
cess) transfer, and the completion of the data transfer is notified to the software (interrupt handler) by the interrupt from the input / output control unit to the arithmetic processing unit, there is no problem that the data block to be transferred is overtaken by the interrupt.

[0003] Further, it is composed of an arithmetic processing unit, a storage unit, an input / output control unit, and a redundant bus connecting them, and performs data transfer from the input / output control unit to the storage unit. In an information processing apparatus that notifies software (interrupt handler) of an arithmetic processing unit by interruption to the arithmetic processing unit, the overtaking control is performed by software.

A duplex bus is an input / output bus (such as an I / O bus) for connecting an input / output control unit and a device control unit as shown in FIG. 1 for explaining an embodiment of the present invention. And a system bus (SYSBUS or the like) to which the input / output control unit, the storage unit, the arithmetic processing unit, and the like are connected is doubled to substantially increase the bit (byte) width of the bus and increase the bus transfer bandwidth. It is intended to improve performance such as realization of high-speed transfer.

[0005] As an example of a method for realizing the overtaking control of the interrupt in the redundant bus by software, the arithmetic processing unit issues an I / O read request (DMA transfer from the device control unit to the storage unit) to the device control unit. When the data transfer end interrupt handler is activated, dummy access (such as dummy I / O read without data read transfer) is continuously performed to the device control unit, and the dummy I / O is performed. There is a method in which after the arithmetic processing unit obtains a response (response) to the read from the device control unit, the data transferred to the storage unit by the above-described I / O read request is processed.

According to this control method, a data block read from the device control unit and waiting for output to the system bus by one input / output control unit can also be used for device control of dummy I / O read. The data block has already been transferred to the storage unit when the response to the dummy I / O read from the device control unit arrives at the arithmetic processing unit because it precedes the response from the unit in time series. Thus, "garbled data" (treating old data as new data) due to passing of an interrupt is avoided.

[0007]

In the above-mentioned information processing apparatus, when software does not perform overtaking control, data in block units each having a predetermined byte length are alternately transmitted from the input / output control unit to the storage unit using a duplex bus. When the data transfer is completed, the I / O control unit interrupts the arithmetic processing unit at the end of the data transfer.However, because of the redundant bus, the last data block and the interrupt go up to separate I / O control units, respectively.
While waiting for the last data block to be issued to one bus due to bus busy in one input / output control unit, a subsequent interrupt overtakes the waiting data block and performs operation from the other bus. A situation occurs in which the software (interrupt handler) of the processing unit is notified.

[0008] When the software is notified of the interruption due to the passing of the interruption, the old data block before the data block is written to the storage unit is used, resulting in "garbled data".

On the other hand, when the software controls the overtaking, valuable performance of the arithmetic processing unit is wasted, and as a result, improvement of the system performance by the redundant bus is hindered.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an information processing apparatus which solves the above-mentioned problems, reliably avoids garbled data due to misuse of old data blocks, and achieves an improvement in performance.

[0011]

In order to achieve the above object, the present invention provides a dual processing system including an arithmetic processing unit, a storage unit, first and second input / output control units, and a device control unit. In the information processing apparatus having the above-described bus configuration, the first input / output control means decodes a transaction input from the device control means and transfers DMA data from the device control means to the storage means (“DMA data transfer”). , The write execution signal for notifying the second input / output control means that the DMA write transaction is being held is set to the active state. Circuit means, wherein the second input / output control means inputs the write execution signal output from the first input / output control means, and When the transaction input from the means is decoded and an interrupt request is detected, the interrupt request is suspended while the write execution signal is in an active state, and the write execution signal is inactivated. And a circuit means for controlling so as to issue the suspended interrupt request.

[0012] The present invention preferably provides the first and second embodiments.
Input / output control means includes input / output cache means for retaining data and maintaining data consistency with the storage means (referred to as "coherency"), and the first input / output control means When the decoded result indicates the DMA write, the write execution line is set to an active state, and when the transaction hits the input / output cache unit,
After the transaction is stored in the input / output cache unit, the write execution line is set to an inactive state.

Preferably, when the transaction misses the input / output cache means, an exclusive coherent read request for invalidating a cache is issued on the first system bus. Writing response data to the exclusive coherent read request from the first system bus to the input / output cache, writing the held transaction to the input / output cache, and setting the write execution line to an inactive state. It is characterized by the following.

The present invention comprises a first and a second system bus,
Via first and second input / output control means respectively connected to the first and second system buses, first and second input / output buses, and the first and second input / output buses. In an information processing device including a device control unit, a storage unit, and an arithmetic processing unit, which are respectively connected to the first and second input / output units, the first input / output control unit has a DMA write. When it is recognized that the DMA write is held, the information indicating that the DMA write is held is notified to the second input / output control means, and the held DMA write is output to the first system bus. DMA write execution detection means for controlling is provided, and the second input / output control means receives an interrupt from the device control means based on the notification information from the DMA write execution detection means of the first input / output control means. If you do, DM Light is running pending the interruption thus suppressing the acquisition request of the second system bus, D
Interrupt inhibiting means for issuing an acquisition request for the second system bus when the MA write is not being executed and issuing the interrupt suspended when the second system bus is acquired. An information processing device having a feature is provided.

[0015] The present invention preferably provides the first and second embodiments.
Input / output control means includes input / output cache means for holding data and maintaining data consistency with the storage means (referred to as "coherency"), and the first and second system buses have a coherency function. Then, the first input / output control means recognizes that it has a DMA write,
The second I / O control unit is notified of information that the A write is being held, and if the address of the held DMA write matches the address held by the I / O cache unit, the data is deleted. Recognizing that writing to the input / output cache means no longer holds the DMA write,
If the held DMA write address does not match the address held in the input / output cache means, the first
After the first system bus is acquired and the first system bus is acquired, if a data block having the same address is provided with a coherency function, a read for invalidating the cache (referred to as “exclusive coherent read”) ) Is output to the first system bus, and after receiving the response data of the read, the data is written to the input / output cache, and it is recognized that the pending DMA write process has been completed, and the second Means for notifying the input / output control means.

In the present invention, preferably, the first input / output control means inputs a transaction sent from the device control means via a first I / O bus, and A decoder for decoding a transaction stored in the input buffer register; a first flag indicating validity / invalidity of the transaction; a second flag indicating DMA read / write; and a third flag indicating presence / absence of an interrupt request And a register including at least a field for holding the transaction; and an output buffer register for outputting the transaction to a first system bus.
Are turned on when the transaction transmission signal from the device control means is activated, and when the transaction is valid, the first flag indicates the on state, and the second flag indicates the DMA state. The write execution signal is activated when a write is indicated.

Further, the present invention preferably comprises the second step.
An input buffer register for inputting a transaction sent from the device control means via a second I / O bus, a decoder for decoding a transaction stored in the input buffer register, A register including at least a first flag indicating validity / invalidity of the transaction, a second flag indicating DMA read / write, a third flag indicating the presence or absence of an interrupt request, and a field for holding the transaction; And an output buffer register for outputting the transaction to a second system bus, wherein the first flag is set to an on state when a transaction transmission signal from the device control means is activated and the transaction is valid. And the first flag indicates an ON state. In this case, the third flag indicates an interrupt request from the device control means, and is controlled so that the interrupt request from the device control means is not transmitted to the arithmetic processing unit when the write signal line is in an active state. It is characterized by doing.

[0018]

According to the present invention, D is transferred from a device to a storage device.
Since the overtaking due to the interruption of the data block in the MA transfer is suppressed by hardware, the synchronous control of the data transfer and the interrupt by software is not required, and the order of the data transfer and the interrupt can be reliably guaranteed. It is possible to realize an information processing device configured with a high-speed, high-data-integration duplex bus, and is suitably applied to, for example, an information processing device such as a file server that requires high-speed data transfer.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[0020]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

Referring to FIG. 1, the information processing apparatus of the dual bus system according to the present embodiment includes a first input / output control unit 101,
Second input / output control unit 201 and device control unit 30
1 is provided.

The first input / output control unit 101 (= input / output control unit 1) includes SYSBUS1 and REBUS of the first system bus.
Both are connected to a CPU (arithmetic processing unit) (not shown) and a memory via Q1 and GNT1, and a first I / O
It is connected to the device control unit 301 via IOBUS1, ADS1, and RDY1 of the O bus.

The second input / output control unit 201 (= input / output control unit 2) is provided with SYSBUS2, REBUS of the second system bus.
Q2 and GNT2 are connected to a CPU and a memory (not shown), and the second I / O bus IOBUS2,
It is connected to the device control unit 301 via S2 and RDY2.

When viewed from the device control unit 301 side, it is connected to the input / output control unit 1 via the first I / O bus IOBUS1, ADS1, RDY1 and the second I / O bus.
It is connected to the input / output control unit 2 via IOBUS2, ADS2, and RDY2 of the O bus.

In FIG. 1, "1" or "2" (for example, R
"1" and "2" in EQ1, REQ2 or BUF1, BUF2, etc. indicate "first" or "second" in a duplicated bus and an input / output control unit,
In the following, this notation is mainly used. When “first” and “second” are designated, for example, “REQ1”
/ 2 "or the like.

The system bus is duplicated, and SYSBUS
1/2, REQ1 / 2, GNT1 / 2, SYS
BUS1 / 2 transfers the address / data / command of the transaction, and REQ1 / 2 denotes a bus use request line for a bus agent (also referred to as a “bus arbiter”) connected to the system bus, GNT1 / 2.
Is a bus use permission line from the bus agent. Also, a first bus composed of SYSBUS1, REQ1, and GNT1 is used.
System bus, SYSBUS2, REQ2, GNT
The second system bus consisting of two operates independently.

The I / O bus is duplicated and IOBUS1 /
2, consisting of ADS1 / 2, RDY1 / 2, IOBUS
1/2 transfers the address / data / command of the transaction, ADS1 / 2 is the transaction transmission signal (address strobe signal) from the device control unit 301, and RDY1 / 2 is the transaction reception response of the input / output control unit 1/2. (Ready signal).

As shown in FIG. 1, the input / output controller 1 includes an input buffer register (INBUF1) 108, a buffer register (BUF1) 113, an output buffer register (OUTBUF1) 114, and a decoder (DEC1) 11.
2. Write execution detection unit 115, register (RADS1)
109, a register (RRDY1) 110.

The input / output controller 2 includes an input buffer register (INBUF2) 208 and a buffer register (BUF).
2) 213, output buffer register (OUTBUF2)
214, decoder (DEC2) 212, interrupt suppression unit 215, register (RADS2) 209, register (R
RDY2) 210, and the write execution line 111 output from the write execution detection unit 115 of the input / output control unit 1 is input to the interrupt suppression unit 215 of the input / output control unit 2.

INBUF1 / 2 is the device control unit 30
Reference numeral 1 denotes a register for holding a transaction (address, command, data) output to IOBUS1 / 2 for one clock.

RADS1 / 2 is a device control unit 301
Is a register that holds the address strobe (ADS) 1/2 output by the CPU for one clock, and outputs the logic "1" one clock after the ADS1 / 2 becomes valid.

In RRDY1 / 2, DEC1 / 2 decodes an address / command whose output of RADS1 / 2 is logic "1" and which is stored in INBUF1 / 2.
As a result of the decoding, if the received transaction is valid, this register indicates the logic “1” one clock after RADS1 / 2 becomes the logic “1”.

DEC1 / 2 decodes the address / command stored in INBUF1 / 2, determines whether the received transaction is valid or invalid, and determines the type of transaction (interrupt, DMA write, or DM).
A read). Note that "DMA
“Write (DMA write)” refers to a DMA transfer for writing data from the device control unit 301 to the storage unit via the I / O bus and the system bus.
ad) "means a DMA transfer for reading data from the storage unit to the device via the system bus and the I / O bus.

BUF1 / 2 is V (Valid: valid /
An invalid flag, also referred to as a “valid flag”), an interrupt flag (an interrupt flag is a flag indicating the presence or absence of an interrupt from the device control unit 301), a DMA read / DMA
It consists of a write flag and a transaction field (address, data) for holding a transaction.

The valid flag V is set such that DEC1 / 2 is IN
As a result of decoding the transaction stored in BUF1 / 2, if the received transaction is valid, the logic becomes "1" one clock after RADS1 / 2 becomes "1", and the transaction of BUF1 / 2 becomes After being output to SYSBUS1 / 2, it becomes logic "0".

Interrupt flag and DMA read / DMA
The write flag is updated at the same timing as when the valid flag V becomes logical "1". The logical value (combination) of the interrupt flag and the DMA read / DMA write flag is such that DEC1 / 2 becomes INBUF1 / 2. As a result of decoding the stored transaction (command), the transaction is “1, 0” if the transaction is an interrupt, “0, 0” if the transaction is a DMA read, and DM
In the case of the A write, it is "0, 1".

The transaction field of BUF1 / 2 is updated at the same timing as the timing when the valid flag V becomes logical "1", and the transaction address, command and data are stored from INBUF1 / 2.

REQ1 is a valid flag V of BUF1.
Becomes “1” when it becomes “1”,
A bus use request of SYSBUS1 is made.

REQ2 is a valid flag V of BUF2.
Is connected via an AND gate, and the other input of the AND gate (the output of a NAND gate to be described later) is a logical "1".
In this state, when the valid flag V becomes logic "1", the bus use request of the SYSBUS2 is made by making the logic "1".

In GNT1 / 2, REQ1 / 2 is logic "1" (when the input / output control unit 1/2 requests use of the bus).
When the right to use the bus is given to the input / output control unit 1/2, the logic becomes "1".

OUTBUF1 / 2 stores the address, command, and data of the transaction one clock after the transaction is stored in BUF1 / 2. When GNT1 / 2 becomes “1”, OUTBUF1 /
2 outputs a transaction to SYSBUS1 / 2.

The write execution detector 115 receives the valid flag V and the DMA read / write flag as inputs.
An ND gate is provided, and the output of the AND gate is used as a write execution line 111. When the valid flag V is logic “1”,
When the DMA read / write flag is logic "1" (in the case of DMA write), the write execution line 111 is set to logic "1", and the input / output control unit 1 indicates that the DMA write is being executed. Notify part 2.

The interrupt suppressing unit 215 of the input / output control unit 2
A NAND gate which receives the write execution line 111 and an interrupt flag of BUF2 of the input / output control unit 2 as inputs,
An AND gate that receives the output of the D gate and the valid flag V of BUF2 is input.
It is configured to output to the second system bus as Q2.

When the valid flag V is logic "1", the interrupt flag of BUF2 is logic "1", and
When the write execution line 111 is at logic "1", the output of the NAND gate of the interrupt suppressing unit 215 is at logic "0". Therefore, the valid flag V is masked and the output of the AND gate is always "0". REQ2 is kept at the state of logic "0", and the input / output control unit 2 suppresses the issuance of an interrupt to SYSBUS2.

When the interrupt flag is logic “0” or the write execution line 111 is logic “0”, the output of the NAND gate of the interrupt suppression unit 215 becomes logic “1” and the input / output control unit 2 executes Issuance of the middle transaction is not suppressed by the interrupt suppression unit 215. In other words, the valid flag V of BUF2 conducts the AND gate as it is, and when the valid flag V is logic "1", R
EQ2 becomes logic "1".

FIG. 2 is a timing chart showing the operation timing of one embodiment of the present invention. In FIG. 2, IOB
DMA write 1 (DMA transfer for writing data from the device side to the storage unit) is input to the input / output control unit 1 from the US 1 side, and after the DMA write 1 ends, IOBUS 2
Is input to the input / output control unit 2.

If the write execution line 111 becomes logic “1” before the interrupt is input to the input / output control 2, the interrupt suppression unit 215 detects the state, and the interrupt is input to the input / output control unit 2. (When an interrupt transaction is input to IOBUF2 and decoded by decoder 2 and the interrupt flag of BUF2 is set to logic "1"), the interrupt request is suppressed. That is, while the write execution line 111 is at logic “1”, the valid flag V of the BUF2 is logic “1” and the interrupt flag is logic “1”.
At this time, REQ2 holds the state of logic "0".

DMA write 1 being processed by the input / output control unit 1
Is output to the SYSBUS 1 to return the write execution line to logic “0”.

In response to this, the interrupt suppression unit 215 outputs the suppressed interrupt request to SYSBUS2,
When the bus is permitted to be used (when GNT2 becomes logic "1"), a pending interrupt is issued.

[0050]

[Embodiment 2] FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.

Referring to FIG. 3, in this embodiment, the I / O control unit 1 in the first embodiment shown in FIG.
A cache 401, a hit determination circuit 402, and an input buffer (INBUF3) 403 are added.

In the following, only the differences between this embodiment and the first embodiment will be described. The I / O cache 401 is
Data consistency and data consistency with storage means (coherenc
y, which is an input / output cache memory for maintaining “coherency” (a predetermined cache coherency protocol is implemented for maintaining coherency. For the cache coherency protocol, for example, see the document “JLHennessy, DAPatterson,
“COMPUTER ARCHTECTURE: A QUANTATIVE APPROACH”, M
ORGAN KAUFFMANN PUBLISHERS, INC. 1990, 466-47
3 pages "or literature:" JLHennessy, DAPatterso
n, “COMPUTER ORGANIZATION AND DESIGN: THE HARDWAR
E / SOFTWARE INTERFACE ”, MORGAN KAUFFMANN PUBLISHER
S, INC. 1994, p. 575 ").

The I / O cache 401 includes a plurality of lines including a V flag, a cache status, a data field, and an address field.

When the value of the V flag is logical "1", it indicates that a valid transaction is stored in the corresponding I / O cache line, and when the value is logical "0", the corresponding I / O cache line is Indicates that the line is invalid.

The cache status of the I / O cache 401 indicates that the status of the corresponding I / O cache line is one of clean exclusive, dirty exclusive, and shared. Note that "dirty" indicates a state in which the cache line is dirty, that is, a state in which consistency is not maintained.

The data field of the I / O cache 401 stores the data of the transaction, and the address field stores the address of the transaction (more specifically, the address tag composed of a predetermined upper bit field of the address signal).

When the transaction stored in BUF1 is determined as a miss in the I / O cache 401,
Issue from OUTBUF1 to SYSBUS1. OUT
The response of the transaction issued from BUF1 to SYSBUS1 is from SYSBUS1 to INBUF3.
Through the I / O cache 401.

Then, the stored transaction is D
When the write operation is the MA write, the status, data field, and address field of the corresponding I / O cache line are updated.

The hit determination circuit 402 determines whether the transaction stored in the BUF1 hits any line of the I / O cache 401 or makes a miss.

The transaction hits the I
This is a case where the V flag of the / O cache 401 is logical "1", and there is a line in the I / O cache 401 whose address field content (address tag) matches the address tag of the transaction. On the other hand, a miss occurs when the V flag of the I / O cache 401 is logical "0" or the addresses do not match.

When the transaction “DMA write” is stored in BUF1, the write execution line 111 becomes logic “1” (both the valid flag V of BUF1 and the DMA read / write flag are logic “1”). When the transaction hits a certain line in the I / O cache 401, the transaction is stored in the I / O cache 401.

After the transaction is stored, the write execution line 411 is set to logic "0".

On the other hand, if the transaction misses,
The transaction “DMA write” is changed to a read that invalidates the cache, that is, an exclusive (exclusive) coherent read, and OUTB
Issued from UF1 to SYSBUS1 (note that SYSBUS1 is
The exclusive coherent read issued to the BUS1 invalidates a cache such as a CPU connected to the SYSBUS1).

The data response of exclusive coherent read is from SYSBUS1 to INB.
The data is stored in the I / O cache 401 via the UF 3, but when this operation is completed, the write execution line 111 becomes logic “0”.

Then, the write execution line 111 becomes logic "0".
At this point, if the interrupt request is suspended, the input / output control unit 2 sends the interrupt request to the SYSBUS2.
Issue to

FIG. 4 is a timing chart showing the operation timing of the second embodiment of the present invention.

The transaction of the DMA write 2 is input to the input / output control unit 1 from the IOBUS 1.

When the DMA write 2 is stored in BUF1, the write execution line becomes logic "1".

The valid flag V of BUF1 is a logical "1"
Is reached, hit determination is performed by the hit determination circuit 402. In this case, it is determined that a mistake has occurred.

When a cache miss occurs, SYSBUS
A bus use request is made for REQ1 by setting REQ1 to logic "1".

When GNT1, which is the use permission signal for the first system bus, becomes logic "1", an exclusive coherent read is issued to SYSBUS1.

As shown in FIG. 2, for example, when a data response is received from SYSBUS1 after 9 bus cycles, the transaction is stored in the data field of the cache line of the I / O cache 401 from INBUF3.

One cycle (1T) later, the data (BUF data) stored in BUF1 is transferred to the corresponding I
The data is stored in the / O cache line (partial merge), and the write execution line 111 is set to logic “0”.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments, but includes various embodiments according to the principles of the present invention.

[0075]

As described above, according to the present invention,
Synchronization of data transfer and interrupts under software control is not required, so that CPU processing time for synchronous processing is not wasted, and the order of data transfer and interrupts can be guaranteed. This makes it possible to realize an information processing device configured with a highly-reliable duplex bus. Further, according to the present invention, by providing the I / O cache, data coherency is maintained and data transfer processing performance is further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of another embodiment of the present invention.

[Explanation of symbols]

 101 I / O control unit 1 102 System bus 1 103 Bus use request line 1 104 Bus use permission line 1 105 I / O bus 1 106 Address strobe line 1 107 Receive response line 1 108 Input buffer 1 109 Address strobe register 1 110 Reception response register 1 111 Write execution line 112 Decoder 1 113 Transaction buffer 1 114 Output buffer 1 115 Write execution detection unit 201 I / O control unit 2 202 System bus 2 203 Bus use request line 2 204 Bus use permission line 2 205 I / O bus 2 206 Address strobe line 2 207 Receive response line 2 208 Input buffer 2 209 Address strobe register 2 210 Receive response register 2 212 Decoder 2 213 Transaction buffer 2 214 Output buffer 2 215 Interrupt suppression unit 301 Device control unit 401 I / O cache 402 Hit determination circuit 403 Input BUF3

Claims (7)

[Claims] 1. An image processing apparatus comprising: an arithmetic processing unit; a storage unit; first and second input / output control units; and a device control unit;
In the information processing apparatus having a duplicated bus configuration, the first input / output control unit decodes a transaction input from the device control unit and transfers DMA data from the device control unit to the storage unit (“ DMA write ”), the write execution signal for notifying the second input / output control means that the DMA write transaction is being held is set to the active state. The second input / output control means receives the write execution signal output from the first input / output control means, decodes a transaction input from the device control means, and interrupts the transaction. Request is detected, the interrupt request is issued while the write execution signal is in the active state. Distillate City, information processing apparatus, characterized in that the write execution signal includes a circuit means for controlling to issue the pending interrupt requests when it becomes inactive. 2. The apparatus according to claim 1, wherein said first and second input / output control means include input / output cache means for retaining data and maintaining data consistency with said storage means (referred to as "coherency"). When the I / O control means sets the write execution line to an active state when the DMA write is a result of decoding the transaction, and when the transaction hits the I / O cache means, 2. The write execution line is made inactive after storing the transaction in the input / output cache unit.
The information processing device described. 3. An exclusive coherent read request for invalidating a cache is issued on a first system bus when the transaction misses the input / output cache means, and the exclusive coherent read is issued. And writing the response data to the request from the first system bus to the input / output cache, writing the held transaction to the input / output cache, and setting the write execution line to an inactive state. 2. The information processing apparatus according to item 2. 4. The system of claim 1, further comprising: a first and a second system bus;
First and second input / output control means respectively connected to a second system bus; first and second input / output buses; and the first and second input / output buses via the first and second input / output buses. In an information processing apparatus including a device control unit, a storage unit, and an arithmetic processing unit connected to the second input / output unit, it is recognized that the first input / output control unit has a DMA write. In this case, the DMA write is notified to the second input / output control means of information indicating that the DMA write is being held, and the DMA write is controlled so as to output the DMA write being held to the first system bus. An execution detection unit, wherein the second input / output control unit receives an interrupt from the device control unit based on notification information from the DMA write execution detection unit of the first input / output control unit, DMA write During execution, the acquisition request for the second system bus is suppressed to suspend the interrupt, and when the DMA write is not being executed, the acquisition request for the second system bus is issued, and the second system bus is issued. An information processing apparatus comprising: an interrupt suppressing unit that issues the interrupt that has been suspended when acquired. 5. The first and second input / output control means include input / output cache means for retaining data and maintaining data consistency with storage means (referred to as "coherency"), And the second system bus has a coherency function. The first input / output control means recognizes that the DMA write is held, and sends information indicating that the DMA write is held to the second input / output. Notifying the control means that if the address of the DMA write being held matches the address held in the I / O cache means, data is written to the I / O cache means and the DMA write is no longer held. When the held DMA write address does not match the address held in the input / output cache unit, the first DMA write address is recognized.
System bus acquisition request, and after acquiring the first system bus, it has a coherency function, and if it has a data block with the same address, a read that invalidates the cache (called "exclusive coherent read") ) Is output to the first system bus, the read response data is received, the data is written to the input / output cache, and the pending DMA write processing is recognized and the second data is output. The information processing apparatus according to claim 3, further comprising means for notifying the input / output control means. 6. The first I / O control means includes a first I / O control unit.
An input buffer register for inputting a transaction sent from the device control means via the O bus, a decoder for decoding the transaction stored in the input buffer register, a first flag indicating validity / invalidity of the transaction; , A register including at least a second flag indicating DMA read / write, a third flag indicating the presence or absence of an interrupt request, and a field for holding the transaction, and outputting the transaction to a first system bus. The first flag is turned on when the transaction transmission signal from the device control means is activated, and the transaction is valid, and the first flag is turned on. Status, and the second flag is The information processing apparatus according to claim 1, characterized in that the active the write execution signal when indicating the MA light. 7. The second input / output control means includes a second I / O control means.
An input buffer register for inputting a transaction sent from the device control means via the O bus, a decoder for decoding the transaction stored in the input buffer register, a first flag indicating validity / invalidity of the transaction; , A second flag indicating DMA read / write, a third flag indicating the presence or absence of an interrupt request, a register including at least a field for holding the transaction, and outputting the transaction to a second system bus. An output buffer register, wherein the first flag is turned on when a transaction transmission signal from the device control means is activated, and the transaction is valid, and the first flag is turned on. In the case shown, the third And a control unit that controls not to transmit the interrupt request from the device control unit to the arithmetic processing unit when the write signal line is in an active state. Item 10. The information processing apparatus according to Item 1.