JPH09148452A - Cmos output buffer with reinforced capability for protectingit from static discharge - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output buffer having a very high electrostatic discharge proof power with a very small occupied area. SOLUTION: An electrostatic discharge proof circuit comprises a PMOS- triggered lateral SCR unit PTLSCR 30 composed of a short-channel thin film oxide PMOS unit 12 inserted in the structure of a lateral semiconductor controlled rectifier(SCR) and an NMOS-triggered lateral SCR unit NTLSCR 50 composed of a short-channel thin film oxide NMOS unit 14 inserted in the structure of the lateral SCR. These CMOS units lower the conduction voltage of the lateral SCR from the original switching voltage to the snap back breakdown voltage of these units. The discharge proof circuit includes two parasitic transistors which are Dp between an output buffer 10 and VDD and Dn between this buffer and VSS and accordingly is protected efficiently by NTLSCR, Dn, Dp and PTLSCR in one-to-one correspondence to the four electrostatic discharge modes PS, NS, PD and ND.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electrostatic discharge protection circuits for complementary metal oxide semiconductor (CMOS) output buffers.

[0002]

BACKGROUND OF THE INVENTION Submicron CMOS semiconductor integrated circuits often suffer due to their lack of electrostatic discharge (ESD) protection. As CMOS semiconductor technology advances and reaches the sub-micron stage, manufacturing processes for various device structures, such as thinner gate oxides, shorter channel lengths, shallower sort / drain interfaces, low impurity drain structures and metals. Silicon diffusion layer is CMO
The electrostatic discharge protection capability of the S semiconductor circuit is significantly reduced. This is described in the following references:
C. Duvvury and A. Amerasekera, "ESD: a pervasive reli
ability concern forIC technologie ", Proc.of IEEE V
ol.81, no.5, pp.690-702, May 1993, and A. Ameraseke.
ra and C. Duvvury, "The impact of technology scaling
on ESD robustness and protection circuit design ",
1994 EOS / ESD Symp.proc.EOS-16, pp237-245.

In particular, an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMO) in a CMOS output buffer are used.
The drain of S) is usually connected directly to the output pad to drive an external load. Since the output buffer is in direct contact with the outside, the electrostatic discharge protection capability is significantly reduced when manufacturing it with submicron technology. C
The NMOS and PMOS devices in the output buffer are designed to have a very large device size in order to improve the electrostatic discharge protection capability of the MOS output buffer as well as to increase the ability to drive the output and external loads. However, even with such a large size device, submicron C
When manufactured with MOS manufacturing technology, the electrostatic discharge protection capability of the output buffer is still reduced by submicron manufacturing technology. This is described in the following references: TLPolgreen and A. Chatterjee, "Improving the
ESD failure threshold of silicided NMOS output tra
nsistors by ensuring uniform current flow ", IEEE T
rans.Electron Devices, Vol.39, no2, pp.379-388, 19
92; C. Duvvury, C. Diaz, and T. Haddock, "Achievingunif
orm NM0S device power distribution for submicron E
SD reliability ", 1992 IEDM Technical Digest, pp.131
-134; and C. Duvvury and C. Diaz, "Dynamic gate coup
ling of NMOS for efficient output ESD Protection ",
Proc.of IRPS, PP.141-150, 1992. Submicron CMO
In order to improve the electrostatic discharge protection capability of the S output buffer, a single layer "ESD implant" (electrostatic discharge protection character concentration value) photomask was added to the submicron CMOS manufacturing process to make the relatively strong device structure special. It was mounted in a CMOS semiconductor output buffer to improve the electrostatic discharge protection capability. However, the increase in these manufacturing processes and photomasks has resulted in an increase in the manufacturing cost of integrated circuits.

Another method is to add an electrostatic discharge protection device between the CMOS output buffer and the output pad to improve the electrostatic discharge protection capability of the submicron CMOS output buffer. Y.-JBLiu and S.Cagnina,
"Electrostatic dischage protection device for CMO
S Integrared circuit outputs ", US Pat. No. 4,73
Field oxide (N-type) device is used for 4,752, and N-type transistor (NM) in CMOS output buffer is used.
It has been described in an attempt to place it in parallel with the OS) to improve the electrostatic discharge protection capability of the CMOS output buffer. TCCh
En and DSCulver, "ESD Protection circuit" US Pat. No. 5,329,143 discloses a lateral N-P-N bipolar transistor placed in parallel with an N-type transistor (NMOS) in a CMOS output buffer to provide electrostatic capacitance for the CMOS output buffer. Attempts to improve discharge protection capabilities are described. However, the conduction voltages of the field oxide device and the lateral NPN bipolar transistor are generally higher than that of the short channel thin oxide NMOS device. Therefore, even if the above two types of parallel devices are used to improve the electrostatic discharge protection capability of the output buffer, the effect is very small.

DBScott, PWBosshart, and IDG
allia, 's "Circuit to improve electrostatic dischar
ge protection "U.S. Pat. No. 5,019,888 discloses that a large-sized thin oxide NMOS device in an output buffer is disassembled into a plurality of small-sized NMOS devices and arranged in parallel with each other, and each small-sized NMOS device is combined. Attempts to improve electrostatic discharge protection by adding a resistor in series are described: KFLee, A.Lee, MLMarmet, and K.
W. Ouyang, "Electrostatic Discharge protection ci
rcuit with bimodal resistance characteristics, "US Pat. No. 5,270,565 discloses that a field oxide device is connected to an output pad, which is placed in parallel with a thin oxide NMOS device in an output buffer, together with a thin oxide NMO.
Connect the drain of the S device to a series of N-type wells (N-Well)
It describes an attempt to improve the electrostatic discharge protection capability by adding to the resistance made by and connecting in series to the output pad.
GN Roberts, "output ESD protection circuit" US patent
In No. 5,218,222, a lateral NPN bipolar transistor is connected to the output pad and the NMO in the output buffer is connected.
Attempts have been made to place it in parallel with the S device, and at the same time add a series resistor between the output buffer and the output pad to improve the electrostatic discharge protection capability. In the above three documents,
Although both add a series resistance between the output buffer and the output pad, the increase of these non-rated series resistance can improve the electrostatic discharge protection capability of the submicron CMOS output buffer, but The drive capability output is limited, and the output signal is also caused by the series resistance, which causes a time delay. Therefore, the series resistance addition method results in a limitation in the application of the output buffer at high speed or heavy load condition.

In addition, a lateral semiconductor control rectifier (SC
The R) device is also used in a submicron complementary integrated circuit as an electrostatic discharge protection device to improve its electrostatic discharge protection capability. Lateral SCRs have already been found to provide the highest electrostatic discharge protection with the smallest footprint. A. Chatterjee and T. Polgreen, "A low-volt
age triggering SCR for on-chip ESD protection at
output and input pads ", IEEE Electron Device Lette
rs, Vol.12, No.1, pp.21-222, Jan.1991; and A. Chatte
rjee and T. Polgreen, "A low-voltage triggeri
ng SCR for on-chip ESD protection at output and i
nput pads ", Proc.of 1990 Symposium on VLSI Technol
Ogy, pp.75-76, named the improved lateral SCR structure as LVTSCR (Low Voltage Trigger SCR) and placed it in parallel with the NMOS device in the output buffer to improve electrostatic discharge protection capability. This type of LVTSCR device not only effectively improves the electrostatic discharge protection capability of the submicron CMOS circuit's output buffer, but does not require the addition of a series resistor between the output buffer and the output pad.

Electrostatic discharge (ESD) is a phenomenon where any input or output pin of the IC will probably have a positive or negative voltage polarity with respect to the VDD (high voltage source of the IC) or VSS (low voltage source of the IC) pin. Applied and discharged. Therefore CM
Regarding the output pins of the OS output buffer, there are four different discharge methods: (1) PS mode: electrostatic discharge when VDD bus is floating. Some output pins correspond to VSS bus, Has positive voltage polarity. (2) NS mode: There is electrostatic discharge when the VDD bus is floating. An output pin corresponds to the VSS bus and has a negative voltage polarity. (3) PD mode: There is electrostatic discharge when the VSS bus is floating. An output pin corresponds to the VDD bus and has a positive voltage polarity. (4) ND mode: There is electrostatic discharge when the VSS bus is floating. An output pin corresponds to the VDD bus and has a negative voltage polarity.

In the above four types of discharge modes, the output pin has an N-type transistor (NMOS) and a P-type transistor (PMO) in the output buffer of the CMOS integrated circuit (IC).
S) Damages the device. The electrostatic discharge failure threshold for a pin of an integrated circuit is then defined as the lowest electrostatic discharge voltage that the pin can withstand in four different electrostatic discharge modes. For example, some output pins are in PS, NS, PD mode
It can withstand an electrostatic discharge voltage of 6000 volts, but in ND mode it can only withstand an electrostatic discharge voltage of 1000 volts. In this case, the electrostatic discharge failure threshold for that pin is only 1000 volts. In the various references mentioned above, all electrostatic discharge protection measures are taken on the VSS terminal side of the output pin, and all additional parallel devices are also placed between the output pad and the VSS terminal. The device is not placed between the output pad and VDD pin. When measuring the electrostatic discharge of such an output buffer in ND mode or PD mode, the PMOS device (connected between the output pad and VDD pin) in the output buffer is easily destroyed by electrostatic discharge, and the output The pin's ESD failure threshold is not effectively increased. Therefore, the electrostatic discharge protection circuit of the output buffer must be able to provide the protection capability of the above-mentioned four kinds of electrostatic discharge modes together, and only then can the electrostatic discharge protection capability of the submicron CMOS integrated circuit be effectively provided. Can be improved.

[0009]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to overcome the deficiencies in the above references and to improve the electrostatic discharge protection capability of submicron complementary output buffers entirely.

[0010]

According to the present invention, two low voltage trigger SCRs and two diodes are arranged in a complementary connection system, and four types of electrostatic modes (PS, NS, PD and ND) are used. Protects against discharge. Also, these full-scale electrostatic discharge protection circuits and NMO in the CMOS output buffer
The S and PMOS devices are appropriately arranged in a mixed form to reduce the occupied area. The present invention can provide a relatively high ESD failure threshold with a relatively small footprint (including the output buffer and electrostatic discharge protection circuit), and the present invention provides a series resistance between the output buffer and the output pad. Since it is not used, the drive capability output by the output buffer and the delay time of the output signal are not affected.

The present invention is a CM with enhanced electrostatic discharge protection capability.
It relates to the OS output buffer. The CMOS output buffer has a circuit structure connected to an inverter, and has a thin oxide PMOS device and a thin oxide NMOS device therein. The source of this PMOS device is connected to VSS and the drain is also connected to the output terminal.
The common output terminal is connected to the output pad for packing the IC connection pins. This PMOS and NMO
The input gate electrode of the S device is connected to a circuit inside the IC and is controlled by the internal circuit of the IC.

In order to protect against electrostatic discharge, the present invention uses two parasitic diodes and two parasitic low voltage trigger SCRs as an electrostatic discharge protection device, and there are four types (PS, NS, PD). , ND) mode electrostatic discharge protection. The first parasitic diode Dp and the PMOS device of the output buffer are arranged in parallel, the anode of Dp is connected to the output pad and the cathode is connected to VDD (first supply voltage). This Dp protects against PD mode electrostatic discharge. The second parasitic diode Dn and the NMOS device of the output buffer are also arranged in parallel, the anode of Dn is connected to VSS (second supply voltage) and the cathode of Dn is connected to the output pad. And this Dn is NS
Protects against mode electrostatic discharge. The first low voltage trigger SCR is one PMOPS that triggers the lateral SCR and is called PTLSCR (PMOS-Triggered Lateral SCR). This PTLSCR
The device and the PMOS device in the output buffer are the output pad and VD
Located in parallel between D, this PTLSCR device protects against ND mode electrostatic discharge. The second low voltage trigger SCR has one NMOPS lateral SC
It triggers R and is called NTLSCR (NMOS-Triggered Lateral SCR). This NTLS
A CR device and an NMOS device in the output buffer are placed in parallel between the output pad and VSS, and the NTLSCR device protects against PS mode electrostatic discharge. Therefore, all four electrostatic discharge modes of the output pin are protected by corresponding devices on a one-to-one basis.
The failure threshold is obviously increasing.

This PTLSCR device incorporates a short channel thin oxide PMOS device into the structure of a lateral SCR, and the NTLSCR device has a short channel thin oxide N device.
The MOS device is incorporated into the structure of the lateral SCR. The thin oxide PMOS and NTLSCR devices are designed to trigger lateral SCR. When the PTLSCR device receives an ND mode electrostatic discharge, the drain of the PMOS device incorporated therein snaps back, triggers the PTLSCR device to conduct, and causes an electrostatic discharge current to flow to the bypass. . When the NTLSCR device is subjected to PS mode electrostatic discharge, the drain of the NMOS device incorporated therein is snapback destroyed, triggering this NTLSCR device to conduct, and passing an electrostatic discharge current to the bypass. Of. Therefore, the trigger voltage of the PTLSCR and NTLSCR drops to the snapback breakdown voltage of the PMOS and NMOS devices (between about 13 and 15V), and the trigger voltage of the original SCR (about 30 to 50V) is not reached again.
The TLSCR and NTLSCR can be designed to conduct faster and protect against output buffer breakdown due to electrostatic discharge as compared to PMOS and NMOS devices in CMOS output buffers.

The present invention can be implemented in any CMOS or Bipolar CMOS (BiCMOS) fabrication process, which is N-type well / P-type substrate, P-type well /
Regardless of whether it is an N-type substrate or a bipolar manufacturing technology. In the present invention, PTLSCR and NTLSW
A CR device is added to the CMOS output buffer, but the shareable part of it is shared with the device in the output buffer to reduce the occupied area, so that it can be used with the old design (or the one proposed in the past). By comparison, the present invention provides a higher electrostatic discharge protection capability for CMOS output buffers with a relatively smaller footprint.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

A. Circuit Structure FIG. 1 is a sketch of a circuit to which the present invention is applied. This Figure 1 shows a CMOS output buffer with enhanced electrostatic discharge protection.
10 is shown. The output buffer 10 includes a thin oxide PMOS device 12 that raises the threshold of the output voltage and a thin oxide NMOS device 14 that lowers the threshold of the output voltage. The source of PMOS device 12 is connected to VDD and the source of NMOS device 14 is connected to VSS. The drains of the PMOS device 12 and the NMOS device 14 are united to form an output terminal 17. The output terminal 17 is connected to the output pad 20 via the connection line 18.
The pre-stage device 16 is an IC internal circuit that outputs a signal to the gate electrode of the output buffer 10 to control the voltage threshold value on the output pad.

In order to improve the electrostatic discharge protection capability, PT
The LSCR device 30 and the PMOS device 12 are connected in parallel between VDD and the connection line 18, and the NTLSCR device 50 and N are connected.
The MOS device 14 is connected in parallel between the connection line 18 and VSS. The CMOS output buffer 10 also includes two parasitic diodes Dp60 and Dn70. The Dp60 diode is placed in parallel with the PMOS device 12 and its anode is connected to the connection line 18, and the Dn70 diode is placed in parallel with the NMOS device 14 and its anode is connected to VSS.

The PTLSCR device 30 is for ND mode electrostatic discharge protection, the Dp diode 60 is for PD mode electrostatic discharge protection, the NTLSCR device 50 is for PS mode electrostatic discharge protection, and the Dn diode 70 is for NS mode. It is for electrostatic discharge protection. Therefore, the four types of electrostatic discharge modes generated on the output pad 20 are all protected in a one-to-one correspondence, and in addition, these PTLSCR, NTLSCR,
The Dn, Dp device can immediately provide a direct electrostatic discharge channel to allow the electrostatic discharge current to flow to the bypass.

The conduction voltage of the PTLSCR (NTLSCR) device is equal to the snapback breakdown voltage of the short channel thin oxide PMOS (NMOS) device incorporated in the PTLSCR (NTLSCR) device and not the trigger voltage of the original lateral SCR. This short channel thin oxide PMOS
The snapback breakdown voltage of the NMOS device and the NMOS device varies depending on the manufacturing process, but generally speaking, the snapback breakdown voltage is lower than that of the thin oxide film. This snapback breakdown voltage is also related to the channel length, and generally speaking, the snapback breakdown voltage of PMOS and NMOS devices with shorter channel lengths is lower.

Therefore, the PTLSCR device 30 (NTLSCR
Protecting the PMOS device 12 (NMOS device 14) with the device 50) protects it from damage due to electrostatic discharge,
PMOS embedded in CR device (NTLSCR device)
(NMOS) channel length is PMOS in output buffer
It is slightly shorter than the channel length of device 12 (NMOS device 14). In this way, the PTLSCR device 30 (NTLS
Since the conduction voltage of the CR device 50) is lower than the snapback breakdown voltage of the PMOS device 12 (NMOS device 14), it should be conducted first and the electrostatic discharge current should be passed to the bypass to protect the output buffer. You can do it.

Since the semiconductor-controlled rectifier originally has a very good electric energy conductivity and has a very high withstand voltage against electrostatic discharge (compared with other electrostatic discharge protection devices), the present invention It is possible to effectively improve the protection capability of the output buffer against electrostatic discharge without adding a series resistor between the output buffer and the output pad, without increasing the delay time of the output signal. It does not affect the output capability of the output buffer. B. Device Structure FIG. 2 is a device sectional view of the PMOS device 12 and the PTLSCR device 30 of FIG. In FIG. 2, the PTLSCR device 30 and the PMO are shown.
The S device 12 coexists and is manufactured as an N-type well / P-type substrate to reduce the occupied area.

As shown in the semiconductor structure 100 of FIG. 2, the PMOS device 12 in the P-type substrate 32 / N-type well 34 comprises P-type high carrier concentration regions 31 and 33. The high carrier concentration region 31 is the source of the PMOS device 12, which source is connected to VDD. The high carrier concentration region 33 is the drain of the PMOS device, which drain is connected to the output pad 20, and the gate electrode 35 of the PMOS device 12 is connected to the pre-stage device 16. In addition, the N-type high carrier concentration regions 45 and 47 are in the same N-type well 34, and these high-carrier concentration regions 45 and 47 are connected to VDD to provide the bias voltage of the N-type well 34. , PMOS
It forms the bulk of the device 12.

In FIG. 2, the parasitic diode Dp60 forms a junction surface between the N-type well 34 and the P-type high carrier concentration region 33. In addition, the region 98 of high P-type carrier concentration is P
It is a protective loop on the mold substrate 32 that prevents latchup. This protection loop is P on the layout.
It is possible to have the MOS device 12 and the PTLSCR device 30 enclosed therein. This P-type high carrier concentration region
98 is connected to VSS.

The PTLSCR device 30 includes a lateral SCR
(P-type high carrier concentration region 70, N-type well 34, P
A substrate 32 and an N-type well 34 including another N-type high carrier concentration region 72) and a short channel thin oxide PMOS device 90. PTLS
The PMOS device 90 incorporated in the CR device 30 includes a P-type high carrier concentration region 70, the source of which is
Connected to VDD. Further, the region 80 having a high P-type carrier concentration extends over the joint surface between the N-type well 34 and the P-type substrate 32,
It is the drain of the PMOS device 90. This drain does not connect anywhere, it just spans between the two mating faces. In addition, the gate electrode 82 of the PMOS device 90 is VDD
Connected to

The purpose of incorporating the PMOS device 90 into the lateral SCR to form the PTLSCR device 30 is the PTLSC.
When the R device 30 receives the ND mode electrostatic discharge, the PMO
The drain 80 of the S device 90 is used in a snapback broken state to trigger and bring the lateral SCR into conduction. The conduction voltage of this PTLSCR device 30 is a PMOS device.
Equal to a snapback breakdown voltage of 90, not the same as the original trigger voltage (between about 30 and 50V). This PTLSC
When the R device conducts, its holding voltage is the original lateral SC.
It is equal to the holding voltage of R (about 1V), but the conduction resistance is very low (about 2-5 ohms). The gate electrode 82 of the PMOS device 90 is connected to VDD so that the PMOS device 90 remains off when the integrated circuit is operating normally.

Shown in FIG. 3 is a cross-sectional view of semiconductor structure 200, NMOS device 14 and NTLSCR device 50.
In FIG. 3, the NTLSCR device 50 and the NMOS device 14 coexist to reduce the occupied area. Shown in FIG. 3 is an NTLSCR device 50 and an NMOS device 14 fabricated as an N-type well / P-type substrate structure. NM
In the OS device 14, the N-type high carrier concentration regions 51 and 53 respectively constitute the source and the drain thereof, and the P-type substrate 32 passes through the P-type high carrier concentration regions 71 and 73.
Connected to VSS to provide the bulk bias voltage for NMOS device 14. Further, the gate electrode 52 is connected to the front stage device 16
It is connected to the. The parasitic diode Dn70 is composed of an N-type high carrier concentration region 53 (that is, the drain of the NMOS device 14) and a P-type substrate 32. In FIG. 3, the N-type high carrier concentration region 75 constitutes a protection loop for preventing latch-up in the N-type wells 54 and 58, and this loop has a layout in which the NMOS device 14 and the NTLSCR device are protected.
Fifty are enclosed in it. This N-type high carrier concentration region 75 is connected to VDD.

The NTLSCR device 50 comprises a lateral SCR and a short channel thin oxide NMOS device 98. This lateral SCR is connected to the output pad at the P-type high carrier concentration region 91, and the N-type well 58, the P-type substrate 32 and another N-type well 56 (the N-type high carrier concentration region 92 are Connect to VSS). NMOS device
In the region 98, the region 92 having a high N-type carrier concentration serves as the source and is connected to VSS, and another region 93 having a high N-type carrier concentration serves as the drain. The N-type high carrier concentration region 92 laterally straddles the N-type well 56 and the P-type substrate 32.
Has entered. Another N-type high carrier concentration region 93
Extends over the junction surface between the P-type substrate 32 and the N-type well 56, the region 93 having a high N-type carrier concentration is not connected to any other region. Also the gate electrode of the NMOS device 98
94 is connected to VSS.

The purpose of incorporating the short channel thin oxide NMOS device 98 into the structure of the lateral SCR to form the NTLSCR device 50 is to provide a drain 93 of the NMOS device 98 when the NTLSCR device undergoes PS mode electrostatic discharge. Is used in the snapback destruction state to trigger and bring the lateral SCR into conduction. Therefore, this NTLSC
The conduction voltage of the R device 50 is equal to the snapback breakdown voltage of the NMOS device 98 and not the original trigger voltage of the lateral SCR (about 30-50V). When this NTLSCR device conducts, its holding voltage is equal to the holding voltage of the original lateral SCR (around 1V), but the conduction resistance is very low (about 2-5 ohms).

2 and 3 show the device structure in the N-type well / P-type substrate of the PTLSCR device and the NTLSCR device, but FIG. 4 and FIG. 5 show the PTLS device.
It is a structure of a device when a CR device and an NTLSCR device are formed on a P-type well / N-type substrate. PT in Figures 4 and 5
The operating principle and design concept of both the LSCR device and the NTLSCR device are the same as those of the devices of FIGS. 2 and 3, and they are realized by different manufacturing processes. Shown in FIG. 4 is a semiconductor device structure 300 realized during the manufacturing process of a P-type well and an N-type substrate.
A device 12 and a PTLSCR device 30 are included. PMOS
Device 12 is comprised of P-type high carrier concentration regions 310 and 312, the sources and drains of which are connected to VDD and output pad 20, respectively. The gate electrode of the PMOS device 12 is connected to the pre-stage device 16. The PMOS device 12 has a lateral SCR (P-type well 306 is connected to VDD via a P-type high carrier concentration region 352, and is connected to the N-type substrate 302, P-type well 308, and output pad 20. The N-type high carrier concentration region 351) and the PMOS device 350 coexist. The source and drain of the PMOS device 350 are P-type high carrier concentration regions 352 and 354, respectively, and a P-type well 306 and another P-type well 308 and N-type substrate 302, respectively.
Plays its role across the joint surface of. Another P
The wells 304 and 308 are regions 32 of high P-type carrier concentration.
Connect to VSS via 0 to connect PMOS device 12 and PTLS
It surrounds the entire CR device 30 and forms a protective loop to prevent latch-up.

FIG. 5 shows the semiconductor structure 400 as P
Type well / N-type substrate manufacturing process, which includes NMOS device 14 and NTLSCR device 50.
It is included. The NMOS device 14 is composed of N-type high carrier concentration regions 420 and 422, and has a P-type well 40.
Within 6 are the source and drain. Also NMO
The gate electrode 424 of the S device is connected to the pre-stage device 16. The P-type well 406 is a region 43 having a high P-type carrier concentration.
Connect to VSS via 0 to connect the bulk of NMOS device 14
Provides a bias voltage. The NTLSCR device 50 is composed of a lateral SCR and an NMOS device 450, and the lateral SCR is connected to the P-type well 408 (connected to the output pad 20 via the P-type carrier-rich region 430), the N-type substrate 302, and P-type. The well 406 and the N-type high carrier concentration region 432 (connected to VSS). In the NMOS device 450, N-type high carrier concentration regions 432 and 434 form its source and drain, and its gate electrode 435 is connected to VSS. The N-type high carrier concentration region 434 laterally extends over the junction surface between the N-type substrate 302 and the P-type well 406, but is not connected anywhere. Another N-type well high carrier concentration region 410 (connected to VDD) is on the N-type substrate 302, and is used for the NMOS device 14 and NT.
It surrounds the LSCR device 50 and forms a guard loop to prevent latch-up. C. Layout Example FIG. 6 shows a layout plan view 600 of the semiconductor structure 100 of FIG. 2 with a dense layout. The line AA 'in FIG. 6 corresponds to the transverse line in the cross-sectional view of FIG.
In FIG. 6, the PMOS device 12 has three parallel finger-like protrusions 33, which are also drains of the PMOS device 12. The PTLSCR device 30 is on the right side of FIG. In addition, the loop 98 to prevent latch-up is P at the outermost edge.
It encloses the entire MOS device 12 and the PTLSCR device 30.

FIG. 7 is a layout plan view 700 of the semiconductor structure 200 of FIG. 3 with a dense layout. The line BB 'in FIG. 7 corresponds to the transverse line in the sectional view of FIG. In FIG. 7, the NMOS device 14 has three finger-like projections 53 that are parallel to each other.
There are 14 drains. The NTLSCR device 50 is on the right side of FIG. In addition, a loop 75 for preventing latch-up surrounds the entire NMOS device 14 and NTLSCR device 50 at the outermost portion.

6 and 7 show examples of layouts in which the present invention is applied to the manufacturing process of an N-type well / P-type substrate.
By comparison, the layout embodiments of semiconductor structures 300 and 400 of FIGS. 4 and 5 are similar to those shown in layout diagrams 600 and 700 of FIGS. 6 and 7. This is because the manufacturing process is only changed to the P-type well / N-type substrate manufacturing process. However, the layout format of the present invention is not limited to the examples shown in FIGS. 6 and 7, and the present invention can be realized by other layout formats. D. Circuit operation principle (1) CMOS semiconductor integrated circuit is operating normally: VDD is 5V when the integrated circuit is operating normally.
Is connected to the power supply of and VSS is grounded. In this case the gate electrodes of PMOS device 90 and NMOS device 98 are connected to their respective sources,
Since the MOS device 98 is in the OFF state, the PTLSCR device is
30 and the NTLSCR device 50 are also in the OFF state, and the output buffer composed of the NMOS device 12 and the PMOS device 14 (see FIG. 1) outputs a signal to the output pad 20 based on the instruction of the signal of the pre-stage device 16. There is.

In addition, the parasitic diodes Dp60 and Dn70 output signals and exhibit a voltage fixing (clamping) function. When the voltage signal causes an over-level or low-level phenomenon at the output pad 20, the diode Dp60 fixes the high voltage threshold to the maximum threshold of about VDD + 0.6V and the diode Dn70 keeps the low voltage. Threshold about VSS-0.6V
Fixed to the lowest threshold of. Therefore, in the normal operation state (VDD = 5V, VSS = 0V), the voltage threshold of the output pad 20 is fixed between about 5.6V and -0.6V. (2) State of electrostatic discharge: If the integrated circuit is floating, it can be easily destroyed by electrostatic discharge.
Regarding the electrostatic discharge for each pin of the integrated circuit, there are four possible discharge modes. PS, NS, PD and ND modes (details have been described in the prior art section). In this case, the PTLSCR device 3 added in the present invention
0, NTLSCR device 50 and parasitic diodes Dp60 and D
The n70 will have a protective effect.

When a PS mode electrostatic discharge occurs at the output pad 20, this electrostatic voltage first conducts to the anode of the NTLSCR device 50 (the P-type high carrier concentration region 91 in FIG. 3) and then N It conducts to a region 93 having a high N-type carrier concentration via the mold well 58. This N-type high carrier concentration region 93 is also the drain of the NMOS device 98. This electrostatic discharge voltage is directed to the drain of the NMOS device 98 and falls into a snapback breakdown condition, first fixing the voltage on the output pad. When a snapback breakdown occurs at the drain of the NMOS device, this breakdown current flows from the N-type well 58 to the P-type substrate 32, triggering the lateral SCR to conduct and also the NTLSCR device 50 to conduct. The holding voltage of the connected NTLSCR device 50 is about 1-2V.
Since the conduction resistance is considerably low, the bypass path (through the NTLSCR device) is opened from the output pad 20 and the electrostatic discharge current flows to VSS.

Since the NTLSCR device 50 has a very high electric energy conductivity, it can receive a relatively high electrostatic discharge current with a relatively small occupied area. Therefore, if the output buffer is electrostatically discharged in PS mode, it can be effectively protected by the NTLSCR device. Output pad for electrostatic discharge in NS mode
If it occurs at 20, this negative electrostatic voltage is NMOS
Conduction is made to the drain of the device 14, that is, the region 53 (in FIG. 3) where the N-type carrier concentration is high. And the parasitic diode D
n70 conducts in the positive direction and provides a current path for electrostatic discharge. Therefore, the electrostatic voltage on the output pad is
Fixed by this, this output buffer is protected. That is, even if the diode conducts in the positive direction, it has a high electrostatic discharge protection capability.

When a PD mode electrostatic discharge occurs on the output pad 20, this positive electrostatic voltage conducts to the drain of the PMOS device 12, ie, the P-type carrier-rich region 33 (in FIG. 2). . The parasitic diode Dp60 then conducts in the positive direction and provides a current path for electrostatic discharge. Therefore, the electrostatic voltage on the output pad is fixed by the diode Dp and this output buffer is protected. That is, Dp
Has a high electrostatic discharge protection capability even when it conducts in the positive direction.

When an ND-mode electrostatic discharge is generated at the output pad 20, this negative electrostatic voltage causes the negative voltage of the cathode of the PTLSCR device 30 (the N-type high carrier concentration region 7 in FIG. 3).
2) and then to the region 80 having a high P-type carrier concentration via the P-type substrate 32. This P-type high carrier concentration region is also the drain of the PMOS device 90. This negative electrostatic discharge voltage is directed to the drain of the PMOS device 90 and falls into a snapback breakdown condition, first fixing the negative voltage on the output pad. When snapback breakdown occurs at the drain of the PMOS device 90, this breakdown current flows from the N-type well 34 to the P-type substrate 32, and the lateral SC
R is triggered to conduct, and the PTLSCR device 30 is also triggered to conduct. Conducted PTLSCR device 30
Has a holding voltage of about 1 to 2V and its conduction resistance is considerably low, so that the bypass path (via the PTLSCR device) is opened from the output pad 20 and the electrostatic discharge current is VD.
It flows to D. Since the PTLSCR device 30 has a very high electrical energy conductivity, it can receive a relatively high electrostatic discharge current with a relatively small footprint. Therefore, if the output buffer is electrostatically discharged in the ND mode, it can be effectively protected by the PTLSCR device 30. E. Conclusion The present invention proposes an effective electrostatic discharge protection circuit, and
S Semiconductor output buffer is protected. Since this electrostatic discharge protection circuit can be closely coupled with the CMOS semiconductor output buffer in layout, it is possible to provide a relatively large electrostatic discharge protection capability with a relatively small footprint.

The CMOS semiconductor output buffer includes a PMOS device for increasing the threshold of the output voltage and an NMOS device for decreasing the threshold of the output voltage. The electrostatic discharge protection circuit of the present invention includes a semiconductor controlled rectifier PTLSCR device triggered by a PMOS device and a semiconductor controlled rectifier NTLSCR device triggered by an NMOS device. The PTLSCR device uses P in the output buffer.
It can be combined with a MOS device and the NTLSCR device can also be combined with an NMOS device in the output buffer. This PTLSCR device (NTLSCR device)
Since the conduction voltage is equal to the snapback breakdown voltage of the PMOS device (NMOS device) and not the trigger voltage of the original semiconductor controlled rectifier, the PTLSCR device and NT
LSCR devices can be designed with a lower electrostatic discharge voltage compared to PMOS and NMOS devices in CMOS metal oxide semiconductor output buffers. Therefore PMO
The S device and the NMOS device can effectively protect the CMOS semiconductor output buffer. Separately in this invention
Two parasitic diodes Dp and Dn are also used to protect against electrostatic discharge.

All four types of electrostatic discharge, PS, NS, PD and ND modes are protected one by one by NTLSCR device, Dn, Dp and PTLSCR device. In the present invention, the PTLSCR device and the NTLSCR device are added, because these two devices originally have a very high electrostatic discharge receiving ability, and a very large device is not necessary. In addition to this, the layout can be combined with the device in the output buffer. Therefore, the present invention can provide a relatively high electrostatic discharge protection capability with a relatively small footprint.

The electrical circuit and device structure of the present invention is compatible with any CMOS and BiCMOS fabrication process,
It is also possible to broaden the range of application of the present invention by applying it to N-type well / P-type substrate, P-type well / N-type substrate, or twin well manufacturing technology. Although the design concept of the present invention and the examples thereof have been described above, those used therein are not limited to the present invention, and therefore, those skilled in the art can further improve the applicability without departing from the spirit and scope of the present invention. It is possible to produce something rich in. Therefore, the scope of protection of the present invention is limited only to the scope of patent application, and is based on that.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit connection of the present invention.

FIG. 2 shows a P in a CMOS output buffer according to the present invention.
It is sectional drawing of the Example which made the MOS device and the PTLSCR device coexist on the P-type board | substrate.

FIG. 3 illustrates N in a CMOS output buffer according to the present invention.
It is sectional drawing of the Example which made the MOS device and the NTLSCR device coexist on the P-type board | substrate.

FIG. 4 illustrates a P in a CMOS output buffer according to the present invention.
It is sectional drawing of the Example which made the MOS device and the PTLSCR device coexist on the N-type board | substrate.

FIG. 5 illustrates N in a CMOS output buffer according to the present invention.
It is sectional drawing of the Example which made the MOS device and the NTLSCR device coexist on the N-type board | substrate.

FIG. 6 is a plan view of FIG.

FIG. 7 is a plan view of FIG.

[Explanation of symbols]

10 Output buffer 12 PMOS device 14 NMOS device 16 Pre-stage device 17 Output terminal 18 Connection line 20 Output pad 30 PTLSCR device 32 P-type substrate 34, 54, 58 N-type well 31, 33, 45, 51, 53, 47, 70, 71, 73, 75, 80, 98, 31
0, 312, 320, 350, 354, 351, 352 High carrier concentration region 35, 82 Gate electrode 50 NTLSCR device Dp60, Dn70 Parasitic diode 100, 200, 400 Semiconductor structure 90, 350 PMOS device 300 Semiconductor device structure 302 N type Substrate 308 P-well 600, 700 Layout plan 33, 53 Fingers 75, 95, 98 Loop

Claims (20)

[Claims] 1. A thin oxide PMOS device having a source connected to a VDD power supply, a thin oxide NMOS device having a source connected to a VSS power supply, a first low voltage triggered silicon controlled rectifier (SCR), and Second low voltage trigger SCR,
A complementary metal oxide semiconductor (C) including a first parasitic diode and a second parasitic diode and including an electrostatic discharge protection circuit.
MOS) output buffer, the drains of the PMOS device and the NMOS device are connected to each other and to the output pad, and the first low voltage trigger SCR is connected between VDD and the output pad for ND mode electrostatic discharge. Against protection, the second low voltage trigger SCR is connected between output pad and VSS to protect against PS mode electrostatic discharge, the first parasitic diode is connected between VDD and output pad, PD CMOS output buffer that protects against mode-mode electrostatic discharge and the second parasitic diode is connected between the output pad and VSS to protect against NS-mode electrostatic discharge. 2. The CMOS output buffer according to claim 1, having a P-type well / N-type substrate structure. 3. The CMOS output buffer according to claim 1, having an N-type well / P-type substrate structure. 4. The first low voltage trigger SCR comprises a lateral SCR and a PMOS device, the anode of the lateral SCR is connected to VDD, its cathode is connected to the output pad, and the PMOS device is its snapback. The CMO of claim 1, wherein the breakdown voltage triggers the lateral SCR.
S output buffer. 5. The second low voltage trigger SCR comprises a lateral SCR and an NMOS device, the anode of the lateral SCR is connected to the output pad, its cathode is connected to VSS, and the NMOS device is its snapback breakdown. The CMOS of claim 1 wherein the voltage triggers the lateral SCR.
Output buffer. 6. A first PMO having a drain connected to the output pad and a source connected to the first and second power supplies, respectively.
S and the first NMOS, the anode is connected to the first power supply, the cathode is connected to the output pad, the snapback breakdown voltage of the first lateral S
A first lateral SCR that includes a second PMOS device that triggers a CR, a second anode that connects the anode to the output pad and a cathode that triggers the second lateral SCR at the second power supply and its snapback breakdown voltage. A CMOS output buffer with an ESD protection circuit consisting of a second lateral SCR connected to an NMOS device. 7. The CMO of claim 6 including a first parasitic diode connected between the output pad and the first power supply.
S output buffer. 8. The CMO of claim 6 including a second parasitic diode connected between the output pad and the second power supply.
S output buffer. 9. A semiconductor substrate having an anode connected to a first power supply and a cathode connected to an output pad of an integrated circuit,
The output buffer in an integrated circuit consisting of a first low voltage triggered lateral SCR incorporating a PMOS device that triggers a lateral SCR with its snapback breakdown voltage
A semiconductor device that provides D protection. 10. The semiconductor device according to claim 9, wherein the cathode of the first lateral SCR comprises an N ⁺ type well formed in an N type well on a P type substrate. 11. The semiconductor device according to claim 9, wherein the cathode of the first lateral SCR is a P ⁺ type well formed in a P type well in an N type substrate. 12. The drain of the PMOS device is formed across the junction of the substrate and the first region of the substrate, and the source thereof is formed across the junction of the semiconductor substrate and the second region. 10. The semiconductor device according to claim 9, wherein the substrate is of one dopant type, and the first region and the second region are of pump dopant type. 13. The semiconductor device according to claim 9, wherein the drain is a P ⁺ type well. 14. A thin oxide PMOS device comprising:
The MOS device and the first low voltage trigger lateral SCR are integrally formed, and the drain of this thin oxide film PMOS device is formed such that the P-type high carrier concentration region is arranged in parallel on the semiconductor substrate. This thin oxide PMOS device is the first low voltage trigger lateral SCR in layout.
10. The semiconductor device according to claim 9, wherein the semiconductor device is arranged in parallel with and is connected in parallel. 15. A second low voltage triggered lateral SCR.
And located on the same semiconductor substrate with the first lateral SCR, the anode of which is connected to the output pad and the cathode of which is connected to the second reference voltage. NMOS device is included, this N
10. The semiconductor device according to claim 9, wherein the MOS device conducts the second low voltage trigger lateral SCR when its drain snaps back. 16. A second low voltage triggered lateral SCR.
16. The semiconductor device according to claim 15, wherein the anode is formed such that a region having a high P-type carrier concentration is present in the N-type well and both are present on the P-type substrate. 17. A second low voltage triggered lateral SCR.
16. The semiconductor device according to claim 15, wherein said anode has a region having a high P-type carrier concentration in a P-type well, and these regions are both present on an N-type substrate. 18. A drain of an NMOS device laterally extends across a junction surface between the semiconductor substrate and a first region, and a source thereof horizontally extends across a junction surface between the semiconductor substrate and a second region. 16. The semiconductor device according to claim 15, wherein the carrier concentration is of a second type, and the first region and the second region are of a second type carrier concentration. 19. The semiconductor device according to claim 15, wherein the drain of the NMOS device is an N-type high carrier concentration region. 20. A thin oxide NMOS device is included to be combined with a second low voltage trigger lateral SCR to save space and the drain of the thin oxide NMOS device is of an N type carrier concentration. The thin region NMOS device is formed by arranging the high regions in parallel with each other on the semiconductor substrate.
The semiconductor device according to claim 15, wherein the semiconductor device is arranged in parallel with R and is connected in parallel.