JPH09147564A - Memory cell array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by connecting a low potential power source node of memory cell to a common artificial ground line and changing over this artificial ground line to the low level voltage or high level voltage for holding the memory cell information depending on the signal for selecting the bit line. SOLUTION: In the memory cells on the non-selected bit lines among the activated memory cells, the source voltage of the transistors TRQ3 and TRQ4 in the memory cell 1 become high since the artificial ground line is connected to the high voltage source 4. TRQ4 is in the conductive condition but the gate- to-source voltage is reduced and thereby a conductive resistance becomes high. As a result, a current flowing into the memory cell from the bit line via TRQ6 and TRQ4 is reduced to realize low power consumption. Meanwhile, the artificial ground line in the memory cells on the selected bit lines among the activated memory cells is connected to the low voltage line 5 and the source voltage of the TRQ3, TRQ4 in the memory cell becomes low. The gate-to-source voltage of TRQ3 becomes near 0V, resulting in non-conductive condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory (SRAM), and more particularly to a special purpose LS.
The present invention relates to a memory cell array in which power consumption during effective operation is reduced by applying it to a memory incorporated in an I (ASIC) or the like.

[0002]

2. Description of the Related Art It is important that the time required for designing an SRAM mounted on an ASIC or the like is short, and a bit slice structure is adopted so as to be able to promptly meet a request for input / output data width (number of bits). A conventional SRAM memory cell array having a bit slice structure is shown in FIG.

FIG. 4 shows the structure of the peripheral portion of the memory cell array corresponding to 1-bit input / output. 1'is a memory cell, WL is a word line for transmitting a memory cell selection signal, and BL0 and * BL0 are bit line pairs for transmitting a differential signal. The same applies to BL1 and * BL1. Note that * indicates inversion. Only one of the word lines WL is controlled by a row address signal input from the outside so that only one of the word lines WL is selected. VDD is a high potential power supply.

In FIG. 4, for convenience of explanation, one word line WL in the selected state and two bit line pairs BL0 and * BL0, B are selected.
Although only L1 and * BL1 are shown, actually, a plurality of word lines and a plurality of bit line pairs are provided, and memory cells are arranged at the intersections thereof, so that a plurality of word lines and bit line pairs are formed. The memory cell array is configured such that the memory cells of (1) are arranged.

Reference numeral 2 is a pull-up element (load) of a bit line pair.
It is. DL and * DL are data line pairs for transmitting differential signals, and although not shown, a data input / output circuit is arranged at one end thereof. S0 and * S0 are interlock switches that are turned on / off at the same time, and are controlled by the bit line pair selection signal Y0. The same applies to the switches S1 and * S1 provided at one end of the bit line pair BL1 and * BL1 and is controlled by the selection signal Y1.

The above switches S0 and * S0, S1 and *
A switch group such as S1, ... constitutes a multiplexer 3, and a selection signal Y0 so that only one set of bit line pairs is connected to the data lines DL and * DL by an externally input column address signal. Y1, ... Is controlled.

FIG. 5 is a circuit diagram showing a specific structure of the memory cell 1'in FIG. Q1 and Q2 are PchMOS transistors, and Q3 ', Q4', Q5 and Q6 are NchMOS transistors. The transistors Q1 and Q3 'and the transistors Q2 and Q4' each form a CMOS inverter. The two CMOS inverters connected in anti-parallel form a prep-flop, and its electrical state (transistors Q3 ', Q4'). 1-bit information is stored depending on the difference between the drain voltage (high level and low level). Transistors Q5 and Q6 are switches (first switch) for connecting and activating the memory cell 1'to the bit line pair.
Switch means).

The memory cell 1'is activated by controlling the word line WL to a high level voltage so that the transistors Q5 and Q6 are rendered conductive. that time,
A current flows from the bit line BL or * BL into the memory cell 1'according to the stored contents, and the bit line B on the side where the current flows
A voltage drop is generated across the pull-up element 2 connected to L or * BL. As a result, a minute differential signal corresponding to the stored content appears between the bit lines BL and * BL, and the stored content is read by detecting the difference with a sense circuit provided in the input / output circuit (not shown). .

[0009]

By the way, due to the structure of the above-mentioned memory cell array, one word line is connected with a number of memory cells corresponding to the number of multiplexes of a bit line pair. Therefore, when a specific one word line is selected, all the memory cells on the selected word line are activated and a current flows from each bit line to each memory cell. As a result, an amount of power consumption corresponding to the number of multiplexed bit lines occurs.

Of this power consumption, only the one that is consumed by one memory cell on the bit line pair specified by the multiplexer is effectively consumed, and the power of the remaining memory cells is wasted. It was being consumed. Since this waste increases with the number of multiplexes of the bit line pair, it is a problem because it is a factor that limits the memory capacity mounted on the ASIC due to the restriction of power consumption.

An object of the present invention is to solve the above problems and to provide a memory cell array in which the power consumption in the operating state is reduced.

[0012]

SUMMARY OF THE INVENTION A first invention has a memory cell which is composed of a flip-flop for holding 1-bit information and a first switch means for controlling activation / inactivation of the cell by a selection signal. In the memory cell array having a plurality of the memory cells arranged in the word line direction for transmitting the selection signal and the bit line direction for transmitting input / output data, the low potential power supply node of the plurality of memory cells connected to the same bit line. Is connected to a common pseudo ground line,
When the bit line is selected, a ground potential or a low-level first voltage close to the ground potential is applied to the pseudo-ground line, and when the bit line is not selected, the first voltage is higher than the first voltage and the information And a second switch means for applying a second voltage capable of holding the voltage.

According to a second invention, in the first invention, means for applying the second voltage to the pseudo ground line is provided, and the bit line is selected in place of the second switch means. The pseudo ground line is connected to the first voltage when the bit line is on, and the third switch means is connected when the bit line is not selected.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment of the Invention] FIG. 1 is a circuit block diagram of a memory cell array showing a first embodiment of the present invention, showing a configuration when applied to an SRAM having a bit slice structure. This corresponds to a memory cell array configuration for 1 bit of input / output. The same components as those described with reference to FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

Reference numeral 1 is a memory cell, and V _GND0 and V _GND1 are pseudo ground lines provided corresponding to bit line pairs (BL0 and * BL0, BL1 and * BL1). The numbers at the end indicate the correspondence with bit line pairs. This pseudo ground line is provided independently for each bit line pair. 4 is a high voltage source of voltage E _H , 5
Is a low voltage source of the voltage E _L , and the voltages have a relationship of “E _H > E _L ”.

The higher the voltage E _H of the high voltage source 4, the greater the effect of reducing the power consumption of the memory cell on the non-selected bit line when the memory cell is activated. I can't keep up. The upper limit is "VDD
-| Vth | ". Here, Vth is the threshold voltage of the PchMOS transistor or the NchMOS transistor, which is the larger absolute value.

The lower the voltage E _L of the low voltage source 5, the faster the reading of information from the memory cell selected by the bit line. For example, the voltage E _L may be the ground potential (GND), in which case no special circuit means is required. Further, this voltage E _L is as long as the pn junction formed between the source of the MOS transistor and the substrate is not forward biased.
It can be a negative value.

SW0 is a changeover switch (second switch means) and is controlled by a signal Y0 for selecting the bit line pair BL0 and * BL0. That is, when selecting the bit line pair BL0 and * BL0 by the signal Y0, the switch SW0 connects the pseudo ground line V _GND0 to the high voltage source 4 and applies the voltage E _H thereto, and when not selected. The low voltage source 5 is connected to apply the voltage E _L. SW1 is also a changeover switch (second switch means), and is a bit line pair BL1 and * BL.
The signal Y1 for selecting 1 is controlled similarly to the switch SW0.

FIG. 2 is a circuit diagram showing a circuit configuration of the memory cell 1 in FIG. The same parts as those shown in FIG. 5 are designated by the same reference numerals. Q3 and Q4 are NchMOS transistors. Here, unlike the conventional memory cell 1'shown in FIG. 4, the source nodes (low potential power supply nodes) of the transistors Q3 and Q4 are connected to the pseudo ground line V _GND , not to the ground (GND). .

Now, in terms of the structure of the memory cell array described above,
The number of memory cells 1 corresponding to the number of multiplexes of the bit line pair is connected to the word line. When a specific one word line is selected, all the memory cells on the selected word line are activated, and the memory cell 1 from the bit line is activated.
Current flows into the. This amount of current depends on the voltage level of the pseudo ground lines V _GND0 , V _GND1 , ....

For convenience of explanation, in the flip-flop in the memory cell 1, it is assumed that the drain of the transistor Q3 has a high level voltage and the drain of the transistor Q4 has a low level voltage. First, among the activated memory cells, the memory cells on the non-selected bit line have the pseudo ground line connected to the high voltage source 4, so that the transistors Q3 and Q4 in the memory cell 1 have a high source potential (voltage E _H ) According to the above assumption, the transistor Q4 is in the conductive state, but since the voltage between the gate and the source decreases, the conductive resistance increases. As a result, transistors Q6 and Q
The current flowing from the bit line to the memory cell via 4 is reduced, and low power consumption can be achieved. Since the transistor Q4 is turned on and the gate electrode of the transistor Q3 is controlled to a low level voltage, the transistor Q3 is turned off without depending on the voltage level of the pseudo ground line.

On the other hand, among the activated memory cells, the pseudo ground line of the memory cell on the selected bit line is connected to the low voltage source 5, so that the transistors Q3 and Q4 in the memory cell have their source potentials changed. Becomes low (voltage E _L ). At this time, since a large gate-source voltage is applied to the conductive transistor Q4, its conductive resistance becomes small. As a result, a large current flows from the bit line to the memory cell via the transistors Q6 and Q4,
A required voltage drop is generated in the pull-up element 2. At that time, the source potential of the transistor Q3 is also controlled to a low level voltage, but since the transistor Q4 is conducting, the gate-source voltage of the transistor Q3 is close to 0V,
Maintain non-conduction.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention.
3 is a circuit block diagram of the memory cell array showing the embodiment of FIG. 4'is a high voltage source for the voltage E _H '. QH0,
QH1 is a PchMOS transistor connected between each pseudo ground line and the ground, and the number at the end thereof indicates the corresponding bit line pair. SW0 ', SW1'
Is a switch (third switch means) and is turned on only when the bit line pair is selected by the bit line pair selection signals Y0 and Y1.

Here, assuming that the threshold voltage of the transistor QH0 is _-Vthp , the voltage level of the pseudo ground line V _GND0 is "E _H '+ V" when the switch SW0' is off.
thp ”, and the voltage level when it is on is E _L.
The former voltage level is a high voltage that can hold the stored information in the memory cell. This embodiment is the same as the above-described memory cell array shown in FIG. 1 except for the method of controlling the pseudo ground line to a high level voltage, and other configurations are the same.
There is an effect of low power consumption equivalent to that of the memory cell array shown in FIG.

In the memory array shown in FIG. 1, it is necessary to switch the switches SW0, SW1 etc. at high speed in order to prevent the pseudo power supply line from being left open for a long time. In the memory cell shown,
Since the voltage is constantly applied to the pseudo power supply line by the transistors QH0, QH1 etc., the switches SW0 ', SW
It is not necessary to speed up the switching of 1 ', etc. Also,
In the memory cell of FIG. 3, switches SW0 'and SW1'
Since there is one contact, etc., the switch SW with two contacts in FIG.
Compared with 0, SW1, etc., the configuration is simplified.

[Other Embodiments] In the above, an example of reading data from a memory cell has been described, but the memory cell array of the present invention is also effective as a low power consumption technique when writing data. That is, with respect to the memory cells on the non-selected bit lines, by controlling the pseudo ground line to the intermediate level voltage, useless power consumption can be suppressed as in the case of reading.

[0027]

As described above, in the first invention,
Even if the number of multiplexed bit lines is large, there is an advantage that the power consumption during operation can be reduced. Therefore, when a bit slice structure is adopted due to design time constraints, such as a memory mounted in an ASIC, the SR
If the memory cell array of the present invention is applied to AM, there is a great effect that the design time can be shortened and the power consumption can be reduced at the same time. In addition to the same effects as the first invention, the second invention has the advantage that there is no need to speed up the switching of the third switch means particularly, and the circuit configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a memory cell array according to a first embodiment of the present invention.

2 is a circuit diagram showing a configuration of a memory cell in the memory cell array shown in FIG.

FIG. 3 is a circuit block diagram showing a configuration of a memory cell array showing a second embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a configuration of a conventional memory cell array.

5 is a circuit diagram showing a configuration of a memory cell in the memory cell array shown in FIG.

[Explanation of symbols]

1, 1 ': memory cell, 2: pull-up element (load),
3: multiplexer, 4, 4 ': high voltage source, 5: low voltage source, WL: word line, BL, * BL: bit line pair, BL
0, * BL0: bit line pair, BL1, * BL1: bit line pair, DL, * DL: data line pair, Y0, Y1: bit line selection signal, SW0, SW1, SW0 ', SW1':
Selection switch for pseudo ground line, V _GND , V _GND0 ,
V _GND1 : Pseudo ground line, Q1, Q2: Pch MOS transistor, Q3, Q4, Q3 ', Q4', Q5, Q6: Nch
MOS transistor, QH0, QH1: Pch MOS transistor, VDD: high-potential power supply, GND: ground.

Claims (2)

[Claims] 1. A memory cell comprising a flip-flop for holding 1-bit information and a first switch means for controlling activation / inactivation of the cell by a selection signal, the memory cell being provided with the selection signal. In a memory cell array configured by arranging a plurality of word lines in the direction of a word line for transmission and a bit line for transmitting input / output data, the low potential power supply nodes of a plurality of memory cells connected to the same bit line are connected to a common pseudo ground line. A low-level first voltage that is at or near the ground potential when the bit line is selected, and is higher than the first voltage when the bit line is not selected and A memory cell array provided with a second switch means for applying a second voltage capable of holding information. 2. A means for applying the second voltage to the pseudo ground line is provided, and the pseudo ground line is replaced by the first switch when the bit line is selected instead of the second switch means. 3. The memory cell array according to claim 1, further comprising a third switch means connected to the voltage of 1 and not connected when the bit line is not selected.