JPH09130643A - Data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit audio and video data or the like of the 4:2:2 profile of the MPEG 2 between nodes connected by an ATM communication line. SOLUTION: When audio video data of the 4:2:2 profile of the MPEG 2 system are sent between nodes via an ATM communication line, a frequency division value of a frequency divider circuit 400 is selected to be 1/(18×q) via an ATM communication line (q is an integer). Thus, a residual time stamp (synchronization data RTS) generated by an RTS generating circuit 164 of a master node is nearly q×25-j (j is an offset). A slave node regenerates an interface clock signal ICL synchronously with the master clock signal with less jitter and it is used for processing audio and video data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system for transmitting audio / video data or the like via an ATM communication line or the like.

[0002]

2. Description of the Related Art In a television broadcasting station or a production house or the like (television broadcasting station) for producing a program, a reference signal (House Clock) signal The video tape recorder (VTR device), which supplies and broadcasts audio / video data (video signal) to the broadcasting device, and the broadcasting device such as the editing device, establish synchronization with each other. As the house clock signal, a video signal (black burst (Black Burs) that normally has a pedestal level in the horizontal scanning period (active video area) is used.
t)) signal is used.

In each broadcasting device, a phase-locked oscillator circuit (PLL oscillator circuit) as described below is used as a circuit for generating a synchronous clock synchronized with a house clock signal. FIG. 16 is a diagram showing a configuration of a conventional PLL oscillation circuit 8 that generates a synchronous clock signal (4f _sc ) for a composite video signal that is synchronized with a house clock signal.

As shown in FIG. 16, the conventional PLL oscillation circuit 8 includes a horizontal synchronization signal generation circuit 800 and a phase comparison circuit 8.
02, a low pass filter (LPF) 804, a voltage controlled crystal oscillation circuit (VCXO) 806, and a frequency dividing circuit (1/9
10) 808. In the PLL oscillation circuit 8, the horizontal synchronization signal generation circuit 800 detects the horizontal synchronization signal of the black burst signal supplied as the house clock signal, and outputs the detected horizontal synchronization signal to the positive input terminal of the phase comparison circuit 802. To do.

The frequency dividing circuit 808 outputs 14.3181818143MH from the voltage controlled crystal oscillation circuit 806.
The z synchronous clock signal 4f _sc is divided into a frequency of 1/910 and output to the negative input terminal of the phase comparison circuit 802. The phase comparison circuit 802 detects the phase difference between the signals input to the positive input terminal and the negative input terminal, and outputs the detected phase difference to the low-pass filter 804.

The low-pass filter 804 removes the high frequency component from the output signal of the phase comparison circuit 802, generates the control voltage signal x, and supplies it to the voltage controlled crystal oscillation circuit 806. The voltage controlled crystal oscillator circuit 806 generates the synchronous clock signal 4f _sc having a frequency according to the voltage value of the control voltage signal x. Since the horizontal synchronizing signal and the synchronizing clock signal are originally in a synchronous relationship, by using the PLL oscillating circuit 8, the synchronizing clock signal 4 perfectly synchronized with the horizontal synchronizing signal 4 can be obtained.
it is possible to reproduce the f _sc, by using the synchronous clock signal 4f _sc reproduced, it is possible to synchronize the operation between the plurality of broadcast equipment.

On the other hand, recently, an asynchronous transmission mode (AT is suitable for transmission of high-speed digital data such as audio / video data.
M: Asynchronous Transfer Mode (A) communication line (A
TM communication line) is being put to practical use. As a method of using the ATM communication line, for example, a plurality of broadcasting devices such as television broadcasting stations are connected via an ATM communication line, and the editing device of the first television broadcasting station to the second television. Remote editing has been considered in which the VTR device of a broadcasting station is controlled to send audio / video data via an ATM communication line, and editing work is performed at the first television broadcasting station.

In order to perform the above-mentioned remote editing, it is necessary to establish synchronization among broadcasting devices of a plurality of television broadcasting stations via ATM communication lines. However, A
19. TM communication line supplies each television broadcasting station
The 44 MHz line clock signal NCLK does not originally have a synchronous relationship with the horizontal synchronizing signal and the synchronizing clock signal 4f _sc, and simply by using an oscillation circuit such as the PLL oscillation circuit 8 (FIG. 16), a plurality of televisions can be used. It is not possible to establish synchronization between John's broadcast equipment.

The present invention has been made in view of the above-mentioned problems of the prior art, and a plurality of nodes (television broadcasting station) connected via a communication line for supplying a line clock signal such as an ATM communication line. It is an object of the present invention to provide a data transmission system capable of establishing an accurate synchronization relationship among the above).

Further, according to the present invention, the synchronous clock signal reproduced due to the fact that the house clock signal (synchronous clock signal) and the line clock signal are not in a synchronous relationship between the nodes connected by the ATM communication line occurs. An object of the present invention is to provide a data transmission system capable of eliminating the influence of jitter and the like and capable of transmitting high-quality audio / video data via an ATM communication line.

Further, according to the present invention, not only the NTSC system audio / video data but also the component video signal 4: 2: 2 is used between the nodes connected by the ATM communication line.
(Audio / video data of D1; SMPTE-125M),
An object of the present invention is to provide a data transmission system capable of transmitting audio / video data of 4: 2: 2 profile of MPEG2 and audio / video data of PAL system.

[0012]

In order to achieve the above object, a data transmission system according to the present invention has a master side data transmission apparatus and a slave side data transmission apparatus connected via an asynchronous transmission mode (ATM) communication system. A data transmission system for transmitting video data to and from a data transmission device, wherein the master-side data transmission device is independent of a line clock signal supplied by the ATM communication line and is synchronized with the video data. An independent clock signal generating means for generating a signal; a synchronous data generating means for generating synchronous data indicating a frequency ratio k: m (k, m is an integer) between the line clock signal and the independent clock signal; Master side transmission means for transmitting the synchronized data to the slave device via the ATM communication system,
The slave-side data transmission device receives the synchronization data transmitted from the master-side data transmission device via the ATM communication system, and a slave-side receiving unit that receives the synchronization data based on the received synchronization data. Dependent clock signal generation means for generating a dependent clock signal dependent on the independent clock signal of the data transmission device on the master side, and data generation means for generating the transmission data synchronized with the generated dependent clock signal, at least generated Slave side transmission means for transmitting the predetermined transmission data to the master side data transmission device via the ATM communication system.

Preferably, the synchronous data generating means of the data transmission device on the master side is the number m of cycles of the independent clock signal for every k cycles of the line clock signal, or m cycles of the independent clock signal. Counting means for counting the number k of cycles of the line clock signal for each time, and subtraction generating means for subtracting a constant j (j is an integer) from the counted number m of cycles or number k of cycles to generate synchronous data. Have
The slave clock signal generating means of the slave-side data transmission device adds oscillating means for generating the slave clock signal having a frequency corresponding to a control voltage and the constant j to the received synchronization data, Adder means for calculating the number k or the number m of the cycle, 1 / k frequency divider for dividing the line clock signal into a frequency of 1 / k, and the dependent clock signal into a frequency of 1 / m. 1 / m frequency dividing means, phase comparing means for phase-comparing the divided line clock signal and the dependent clock signal, and phase difference between the divided line clock signal and the dependent clock signal. And a control voltage generation means for generating the control voltage having a corresponding voltage.

Preferably, the data rate of the ATM communication line is 622.08 Mbps or 155.52 Mbps.
s, the frequency of the line clock signal supplied by the ATM communication line is 19.44 MHz, and the video data is a component video signal 4: 2:
2 (D1 video signal; SMPTE-125M) or M
A PEG2 4: 2: 2 profile video signal, wherein the independent clock signal and the dependent clock signal are a D1 video signal having a frequency of 27.0 MHz or an MP.
EG2 is an interface clock signal of a 4: 2: 2 profile video signal, and the frequency ratio is m: k.
Is substantially 25:18.

Preferably, the data rate of the ATM communication line is 622.08 Mbps or 155.52 Mbps.
s, the frequency of the line clock signal supplied by the ATM communication line is 19.44 MHz, and the independent clock signal and the dependent clock signal are SD in the PAL system with a frequency of 17.734475 MHz.
An I-system (SMPTE-259M) interface clock signal, wherein the frequency ratio m: k is substantially 1175: 1288,3577: 3921,475.
It is characterized by being any of 2: 5209.

The data transmission system according to the present invention is, for example, an AAL having a transmission data rate of 155.52 Mbps.
Audio / video data (video data) is transmitted between broadcasting devices in a plurality of television broadcasting stations that are mutually connected via an ATM communication system (ATM communication line) of one protocol. The data transmission device on the master side is, for example, an editing device and a VTR device, and is a line clock signal NCLK supplied from an ATM communication line or a house clock (synchronous clock signal 4f _sc ) of another television broadcasting station.
It operates in synchronization with a synchronous clock signal independent from

In the data transmission device on the master side, the independent clock signal generating means is independent of the line clock signal or the like supplied by the ATM communication line, and is independent of the editing device and VTR.
A synchronization clock signal 4f _sc (independent clock signal) that is synchronized with the video data processed by the device or the like is generated.

In the synchronous data generating means, for example, the data transmission device (editing device or the like) on the master side is configured so that the component video signal 4: 2: 2 (D1 video signal; SMPTE).
-125M) or MPEG2 4: 2: 2 profile video signal and using an interface clock signal having a frequency of 27.0 MHz as an independent clock signal, the line clock signal NCLK supplied from the ATM communication line, 18 cycles Each independent clock signal period (around 25) is counted, and based on this count value, synchronization data (residual time stamp; RTS (Residual Time)
Stump)).

Further, for example, in the synchronous data generating means, the data transmission device on the master side handles a PAL system video signal and has a frequency of 17.734475 as an independent clock signal.
SDI method for PAL of MHz (SMPTE-259
When the interface clock signal of M) is used, the line clock signal NCLK, 1288 cycles (397
1 cycle, 5209 cycles) or a cycle of an integral multiple thereof (1175, 3577,
(Around 4752) is counted, and the synchronization data RTS is generated based on this count value. The master side transmission means multiplexes the generated synchronization data RTS into a predetermined transmission packet,
It is transmitted to the transmission device on the slave side via the ATM communication line.

The data transmission device (VTR device, etc.) on the slave side uses the house clock signal (synchronization data 4) on the master side.
f _sc ). The slave side receiving means is A
The synchronous data RTS transmitted from the data transmission device on the master side is received via the TM communication line.

The dependent clock signal uses the received synchronous data RTS and the line clock signal 4f _sc to generate a dependent clock signal that is dependent on the independent clock signal of the data transmission device on the master side.

The data generating means generates transmission data in synchronization with the generated dependent clock signal, that is, in synchronization with the independent clock signal (house clock signal) of the master side data transmission device. The slave side transmission means transmits the generated video data to the slave side data transmission device via the ATM communication line.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Hereinafter, a first embodiment of the present invention will be described. FIG. 1 is a diagram showing a configuration of a data transmission system 1 according to the present invention. As shown in FIG. 1, in the data transmission system 1, the data transmission devices 3a to 3f to which the VTR devices 14a to 14f are respectively connected are connected via an ATM communication line 2 which provides a transmission line of the AAL1 protocol to them. It is configured by being connected to each other. The data transmission devices 3a to 3f mutually transmit predetermined transmission data, for example, audio / video data for programs or relays via the ATM communication line 2.

Note that 155.52 MHz supplied from the ATM communication line 2 to the data transmission devices 3a to 3f, respectively.
Frequency of the line clock signal NCLK used for processing the ATM cell as 8-bit parallel data is 19.44 MH.
z (155.52 / 8). On the other hand, the synchronous clock signal 4f _sc used in the data transmission devices 3a to 3f when transmitting by the SDI system is about 14.3 MHz.

If these frequencies are accurate, the ratio of the frequencies of these clocks (NCLK: 4f _sc ) is 118.
8: 874.9999995, which is expressed as an integer ratio,
For example, 1188: 875 or 1188: 874 (if optimized), or 1235: 910 or 1.
236: 910 (when compared in line units).
The transmission data rate of the ATM communication line 2 is 622.
When the line clock signal NCLK 'of 08 Mbps and 622.08 MHz is supplied to the data transmission devices 3a to 3f, the line clock signal NCLK' is set to 1/32.
By dividing the frequency, a line clock signal NCLK of 19.44 MHz can be obtained.

The VTRs 14a to 14f are synchronized with the synchronous clock signal 4f _sc and are audio / video data of D2 standard, component video signal 4: 2: 2 signal (audio / video data of D1 standard (video signal)), MPEG2. 4:
2: 2 profile audio / video data, or P
Data transmission devices 3a to 3f in 143 Mbps serial format by recording / reproducing AL (Phase Alternation by Line) digital audio / video data and using SDDI method (hereinafter simply referred to as SDI method), which is an improved SDI method and SDDI method. Output to.

When the VTRs 14a to 14f record / reproduce audio / video data of D1 standard or audio / video data of MPEG2 4: 2: 2 profile, the interface conditions for these audio / video data are used. , The audio / video data is transmitted in synchronization with the 27.0 MHz interface clock signal.
May be output to ~ 3f. Hereinafter, in the first embodiment, the data transmission devices 3a to 3f mainly handle audio / video data of the D2 standard, and use the SDI method for VT.
An example of transmitting audio / video data between R14a to 14f will be described.

FIG. 2 shows the data transmission device 3a shown in FIG.
3 f are transmission packets (SSCU-PDU packets, hereinafter referred to as “PDU”, which are mutually transmitted via the ATM communication line 2.
FIG. 3 is a diagram showing a configuration of “packet”). In addition,
The number attached to the left of the PDU packet indicates the byte length of each data, and the table attached to the right of the PDU packet indicates the content of each corresponding data.

In the PDU packet, the data TRS has FFh, 00h, and 00h as contents, and indicates the head position of the PDU packet. The data TRS, ancillary data (ANC; ANCillary) area and video data (VID)
It is prohibited that the data included in the PDU packet takes a value of 00h or FFh except for data inserted every 5 bytes in the (EO) area.

For the data RTS1 and RTS2, the line clock signal NCLK is 1188 cycles or 12 lines, respectively.
Synchronous clock signal 4f _sc for every 35 cycles
Offset value j (for example, j = 832, 11
Synchronous data RTS having a 6-bit value obtained by subtracting (in the case of 88 cycles) is inserted.

However, the transmission packet is the synchronous clock signal 4
Since f _sc is transmitted in a time corresponding to 910 cycles, two count values may appear during the transmission of one transmission packet when the data RTS is generated every 1188 cycles of the line clock signal. is there. Data RTS1, RTS
The reason why two areas 2 are secured is to cope with such a case.

Further, the data RTS1 and RTS2 have a synchronous clock signal 4f _sc , 875 cycles or 9 cycles, respectively.
A value obtained by subtracting the offset value j from the count value of the line clock signal NCLK for 10 cycles, that is, the synchronization data RTS based on the synchronization clock signal may be entered. Also,
As the offset value j, the synchronization data RTS is set to 0 as much as possible.
By choosing a value close to, the transmission efficiency is improved.

The data RTS1 and RTS2 are data transmission devices 3 on the receiving side (in the case where one of the data transmission devices 3a to 3f is not specified, the data transmission device 3 will be referred to as the data transmission device 3 hereinafter).
Etc.) is used to establish network synchronization. A valid bit V (Varid) is entered in the sixth bit of the data RTS1 and RTS2, and the content of the valid bit V is, for example, a logical value 1 when these data are valid and when they are not valid. Has a logical value of 0. Further, in order to prevent the data value from becoming 00h and FFh, the logically inverted value of the valid bit V is added as the seventh bit.

The data LNID (Line Number ID) is used to identify the audio / video data of the transmission data included in the ancillary data area and the video data area in the same PDU packet, and the 0th to 2nd bits. Indicates a field number (FN; Field Number) indicating a field including audio / video data, and third to seventh bits having a value of 0 to 31 indicate a line number (LN) indicating a line including audio / video data. ; Line Number).

The data LN1 takes a value in the range of 1 to 525 and is used together with the data LNID1 for identifying the audio / video data within the range of 2 fields. The 1st byte and the 2nd byte of the data LN1 have the 0th to 4th bits and the 5th bit of the numerical value, respectively.
9th bit is entered, and the 5th bit of each contains the logically inverted value of the 4th bit for the same reason as the valid bit V of the data RTS1 and RTS2.

The data LNID2 and LN2 are, for example, when the time at which the transmission data transmitted by the data transmission device 3 on the receiving side is processed is determined, for example, the received transmission data is converted into a program being broadcast in real time. When used, the data transmission device 3 on the transmission side is used when compensating for a transmission delay time occurring in transmission data (transmission packet) in the ATM communication line 2 or the like.

That is, as for the data LNID2 and LN2, the VTR device 14 has a number of lines for the audio / video data included in the same PDU packet to compensate for the transmission delay time in the television broadcasting station on the transmission side. It shows whether or not the transmission data is reproduced early and the data transmission device 3 has transmitted this transmission data. The details of each of the data LNID2 and LN2 are described in the above data LNID.
1, the same as LN1.

By referring to the data LNID2 and LN2, the transmission device 3 on the receiving side can identify the shuffling method and the like from the audio / video data included in the ancillary data area and the video data area.
That is, of the audio / video data, a shuffling block (every 23 lines, etc.) of a video data portion is discriminated from the data LNID2 and LN2, and deshuffling is performed for each shuffling block.

The data Flag has packet table (PT) data indicating the data amount of the ancillary data portion and the video data portion in the 0th to 3rd bits. The fourth to seventh bits include bits sb0 to sb3. These bits sb0 to sb3 are used to convey the shuffling method on the encoder side.

Data RS422-ch1, RS422-
The ch2 is used, for example, for transmission of control data or the like using the RS422 between computers (not shown) respectively connected to the data transmission devices 3 on the transmission side and the reception side. Data RS422-ch1, RS422-ch
In the 0th to 3rd bits of 2, either the upper 4 bits or the lower 4 bits of the data to be transmitted are entered,
The fourth bit contains a bit UL (Upper / Lower) that becomes 1 when the data contained in the 0th to 3rd bits is the upper 4 bits and becomes 0 when the data is the lower 4 bits. For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is entered in the fifth bit. Further, in the 6th bit, the data RS422-ch
1, a valid bit V indicating whether or not RS422-ch2 is valid is added.

The data VOICE contains voice data used for communication and the like. For example, the audio data can be sampled at a sampling frequency substantially equal to the sampling frequency of a PCM encoding device used for general telephone communication, and the horizontal synchronization signal ( 15.75K
Hz) 8 bits are generated, one for every two cycles. Therefore, one audio data is 1 for each cycle of the horizontal sync signal.
It will be transmitted over two generated PDU packets. In the case shown in FIG. 2, the high-order 4 bits or low-order 4 bits of the audio data are put in the 0th to 3rd bits of the data VOICE.

Further, the data RS42 is contained in the fourth bit.
Similarly to 2-ch1 and RS422-ch2, the 0th to 3rd
A bit UL indicating whether the bit data is the upper 4 bits or the lower 4 bits is inserted, and the fifth bit is
For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is inserted, and further, the valid bit V indicating whether or not the audio data is valid is added.

Further, in the sixth and seventh bits, bits 8F1 and 8F2 (8F is used for measuring the delay time given to the PDU packet by the internal circuit of the data transmission device 3 and the ATM communication line 2 are (Abbreviation of 8 Frame) is entered. The data put in the data LNID2 and LN2 is calculated based on the delay time measured using these bits 8F1 and 8F2.

The spare data is an area reserved as a spare in case another use occurs.
Similarly to 1 and RTS2, the logic inversion value of the 6th bit is put in the 7th bit so that the value is neither 00h nor FFh. Data CRCC1, CRCC2, C
The error correction code of the preceding data area is put in each RCC3. Similar to the data RTS1 and RTS2, the logic inversion value of the sixth bit is put in the seventh bit so that the value is neither 00h nor FFh.

The word length of the ancillary data area is, for example, 69 words, and the word width is converted by the word width conversion unit 410 of the word width conversion circuit 44 described above.
S / EBU data is entered. For example, the word width conversion circuit 44 converts 55 words of AES / EBU data into 8
When converted to bits, the 8-bit parallel data obtained as a result of the conversion is 68 words and 6 bits.

In such a case, in order to prevent the prohibition code (00h, FFh) from being generated, the 2-bit value 01 or 10 is put in the remaining 2 bits. The entered 01 or 10 is discarded when the PDU packet is reproduced in the data transmission device 3 on the receiving side. In this area, the AES / EBU data is in the order of the lower word in front of the PDU packet and the upper word in back.

In the video data area, from the word width of 1 word 10 bits conforming to the SDI system, of the image data of 1 word 8 bits conforming to the ATM communication line 2, the data mainly relating to the video is the D2 standard, Alternatively, the above-mentioned D
It is put in line units of video data of one standard or the like. The video data is in the order of the lower byte in front of the PDU packet and the upper byte in the rear.

The ancillary data area and video data area of the PDU packet have variable lengths, and these areas may not include valid data. In addition, the data RS422-ch1, VOICE, etc., are valid bits V
Therefore, for example, when only the valid data V of the data VIOCE is 1 and the valid data V of the other data is 0, only the data VOICE is valid and all the other data are invalid. means.

Hereinafter, the transmission data multiplexed in the ancillary data area and the video data area of the PDU packet and the D input or output to the audio / video processing device 14 will be described.
The relationship between the two types of audio / video data will be described. FIG.
[Fig. 6] is a diagram for explaining the structure of D2 audio / video data. The data amount of the header data of the D2 system corresponding to the system of 525 lines and 29.97 frames / sec is 16 words × 8 bits for each horizontal synchronization period (1 line), so the data rate is as shown in the following formula. 2 Mbps
Becomes

[0050]

## EQU1 ## 16 × 8 bits × 525 lines × 29.97 frames = 2 Mbps (1)

In a system of 525 lines and 28.97 frames / second, the number of pixels included in one line is 910, and the data per pixel is 10 bits. Therefore, the data rate is as shown in the following equation. To 143 Mbp
s.

[0052]

## EQU00002 ## 910 pixels.times.10 bits.times.525 lines.times.29.97 frames = 143 Mbps (2)

However, as shown in FIG. 3, there is an unnecessary portion in the audio / video data of the D2 system, and the ancillary data (audio data), the video data (video data) and the header data shown by diagonal lines in FIG. Only is needed for audio and video playback on the receiving side. FIG.
The data rates of the ancillary data, the video data, and the header data shown in (1) are as follows.

[0054]

## EQU00003 ## Data amount per second of ancillary data part a 21.times.10 bits.times.12 lines.times.29.97 frames.times.2 = 0.15 Mbps (3)

[0055]

## EQU00004 ## Data amount per second of ancillary data part b 376 × 10 bits × 6 lines × 29.97 frames × 2 = 1.3 Mbps (4)

[0056]

## EQU00005 ## Data amount per second of ancillary data part c 55.times.10 bits.times.254 lines.times.29.97 frames.times.2 = 8.4 Mbps (5)

[0057]

## EQU00006 ## Data amount per second of video data part d 768 × 8 bits × (254 + 253) lines × 29.97 frames = 93.3 Mbps (6)

[0058]

[Equation 7] 1 of video data section and ancillary data section
Total data amount per second e a + b + c + d = 0.15 + 1.3 + 8.4 + 93.3 = 103.2 Mbps (7)

Further, when header data is added, the data rate of the ancillary data, video data and header data becomes 105.2 Mbps as shown in the following equation.

[0060]

2 + 103.2 = 105.2 Mbps (8)

As described above, in the ancillary area of the PDU packet and the video data, 105.2 Mbps of the D2 audio / video data (total of 143 Mbps) is removed line by line, excluding unnecessary portions. To be done. Thus, the amount of transmission data is reduced because the unnecessary portion is removed, and as a result, the audio / video data (transmission data) of the D2 system can be adapted to the AAL1 protocol.

In the ancillary area and video data area of the PDU packet shown in FIG. 2, the audio / video data of the D2 standard shown in FIG.
The data (105.2 Mbps in the case of the D2 standard) from which unnecessary parts have been removed from Mbps) is multiplexed and transmitted.

Since the audio / video data of the D2 standard shown in FIG. 3 has a periodicity, it can be multiplexed in a PDU packet by a constant processing method line by line on both the transmitting side and the receiving side. it can. Therefore, the hardware configuration is simple. By multiplexing the transmission data with other data such as RTS data in the PDU packet described above and transmitting the data, not only the transmission data is transmitted, but also useful for processing the transmission data on the receiving side. Data can also be transmitted. In addition to the first embodiment, the data transmission system 1 according to the present invention
Can have various configurations such as increasing or decreasing the number of data transmission devices 3a to 3f, or further increasing the types of data to be multiplexed in the PDU packet.

Second Embodiment Hereinafter, as a second embodiment of the present invention, a configuration of the data transmission devices 3a and 3b and a data transmission method between them will be described. In the second embodiment, for simplification of description, the data transmission devices 3a and 3b are NTSC.
The case where the audio / video data of the D2 standard of the method is transmitted to and from the VTRs 14a to 14f by the SDI method will be described. However, the data transmission devices 3a to 3f use the audio / video data of other than the D2 standard (D1 standard, MPEG2, PAL, etc.). The operation when handling video data is similar, and the configuration of the data transmission devices 3c to 3f other than the data transmission devices 3a and 3b and the data transmission method between the data transmission devices 3c to 3f are the same (hereinafter the same).

FIG. 4 shows the data transmission device 3a shown in FIG.
FIG. 3 is a diagram showing an example of the configuration of FIG. FIG. 5 is a diagram showing a configuration example of the data transmission device 3b shown in FIG. 4 and 5
, The data transmission devices 3a and 3b are
It is composed of a transmitter 5, a receiver 6, an ATM adapter 7 and audio / video processing devices 14a and 14b.

The audio / video processing device 14a connected to the data transmission device 3a is a VTR device 140, a D2 type V device.
TR monitor device 142, editing device (editor) 144
And an editor monitor device 146. Audio / video processing device 14 connected to the data transmission device 3b
b is, for example, a D2 type VTR device (hereinafter, the audio / video processing device 14b is referred to as a VTR device 14b).
The ATM adapter 7 is, for example, an adapter for the AAL1 protocol of the ATM system, and includes the data transmission devices 3a and 3a.
The PDU packet (FIG. 2) input from the transmitter 5 of b is transmitted to the ATM communication line 2 in the payload part of the ATM cell, and the PDU packet is received from the payload part of the ATM cell received from the ATM communication line 2. It separates and outputs to the receiving part 6 of the data transmission devices 3a and 3b.

On the data transmission device 3a side, the VTR device 140 and the editing device 144 are connected to the data transmission device 3b.
The control data RS422 for operating the VTR device 14b connected to is generated, and the audio / video data is recorded and edited, respectively. The control data RS422 generated by the VTR device 140 or the like is the PDU packet data RS422-ch1 and RS422-ch shown in FIG.
2 is multiplexed. Further, as shown in FIG. 4, the control data RS422 generated by the VTR device 140 is also input to the editing device 144 and used for predetermined control.

In addition, from the VTR device 140 to the editing device 14
The control data RS422 input to 4 is the reproduction of the VTR, the recording from a certain time, the fast-forward and the selection of the synchronization source (whether it is synchronized with the input audio / video signal or the house clock). Used for etc. The VTR monitor device 142 and the editor monitor device 146 respectively display the audio / video data reproduced by the VTR device 140.

FIG. 6 is a diagram showing the configuration of the transmitting unit 5 shown in FIG. As shown in FIG. 6, the transmission unit 5 includes a clock generation device 12, an RTS generation device 16, and a transmission device (TX).
18 and a delay processing circuit 22. The clock generator 12 uses, for example, a crystal oscillator or the like to transmit the transmitter 5
To generate a sync clock signal 4f _{sc of} 14.3 MHz and a sync signal SYNC corresponding to a horizontal sync signal, a vertical sync signal, etc.
The S generator 16 and the transmitter 18 are supplied.

The VTR 14 records / reproduces digital audio / video data of D2 standard in synchronization with the synchronous clock signal 4f _sc , and transmits it in a 143 Mbps serial format by the SDI system or SDDI system (hereinafter simply referred to as SDI system). Output to 18. Delay processing circuit 22
Performs delay time measurement processing based on the bits 8F1 and 8F2 input from the receiving unit 6.

FIG. 7 is a diagram showing the configuration of the RTS generator 16 shown in FIG. 6 in the second embodiment. RTS
The generator 16 includes a 1/8 frequency divider circuit 160, a counter circuit 162, an RTS generation circuit 164, and a 1/910 frequency divider circuit 166. With these components, the RTS generator 16 synchronizes with the frequency of the 19.44 MHz line clock signal NCLK (actually, 155.52 MHz line clock signal NCLK 'as described later) supplied from the ATM communication line 2. Clock signal 4f _sc
Shows the actual integer ratio of the frequency of the synchronization data RTS (Residual T) used for establishing synchronization with the transmission units 5 and 30.
ime Stamp) is generated line by line with the synchronous clock signal 4f _sc as a reference.

The frequency dividing circuit 160 receives the line clock signal NC of 155.52 MHz supplied from the ATM communication line 2.
LK 'is divided into a frequency of 1/8, and the counter circuit 16
2 and to each component of the data transmission device 3a shown in FIG. As mentioned above, in practice, ATM
From the communication line 2 to the data transmission devices 3a to 3f 155.
52 MHz line clock signal NCLK 'is supplied,
The frequency is divided into 1/8 inside the data transmission devices 3a to 3f, and 1
It is supplied to each component as a line clock signal NCLK of 9.44 MHz.

In this way, the line clock signal NCLK '
(155.52 MHz) is divided by 1/8 to give 19.44.
By supplying as the line clock signal NCLK of MHz to each component of the data transmission devices 3a to 3f,
The operation timings of the respective constituent parts of the data transmission devices 3a to 3f are relaxed, and standard and inexpensive parts such as general-purpose CMOS logic ICs can be used instead of special parts operating at high speed.

The frequency dividing circuit 166 uses the synchronous clock signal 4f.
_sc is divided into 1/910 frequencies to generate a horizontal sync signal S166 indicating one horizontal sync period of audio / video data,
It outputs to the counter circuit 162 and the RTS generation circuit 164. The counter circuit 162 counts the number of periods of the horizontal synchronizing signal supplied from the frequency dividing circuit 166 and one cycle of the line clock signal NCLK, and counts the count value S162 as R.
It is output to the TS generation circuit 164. The RTS generation circuit 164 uses a predetermined offset value j from the count value S162,
That is, the numerical value j of which the result of subtraction from the count value S162 is 6 bits is subtracted, and the synchronization data RT
S is generated and output to the transmission device 18.

FIG. 8 is a diagram showing the structure of the transmission device 18 shown in FIG. As shown in FIG. 8, the transmitter 18
The first block 180 and the line clock signal NCLK which are connected to the ATM communication line 2 according to the AAL1 protocol and operate in synchronization with the synchronous clock signal 4f _sc
And a second block 210 that operates in synchronization with.

The first block 180 includes a serial / parallel conversion circuit (S / P circuit) 182, a first switch circuit (SW1) 184, and a second switch circuit (SW2) 1.
86, rounding circuit 188, shuffling circuit 1
90, a first FIFO circuit 192, a word width conversion circuit (10 → 8) 194, a second FIFO circuit 196, a timing generation circuit a200, a timing generation circuit b20.
2, control circuit 204 and reference signal generation circuit 2
It is composed of 06. The second block 210 includes a multiplexing circuit (MUX) 212, a third FIFO circuit 214, a control circuit 216, and a timing generation circuit c21.
8.

In the first block 180, the timing generating circuit a200 is used for the other data transmission devices 3a to 3f.
The video data (black burst data) corresponding to the black burst is generated at the operation timing based on the data RTS having the value (default) when the data is not transmitted. The reference signal generation circuit 206 is a circuit outside the first block 180, generates black burst data similarly to the timing generation circuit a200, and outputs it to the terminal a of the switch circuit 184.

The S / P circuit 182 converts the 1-bit serial format SDI transmission data input from the audio / video processing device 14 into a 10-bit parallel format and outputs it to the terminal b of the switch circuit 184. To do. The switch circuit 184 selects the terminal b side to output the output data of the S / P circuit 182 when the transmitter 5 transmits data, and selects the terminal a side otherwise to select the reference signal generation circuit. The black burst data output from 206 is output to the switch circuit 186.

The switch circuit 186 is the switch circuit 18
4 selects the video data portion of the output data (transmission data) of the S / P circuit 182 selected from the S / P circuit 182 of the audio / video data of the D2 system shown in FIG.
It outputs to 88, selects an ancillary data part, and outputs to the word width conversion circuit 194. The rounding circuit 188 converts the data (video data) corresponding to the video data portion shown in FIG. 3 into 8-bit parallel format data (rounds) and sends the data to the shuffling circuit 190. Output. The control circuit 204 handles the header data shown in FIG.

The shuffling circuit 190 receives the 8-bit parallel signal input from the rounding circuit 188,
When a data error occurs in the ATM communication line 2, the data is rearranged in an order that facilitates interpolation and is output to the FIFO circuit 192. The word width conversion circuit 194 converts the data (voice data) corresponding to the ancillary data portion input from the switch circuit 186 shown in FIG. 3 into an 8-bit parallel format, and outputs it to the FIFO circuit 196.

The FIFO circuits 192 and 194 read data in synchronization with the synchronous clock signal 4f _sc ,
Data is sequentially output in synchronization with the line clock signal 4f _sc , and the data is transferred from the first block 180 to the second block 210. Control circuits 204 and 216
Monitors the addresses to which data is written and the addresses to be read in the FIFO circuits 192 and 194, respectively, and controls these addresses. Further, the first block 180 generates the data LN1, LNID1, LN2, LNID2 and the data Flag (FIG. 2) based on the bits 8F1, 8F2, etc., and outputs them to the second block 210.

In the second block 210, the timing generation circuit c218 controls the operation timing of the block 210 based on the line clock signal NCLK.
The data RTS is input from the inspection signal applying circuit 16 and the data LN1, LNID1, LN2, LNID2, and Flag are input from the first block 180 to the multiplexing circuit 212. Further, the multiplexing circuit 212 includes a VTR device 140 and an editing device 14 on the data transmission device 3a side.
4 from the VTR device 1 on the data transmission device 3b side.
Control data RS422 is input from 4b. This control data RS422 is used to control the VTR device.

The multiplexing circuit 212 receives these data, F
Audio data and video data input from the IFO circuits 192 and 194, and control data RS422 (RS
422-ch1, RS422-ch2) are multiplexed.
The data after these data are multiplexed is output to the CRCC addition circuit 213.

The CRCC addition circuit 213 is used for each data CR.
The CC is calculated, added, and output to the FIFO circuit 214. The FIFO circuit 214 buffers the output data of the multiplexing circuit 212 and outputs it as transmission data TXD to the ATM communication line 2. As shown in the figure, bits 8F1 and 8F2 from the delay processing circuit 22 are further added to the output data of the FIFO circuit 214 to form the transmission data TXD.

FIG. 9 is a diagram showing the structure of the receiving unit 6 shown in FIG. As shown in FIG. 9, the reception unit 6 includes a reception device (RX) 32, a VTR 34, a clock control device 36, and a clock generation device 38, and receives a PDU packet transmitted from the data transmission device 3 on the transmission side. And synchronous data RTS and line clock signal NCLK
On the basis of the above, the synchronous clock signal 4f _sc synchronized with the synchronous clock signal 4f _sc of the data transmission device 3 on the transmitting side is reproduced, and the audio / video data is separated from the PDU packet and recorded.

FIG. 10 is a diagram showing the structure of the receiving device 32 shown in FIG. As shown in FIG.
Is connected to the ATM communication line 2 according to the AAL1 protocol and operates in synchronization with the line clock signal NCLK.
It is composed of a second block 350 that operates in synchronization with f _sc . The receiving device 32 separates each data and audio / video data from the PDU packet received from the ATM communication line 2, and outputs the transmission data of the separated data as reception data RVD to the audio / video processing device 14. , Bits 8F1 and 8F2 are output to the delay processing circuit 22.

The first block 320 includes an input data control circuit 322, a first register circuit 324, a CRCC calculation circuit 326, adder circuits 328a and 328b, a first memory circuit 330, a second memory circuit 332 and a second block. Register circuit 334, third register circuit 336, control circuit 338, and timing generating circuit d340.

The second block 350 includes an output data control circuit 352, a fourth register 354, a first reference signal generation circuit 356, a deshuffling circuit 358, a concealment circuit 360, a first error correction circuit 362 and a FIFO circuit 364. , A second error correction circuit 366, a switch circuit 368, a timing generation circuit e370, a second reference signal generation circuit 372, a switch circuit 374, a parallel / serial conversion circuit (P / S circuit) 376, and a control circuit 378. It

PDU stored in the payload part of the ATM cell received by the receiving device 32 from the ATM communication line 2.
The packet is input to the input data control circuit 322, the first register circuit 324 and the CRCC calculation circuit 326. The first register circuit 324 converts the received 8-bit parallel format PDU packet into a 64-bit parallel format. The CRCC calculation circuit 326 performs a calculation process related to each data CRCC (FIG. 2) included in the PDU packet, and outputs the calculation result to the addition circuit 328a. The CRCC calculation circuit 326 determines that the transmission data X ⁿ
+ X ^n-1 + X ^n-2 + ... + X + 1, G (X) = X ¹⁴ + X
Divide by ² + X + 1. If this remainder is other than 0, an error is detected, and the calculation result is set to the logical value 1 and output.

The input data control circuit 322 determines, based on each data included in the input PDU packet, write flag data (a; 8-bit parallel data in which all bits are logical values 0, and each bit is a PDU packet). (Corresponding to 1 byte of) is generated and output to the addition circuit 328b. The adder circuit 328b is the first register circuit 3
Write flag data is added to the output data of 24
Output in bit width.

Further, the input data control circuit 322 generates read flag data (b) having a 9-bit × 8-word structure. After reading the read flag data, the input data control circuit 322 sets only the parity bit to the logical value 1 and all the other bits to the logical value 0, and sets the number of lines (525) ×
The PDU packet is written into the memory circuit 332 having an address space of packet length × 9 bits. The reason why the input data control circuit 322 performs the bit operation of the read flag data in this way is to judge that the necessary data has not arrived when the read flag data of the read data has the logical value 1. Note that the read flag data has a logical value of 0 if it has been written before reading.

The register circuit 334 collects 8 pieces of total 9-bit data of 8 bits of received data and 1 bit of flag data corresponding to the received data as 72-bit data and synchronizes with the line clock signal NCLK from the memory circuit 332. Read out and output to the register 354 in synchronization with the synchronous clock signal 4f _sc .

The input data control circuit 322 also outputs write flag data to the adder circuit 328a (c).
The adder circuit 328 a adds write flag data to the calculation result of the CRCC calculation circuit 326 and returns it to the input data control circuit 322. The input data control circuit 322 outputs the calculation result with the write flag data added to the memory circuit 330.
(D).

The register circuit 336 is the memory circuit 332.
The addition result of the adder circuit 328a stored in is read out in synchronization with the line clock signal NCLK and output in synchronization with the synchronous clock signal 4f _sc . Control circuit 3
38 and 378 are control circuits 20 of the transmitter 18.
4, 216 (FIG. 7), register circuits 334, 3
It manages 36 write and read addresses.

In the second block 350, the timing generation circuit e370 controls the operation timing of each part of the second block 350 based on the synchronous clock signal 4f _sc . The reference signal generation circuit 372 generates and outputs a reference signal. The reference signal generation circuit 356 generates a reference signal and outputs it to the terminal a of the switch circuit 374. The reference signal generated by the reference signal generation circuits 372 and 356 is a signal that does not contain video data and ancillary data and that makes the screen black after reproduction.

The data output from the register circuit 334 is input to the register 354. On the other hand, the data output from the register circuit 336 is the output data control circuit 35.
2 is input. The register circuit 354 transfers each word of the data corresponding to the ancillary data section shown in FIG. 3 (voice data multiplexed in the ancillary area shown in FIG. 2) to the lower 2 bits and its parity bit (a), It is decomposed into the upper 8 bits (b) and its parity bit and output to the input data control circuit 322.

The output data control circuit 352 sends to the deshuffling circuit 358 data corresponding to the video data section shown in FIG. 3 (video data multiplexed in the video data area shown in FIG. 2) and its parity. The error correction circuit 36 outputs (c) the data corresponding to the ancillary data section shown in FIG. 3 (voice data multiplexed in the ancillary data area shown in FIG. 2) and its parity.
2 is output (d) to the data RS42 shown in FIG.
2-ch1, RS422-ch2, VOICE, RTS
Error correction circuit 36
It outputs to 6 (e). That is, the output data control circuit 352 also serves as a separation circuit that separates the audio data and the video data from the PDU packet and the data RS422-ch1 and the like.

By this processing, the output data control circuit 352 a: 8-bit data (1) + flag data (2), b; 2-bit (3) + flag data (4), output of register 2 = CRCC 1 bit Of each data of the + flag data (6), (2), (4), (5),
When any one of (6) has a logical value of 1, a logical value of 1 is newly output as flag data. That is, the output data control circuit 352 performs conversion with a flag of 2 words width of a; (reception data 8 bits + flag data 1 bit) into (ancillary data 10 bits + flag data 1 bit).

The deshuffling circuit 358 performs a process corresponding to the shuffling circuit 190 shown in FIG. 8 based on the data LNID2 and LN2 included in the input data, restores the original order, and sends it to the conceal circuit 360. Output. The concealment circuit 360 interpolates the data of the pixel in which the data error has occurred, for example, by the interpolation of the surrounding pixels, and the switch circuit 374.
It is output to the terminal b.

The error correction circuit 362, which has been input, performs error correction on the input audio data, and outputs it to the FIFO circuit 364. The FIFO circuit 364 outputs the video data output from the concealment circuit 360 and the error correction circuit 362 output from the error correction circuit 362 to the terminal c of the switch circuit 374 at the same timing.

The switch circuits 374 are connected to terminals a ...
The reference signal from the reference signal generation circuit 356, the output data of the concealment circuit 360, and the FIFO
One of the output signals of the circuit 364 is selected in an order suitable for the audio / video data of the D2 system in the SDI system, and is output to the P / S circuit 376. P / S circuit 3
Reference numeral 76 converts the data input from the switch circuit 374 into serial format data, and outputs the synchronous clock signal 4f _sc.
And output to the VTR device 14.

The error correction circuit 366 performs error correction on the input data RS422-ch1 etc. and outputs it to the switch circuit 368. The switch circuit 368 outputs the data whose error has been corrected to the data RS422-ch1, RS422-ch2 and VOIC, respectively.
Separate into E, RTS and preliminary data.

In the data transmission device 3a, the data RS422-ch1 and RS422-ch2 are VT.
It is output to the R device 140 and the editing device 144 (FIG. 4; RS422). In addition, in the data transmission device 3b, the data RS422-ch1, RS422-ch
2 is output to the VTR device 14b (FIG. 5; R
S422).

Audio / video processing device 14 (FIGS. 4 and 5)
Records the audio / video data RVD input from the P / S conversion circuit 330 in synchronization with the synchronous clock signal 4f _sc . The clock generator 38 is, for example, a voltage controlled oscillator circuit having a crystal oscillator circuit, and has a clock control signal C.
The synchronous clock signal 4f _sc having a frequency according to the control of the clock control device 36 via C is generated and supplied to each component of the transmission device 30.

FIG. 11 shows the synchronous data RT in the configuration of the clock controller 36 shown in FIG. 9 in the second embodiment.
It is a figure which shows the part which concerns on the process of S. As shown in FIG. 11, the clock control device 36 includes a 1 / (RTS + j) frequency dividing circuit 382, a phase comparison circuit 384, a low-pass filter (LFP) 386, a 1/8 frequency dividing circuit 380 and 1/9.
The clock generator 3 is composed of a frequency divider circuit 388.
Together with 8, form a PLL (Phase Locked Loop) oscillator circuit.

The clock controller 36 uses these components to synchronize the synchronous data RT input from the receiver 32.
Generates a clock control signal CC on the basis of the S, by controlling the frequency of the synchronization clock signal 4f _sc generator 38 occurs, the synchronous clock signal 4f _sc of the transmission apparatus 10 of the synchronization clock signal 4f _sc of the transmission apparatus 30 Synchronize. Further, the clock control device 36 generates a sync signal SYNC corresponding to the horizontal sync signal and the vertical sync signal and supplies the sync signal SYNC to the audio / video processing device 14 and the like.

The frequency dividing circuit 380 receives the line clock signal NC of 155.52 MHz supplied from the ATM communication line 2.
LK ′ is frequency-divided to a frequency of ⅛, and the frequency-divided signal S380
(= NCLK) is output to the frequency dividing circuit 382 and other components of the data transmission device 3b. In the frequency dividing circuit 380, the line clock signal NCLK ′ of 155.52 MHz is frequency-divided by 1/8 to obtain the line clock signal N.
It is the frequency divider circuit 160 of the RTS generator 16 that generates CLK and supplies it to the other components of the data transmission device 3b.
This is for the same reason as (Fig. 7).

The frequency dividing circuit 382 outputs the frequency divided signal S380 to
1 / (RTS + j) (where RTS is the synchronous data RTS input from the receiving device 32, j is the offset value reduced in the data transmission device 3a), and the phase comparison is performed as a divided signal S382. Output to the negative input terminal of the circuit 384. In this way, the frequency dividing circuit 38
2 adds the offset value j to the synchronization data RTS,
A synchronous clock signal 4f _sc in the data transmission device 3a,
The number of cycles (1235 or 1236) of the line clock signal NCLK for every 910 clocks is calculated, and the divided signal S
Divide the 382.

The frequency dividing circuit 388 is a clock generator 38.
The frequency of the synchronous clock signal 4f _sc generated by is divided into a frequency of 1/910 and the divided signal S388 is output to the positive input terminal of the phase comparison circuit 384. The phase comparison circuit 384 is
The divided signal S388 and the divided signal S382 are compared in phase,
The comparison result S384 is output to the low pass filter 386. The low-pass filter 386 uses the comparison result S384.
To remove the high-frequency component from to generate the clock signal CC,
It outputs to the clock generator 38.

Hereinafter, referring again to FIG. 1, the case where data is transmitted between the data transmission devices 3a and 3b is taken as an example, and the audio / video processing equipment 14a and 1 shown in the second embodiment is shown.
The operation of the data transmission system 1 using 4b will be described.
First, the audio / video processing device 14 on the data transmission device 3a side
From the editing device 144, etc. of a, the V on the data transmission device 3b side is
The operation when controlling the TR 14b will be described. On the data transmission device 3a side, the audio / video processing device 14a
The VTR device 140 and the editing device 144 generate control data RS422 for operating the VTR device 14b.

The control data generated by the VTR device 140 or the like is, for example, the VTR device 14b on the data transmission device 3b side.
In addition, data that specifies audio / video data to be reproduced, data that specifies a reproduction method such as fast forward, fast rewind, and jog shuttle reproduction. Data transmission device 3a
Control data RS422 to PDU packet data R
S422ch-1 and RS422ch-2 are multiplexed with audio / video data at other positions of the PDU packet, and AT
Output to the M adapter 7. ATM adapter 7
The PDU packet is put in the payload portion of the ATM cell and transmitted to the data transmission device 3b via the ATM communication line 2.

The ATM adapter 7 is the data transmission device 3a.
The payload part of the ATM cell sent from
The data is sequentially output to the data transmission device 3b. The data transmission device 3b receives the data RS422-ch1, RS42 of the PDU packet transmitted from the data transmission device 3a.
Control data is separated from 2-ch2 and VTR device 14b
Output to

The VTR device 14b performs, for example, selection of audio / video data to be reproduced, fast-forwarding, fast-rewinding, normal reproduction, or special reproduction such as jog shuttle according to the control data, and audio / video of the D2 system. Data is generated and output to the data transmission device 3b. The data transmission device 3b multiplexes the audio / video data input from the VTR device 14b into the PDU packet shown in FIG. 2 and transmits it to the data transmission device 3a via the ATM communication line 2. Note that the VTR device 14b may be controlled to perform so-called confidence reproduction, in which the recorded audio / video data is reproduced using another head while recording.

The data transmission device 3a is the data transmission device 3a.
The audio / video data transmitted from b is output to the audio / video processing device 14a. Audio / video processing equipment 1
The editor monitor device 146 of 4a displays the audio / video data, the VTR device 140 records the audio / video data, or the editing device 144 operates the audio / video data according to the operation of an editor (not shown). To edit.

As described above, according to the data transmission system 1 of the present invention, one ATM communication line is used for V
It is possible to specify the content of the audio / video data to be reproduced by the TR device 14b and the reproduction method, and to transmit the reproduced audio / video data. Further, according to the data transmission system 1 of the present invention, since the SDI system widely used as the infrastructure in the television broadcasting station can be used as the interface of the VTR 14, the existing equipment can be used as the ATM communication line. Can be easily connected.

Next, the synchronous clock signal 4f _sc of the data transmission device 3a side, to explain an operation when a synchronizing a synchronous clock signal 4f _sc of the data transmission device 3b side. On the data transmission device 3a side, the frequency divider circuit 166 of the RTS generation device 16 (FIG. 6) outputs the sync clock signal 4f _sc at 1/91.
The frequency is divided by 0 to generate a horizontal synchronizing signal S166 corresponding to the house clock inside the data transmission device 3a.

On the other hand, the frequency dividing circuit 160 is 155.52 M
The line clock signal NCLK 'of Hz is divided by 1/8 and 1
Generate a line clock signal NCLK of 9.44 MHz. The counter circuit 162 outputs 1 of the horizontal synchronization signal S166.
For each cycle, that is, audio / video data, the number of cycles of the line clock signal NCLK in units of one line is counted, and RTS is calculated.
Output to the generation circuit 164.

The RTS generation circuit 164 is the counter circuit 1
The offset value j is subtracted from the count value S162 of 62 to generate the synchronization data RTS and output it to the transmission device 18. This synchronization data RTS is a synchronization clock signal 4f _sc
, The frequency ratio between the synchronous clock signal 4f _sc and the line clock signal NCLK is shown. The transmission device 18 is R
The synchronization data RTS input from the TS generator 16 is set to P
The other data is put in the corresponding part of the PDU packet in one of the data RTS1 and RTS2 of the DU packet and transmitted to the data transmission device 3b side via the ATM adapter 7 and the ATM communication line 2.

On the data transmission device 3b side, the reception device 32 (FIGS. 9 and 10) receives the PDU packet transmitted from the data transmission device 3a side via the ATM adapter 7, and separates the synchronization data RTS. And outputs it to the frequency dividing circuit 382 (FIG. 11) of the clock control device 36.
On the other hand, the frequency dividing circuit 380 determines that the line clock signal NCLK '
Is divided into 1/8 frequency, and the divided signal S380 (= NC
LK) is generated. The frequency dividing circuit 382 adds the offset value j to the input synchronization data RTS to calculate (RTS + j) corresponding to the count value S162 of the counter circuit 162, and further divides the frequency dividing signal S380 by 1 / (RTS +
Divide to the frequency of j).

The phase comparison circuit 384 outputs the divided signal S34.
8, the phase of S382 is compared to detect a phase error, and the low-pass filter filters the comparison result S384 to generate the clock control signal CC.
Control the frequency of the synchronous clock signal 4f _sc . As described above, the clock control device 36 controls the clock generation device 38 to synchronize with the synchronization clock signal 4f _sc on the data transmission device 3a side.

FIG. 12 shows the synchronization data RTS generated by the RTS generator 16 shown in FIG. 6 in the second embodiment.
It is a figure explaining the value of. As described above, on the data transmission device 3a side in the second embodiment, as shown in FIG.
As shown in (B), the counter circuit 162 (FIG. 7) counts the synchronous clock signal 4f _sc and the line clock signal NCLK for every 910 cycles, and this count value S162 (= RTS
+ J) generates synchronization data RTS for each horizontal synchronization period of audio / video data (house clock signal). In this case, the synchronous clock signal 4f _sc on the data transmission device 3a side
When the frequency of the line clock signal NCLK is accurate, the count value S162 of the counter circuit 162 is 12
35 and 1236 appear in almost the same number.

Therefore, in the comparison result S384 of the phase comparison circuit 384 (FIG. 11) of the clock control device 36 on the data transmission device 3b side, a pulse-like phase difference appears every horizontal synchronization period. Since the result S384 is smoothed by the low-pass filter 386 and output to the clock generator 38, it is possible to accurately synchronize the synchronous clock signal 4f _sc on the data transmission device 3b side with the data transmission device 3a side. .

The circuit configurations and the like of the transmitting unit 5 and the receiving unit 6 shown in the above embodiment are mere examples, and can be replaced with circuits or the like capable of realizing equivalent functions. Also,
V2 of D2 system as a device connected to the data transmission device 3b
Although the TR device is shown as an example, the present invention is not limited to this, and may be configured such that an editing device, a relay device, or a transmission facility for inputting and outputting data by the SDI system is connected.

The transmission data rate of the ATM communication line 2 is 622.08 Mbps, and 622.08 MHz.
The line clock signal NCLK 'of the data transmission device 3a-
When supplying to the 3f, the frequency dividing circuit 160 of the RTS generation device 16 and the frequency dividing circuit 380 of the clock control device 36.
Is replaced with a circuit that divides the line clock signal NCLK ′ into a frequency of 1/32, the ATM adapter 7 is replaced with a device for a transmission data rate of 622.08 Mbps, and, if necessary, the data transmission devices 3a to The other components of 3f may be modified.

Also, the PDU packet shown in FIG. 2 is an example, and the present invention can be applied to a transmission method using a transmission packet of another format. Further, the data transmission system 1, the transmitter 5 and the receiver 6 according to the present invention are
In addition to video data, it can be applied to any of these data, or data for information processing.

Third Embodiment Hereinafter, as a third embodiment of the present invention, with the line clock signal NCLK as a reference, the synchronous clock signal 4f _sc is counted to generate the synchronous data RTS, and the data transmission device 3a,
A case of synchronizing 3b will be described. Transmission unit 5
At the data transmission device 3a, 3 at the receiving unit 6 by using the clock control device 36.
As shown in FIG. 12, when synchronization is performed between b, the synchronization data RTS generated by the RTS generation device 16 of the data transmission device 3a changes every horizontal synchronization period (line), and affects the clock post-natal signal CC. Then, jitter occurs in the synchronous clock signal 4f _sc generated by the clock generator 38.

The frequency of the synchronous clock signal 4f _sc generated on the data transmission device 3a side and the frequency of the line clock signal NCLK (NCLK ') supplied by the ATM communication line 2 are not always accurate. The RTS generation device 40 (FIG. 13) and the clock control device 42 (FIG. 14) described in the third embodiment can solve such a problem.

FIG. 13 shows the data transmission device 3 shown in FIG.
FIG. 8 is a diagram showing a configuration of an RTS generation device 40 that is used by replacing the RTS generation device 16 shown in FIG. It should be noted that components common to the RTS generation device 40 and the RTS generation device 16 are denoted by the same reference numerals (the same applies hereinafter).

As shown in FIG. 13, the RTS generator 40
Is a frequency dividing circuit 400, a counter circuit 410 and an RTS.
It is composed of a generation circuit 164. RTS generator 40
Is the line clock signal NCLK 'of 155.52 MHz.
To a frequency of 1/8 to generate a line clock signal NCLK of 19.44 MHz, and
It is composed of a frequency dividing circuit 402 which further divides the line clock signal NCLK generated by the frequency dividing circuit 160 into a frequency of 1 / n (n = 1188).

With these components, the RTS generator 40 has the optimized frequency of the line clock signal NCLK of 19.44 MHz and the synchronous clock signal 4f _{sc in} the data transmitter 3a as described in the first embodiment. The ratio 1188: 875 or 1188: 874 is used to generate the sync data RTS.

The frequency dividing circuit 400 divides the line clock signal NCLK 'of 155.52 MHz into a frequency of 1/8, and further divides it into a frequency of 1/1188 to generate a divided signal S400. It outputs to the circuit 410 and the RTS generation circuit 164. Counter circuit 410
Counts the synchronous clock signal 4f _sc generated by the clock generator 12 (FIG. 6) for each cycle of the divided signal S400, and outputs it as the count value S410 to the RTS generation circuit 164. The RTS generation circuit 164 uses the count value S41.
An offset value j (for example, j = 832) is subtracted from 0 to generate synchronization data RTS, which is output to the transmission device 18.

FIG. 14 shows a data transmission device 3 shown in FIG.
FIG. 11 is a diagram showing a portion related to processing of synchronous data RTS in the configuration of the clock control device 42 used by being replaced with the clock control device 36 in the receiving unit 6 on the b side. As shown in FIG. 14, the clock control device 42 includes a frequency dividing circuit 430,
420, phase comparison circuit 384 and low-pass filter 3
86.

Like the frequency dividing circuit 400 of the RTS generator 40, the frequency dividing circuit 430 supplies a line clock signal NCLK ′ of 155.52 MHz supplied from the ATM communication line 2.
To a frequency of 1/8 to generate a line clock signal NCLK of 19.44 MHz, and a line clock signal NCL generated by the frequency divider circuit 380.
Frequency divider circuit 4 for further dividing K into a frequency of 1/1188
It consists of 32.

The clock generator 42 constitutes a PLL oscillation circuit together with the clock generator 38 by the above-mentioned components, like the clock controller 36.
Based on the TS, the frequency of the synchronous clock signal 4f _sc generated by the clock generator 38 on the data transmission device 3b side is controlled to synchronize with the data transmission device 3a side, and further the synchronization signal SYNC is generated.

The frequency dividing circuit 430 has a period of 19.44M.
Corresponding to 1188 cycles of line clock signal NCLK of Hz
To generate a frequency-divided signal S430 as the frequency-divided signal S430.
And outputs it to the positive input terminal of the phase comparison circuit 384.
The frequency divider circuit 420 receives the P signal received by the receiver 32 (FIG. 9).
The offset is set to the synchronous data RTS separated from the DU packet.
Value j is added to correspond to the count value S410 (RTS +
j), and the synchronization clock generated by the clock generator 38.
Lock signal 4f _scTo 1 / (RTS + j) frequency
Then, as the divided signal S420, the negative input of the phase comparison circuit 384.
Output to the input terminal.

The phase comparison circuit 384 and the low-pass filter 386 generate the clock control signal CC from the divided signals S430 and 420 in the same manner as in the RTS generation device 16 (FIG. 11), and the synchronous clock generated by the clock generation device 38. It controls the frequency of the signal 4f _sc .

[0137] Hereinafter, the operation of the RTS generator 40 and a clock control unit 42 when synchronizing a synchronous clock signal 4f _sc of the data transmission device 3b side synchronization clock signal 4f _sc of the data transmission device 3a side. On the data transmission device 3a side, the frequency dividing circuit 400 of the RTS generation device 40 (FIG. 13) outputs the line clock signal NCLK ′ to 1 / (8
(× 1188), and a frequency-divided signal S400 corresponding to 1188 cycles of the line clock signal NCLK of which one cycle is 19.44 MHz is generated.

The counter circuit 410 uses the divided signal S40.
The synchronous clock signal 4f _sc generated by the clock generator 12 is counted every 0 and 1 cycle. That is, the counter circuit 410 counts the number of periods of the line clock signal NCLK and the synchronous clock signal 4f _sc between the 1188 periods. R
The TS generation circuit 164 subtracts the offset value j from the count value of the counter circuit 410, generates synchronization data RTS, and outputs it to the transmission device 18. This synchronization data RT
S indicates the frequency ratio between the line clock signal NCLK and the synchronous clock signal 4f _sc with reference to the line clock signal NCLK. The transmitter 18 receives the input synchronization data R
The TS is multiplexed into a PDU packet and transmitted to the data transmission device 3b side via the ATM adapter 7 and the ATM communication line 2.

On the data transmission device 3b side, the reception device 32 (FIGS. 9 and 10) separates the synchronization data RTS from the PDU packet received via the ATM adapter 7,
It outputs to the frequency dividing circuit 420 (FIG. 13) of the RTS generator 40. On the other hand, the frequency dividing circuit 430 frequency-divides the line clock signal NCLK ′ into a frequency of 1 / (8 × 1188) to generate a frequency-divided signal S430.

The phase comparison circuit 384 outputs the divided signal S42.
0, S430 are compared in phase, and the low-pass filter filters the comparison result S384 to obtain the clock control signal C.
C, controls the frequency of the synchronous clock signal 4f _sc generated by the clock generator 38, and transmits the data transmission device 3a.
It is synchronized with the side synchronization clock signal 4f _sc .

FIG. 15 is a block diagram of the third embodiment shown in FIG.
Synchronous data RT generated by the RTS generation device 40 shown in FIG.
It is a figure explaining the value of S. As described above, on the data transmission device 3a side according to the second embodiment, as shown in FIG.
As shown in (A) and (B), the counter circuit 410 (FIG. 13) has a line clock signal NCL of 19.44 MHz.
K, the synchronous clock signal 4f _sc is counted every 1188 cycles, and the line clock signal NCLK is calculated from the counted value S410.
The synchronization data RTS based on is generated.

In this case, when the frequencies of the synchronous clock signal 4f _sc and the line clock signal NCLK on the data transmission device 3a side are accurate, the count value S of the counter circuit 410
In 410, the count value S410 is almost 875,
The probability that the count value is 874 is about 1 / 1,000,000.

Therefore, almost no phase difference appears in the comparison result S384 of the phase comparison circuit 384 (FIG. 14) of the clock control device 42 on the data transmission device 3b side, and when the RTS generation device 40 and the clock control device 42 are used, RTS
The generator 16 and the clock controller 36 (see FIGS. 7 and 1).
Compared with the case of 1), it is possible to reproduce the synchronous clock signal 4f _sc with very little jitter on the data transmission device 3b side, and the audio signal between the data transmission devices 3a and 3b can be reproduced.
The transmission quality of video data is improved. The RTS generation device 40 and the clock control device 42 described in the third embodiment can be modified in the same manner as the RTS generation device 16 and the clock control device 36 described in the second embodiment. Is.

Fourth Embodiment In each of the embodiments described above, the D of NTSC system is used.
The case where the audio / video data of two standards are handled and the synchronization clock signal 4f _sc of about 14.3 MHz is synchronized between the data transmission devices 3a and 3b has been described, but in the fourth embodiment, for example, the component Video signal 4: 2: 2 (audio / video data of D1; SMPTE-
125M) and MPEG2 4: 2: 2 profile audio / video data, and synchronizing the 27.0 MHz interface clock signal ICL used in these systems between the data transmission devices 3a and 3b, or , PAL audio / video data and synchronizing the 177.344475 MHz SDI (SMPTE-259M) interface clock signal ICL in the PAL system between the data transmission devices 3a and 3b will be described.

First, the RT explained in the third embodiment.
S generator 40 and clock controller 42 (see FIG. 13,
14) using the component video signal 4:
2: 2 and MPEG2 4: 2: 2 profile audio / video data (hereinafter simply referred to as “MPEG2 audio / video data”) are transmitted between the data transmission devices 3a and 3b. Used in these schemes 2
A case where the interface clock signal ICL of 7.0 MHz is synchronized between the data transmission devices 3a and 3b will be described.

When synchronizing the interface clock signal ICL of the MPEG2 system between the data transmission devices 3a and 3b, the frequency dividing circuit 160 of the RTS generating device 40 and the frequency dividing circuit 380 of the clock control device 42 are removed, and the clock generating device is removed. The center oscillation frequency of 38 is 27.0
It is necessary to change to MHz and further to change the frequency division value 1 / n of the frequency dividing circuit 402 and the frequency dividing circuit 432. MPE
The frequency division value 1 / n of the frequency dividing circuit 402 when synchronizing the G system interface clock signal ICL is a numerical value of n = 18 × q, m = 25 × q (q is an integer) by solving the following equation. Can be obtained.

[0147]

N / NCLK = m / ICL (9) where n is an integer and the frequency division ratio of the frequency dividing circuits 402 and 432 is 1
/ N is a denominator, m is an integer, and the count value of the counter circuit 410 when n is the frequency dividing circuit 402, NCLK = 19.44
MHz, ICL = 27.0 MHz.

Therefore, the frequency division ratio of the frequency dividing circuit 402 is 1 /
By setting (q × 18), the RTS generation device 40 on the side of the data transmission device 3a uses q × 2 as the synchronization data RTS.
A value centered on 5-j (j is an offset value) is generated. This synchronization data RTS is multiplexed into a PDU packet (FIG. 2) by the transmission device 18, and is received by the reception device via the ATM adapter 7 on the data transmission device 3a side, the ATM communication line 2 and the ATM adapter 7 on the data transmission device 3b side. It is transmitted to 32, separated from the PDU packet, and input to the clock controller 42. The clock control device 42 controls the clock generation device 38 (FIGS. 9 and 11) based on the synchronous data RTS, and the data transmission device 3a.
The interface clock signal ICL on the side of the data transmission device 3b generated by the clock generator 38 is synchronized with the interface clock signal ICL on the side.

Next, by using the RTS generator 40 and the clock controller 42 (FIGS. 13 and 14), the PAL audio / video data is transmitted between the data transmitters 3a and 3b, and the SDI in the PAL system is transmitted. Method 177.34
A case where the interface clock signal ICL of 475 MHz is synchronized between the data transmission devices 3a and 3b will be described.

The SDI interface clock signal ICL in the PAL system is used as the data transmission device 3a, 3a.
When synchronizing between b, the frequency dividing circuit 160 of the RTS generation device 40 and the frequency dividing circuit 38 of the clock control device 42.
The frequency division ratio of 0 is changed to 1/10, and the clock generator 38
It is necessary to change the central oscillating frequency of 1 to 17.734475 MHz and further change the frequency division value 1 / n of the frequency dividing circuit 402 and the frequency dividing circuit 432.

The frequency division value 1 / n of the frequency dividing circuit 402 when synchronizing the SDI interface clock signal ICL in the PAL system is obtained by solving the following equation:
(N = 1288 × q, m = 1175 × q), (n = 39
21 × q, m = 3577 × q), (n = 5209 × q,
It is possible to obtain a combination of numerical values such as m = 4752 × q).

[0152]

N / NCLK = m / ICL (10) However, ICL = 17.734475 MHz.

Therefore, the frequency dividing ratio of the frequency dividing circuit 402 is 1 /
If (1288 × q), the value of the synchronization data RTS generated by the RTS generation device 16 is a value centered on 1175 × q−j. In addition, the frequency division ratio of the frequency dividing circuit 402 is 1 /
Assuming (3921 × q), the value of the synchronization data RTS generated by the RTS generation device 16 is a value centered on 3577 × q−j. In addition, the frequency division ratio of the frequency dividing circuit 402 is 1 /
If it is (5209 × q), the value of the synchronization data RTS generated by the RTS generation device 16 is a value centered on 4752 × q−j.

Whichever combination of these numerical values is used, as in the case of transmitting the above-mentioned MPEG2 audio / video data between the data transmission devices 3a and 3b,
The PAL audio / video data is transmitted to the data transmission device 3a,
It is possible to transmit between 3b and process in synchronization with the interface clock signal ICL of the SDI system in the PAL system.

As described above, the data transmission device 3
Appropriate changes are made to the components of a and 3b, and the frequency dividing circuit 16
By changing the frequency division ratio of 0, 380, 402, 432, the audio / video data of the D2 standard of the NTSC system is transmitted between the data transmission devices 3a and 3b, and about 14.3 MHz.
In addition to processing in synchronization with the synchronization clock signal 4f _sc of
It is possible to process audio / video data of the EG2 system and the PAL system in synchronization with the interface clock ICL of these systems.

Moreover, the numerical value n and the numerical value m shown in the fourth embodiment are optimized, and the interface clock signal I having less jitter in the data transmission device 3b is obtained.
CL can be reproduced. Therefore, the data transmission device 3
The reliability of audio / video data between a and 3b is increased.
The data transmission system 1 using the RTS generation device 40 and the clock control device 42 shown in the fourth embodiment.
As for the above, the modifications shown in the first to third embodiments are possible.

[0157]

As described above, according to the data transmission system of the present invention, a plurality of nodes (television broadcasting station) connected via a communication line for supplying a line clock signal such as an ATM communication line. It is possible to establish an exact synchronization relationship between Further, according to the data transmission system of the present invention, the synchronization reproduced due to the fact that the house clock signal (synchronous clock signal) and the line clock signal are not in a synchronous relationship between the nodes connected by the ATM communication line. It is possible to eliminate the influence of jitter or the like generated in the clock signal, and it becomes possible to transmit high-quality audio / video data via the ATM communication line.

Further, according to the data transmission system of the present invention, N nodes are connected between nodes connected by the ATM communication line.
Not only TSC audio / video data, but also component video signal 4: 2: 2 (D1 audio / video data; SMPTE-125M), MPEG2 4: 2:
Two-profile audio / video data, PAL audio / video data, etc. can also be transmitted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data transmission system according to the present invention.

FIG. 2 is a diagram showing a structure of a PDU packet which the data transmission device shown in FIG. 1 mutually transmits via an ATM communication line 2.

FIG. 3 is a diagram illustrating a configuration of audio / video data of D2 system.

FIG. 4 is a diagram showing a configuration example of a data transmission device (3a) shown in FIG.

5 is a diagram showing a configuration example of the data transmission device (3b) shown in FIG.

6 is a diagram showing a configuration of a transmission unit shown in FIG.

FIG. 7 is a diagram showing a configuration of the RTS generation device shown in FIG. 6 in the second embodiment.

FIG. 8 is a diagram showing a configuration of a transmission device shown in FIG.

9 is a diagram showing a configuration of a reception unit shown in FIG.

FIG. 10 is a diagram showing a configuration of a receiving device shown in FIG.

FIG. 11 is a diagram showing a portion related to processing of synchronous data RTS in the configuration of the clock control device shown in FIG. 9 in the second embodiment.

FIG. 12 shows the RTS shown in FIG. 6 in the second embodiment.
It is a figure explaining the value of the synchronous data RTS which a generation device produces.

13 is a diagram showing a configuration of an RTS generation device (40) used by replacing the RTS generation device (16) shown in FIG. 7 in the transmission section on the data transmission device (3a) side shown in FIG. .

14 relates to processing of synchronous data RTS in the configuration of the clock control device (42) used by replacing the clock control device (36) in the receiving unit on the data transmission device (3b) side shown in FIG. It is a figure which shows a part.

FIG. 15 shows the RT shown in FIG. 13 in the third embodiment.
It is a figure explaining the value of the synchronous data RTS which an S generation device produces.

FIG. 16 is a diagram showing a configuration of a conventional PLL oscillation circuit that generates a synchronous clock signal 4f _sc for a composite video signal in synchronization with a house clock signal.

[Explanation of symbols]

1 ... Data transmission system, 2 ... ATM communication line, 3, 3
a to 3f ... Data transmission devices 3, 14, 14a to 14f ...
Audio / video processing equipment (VTR device), 140 ... VTR device, 142 ... VTR monitor device, 144 ... Editing device,
Reference numeral 146 ... Monitor device for editor, 5 ... Transmitter, 12 ... Clock generator, 16, 40 ... RTS generator, 16
0,166,400,402 ... Frequency divider, 162,41
0 ... Counter circuit, 18 ... Transmission device, 180 ... First block, 182 ... S / P circuit, 184 ... Switch circuit,
186 ... Switch circuit, 188 ... Rounding circuit,
190 ... Shuffling circuit, 192 ... FIFO circuit, 1
94 ... Word width conversion circuit, 196 ... FIFO circuit, 20
0 ... Timing generating circuit a, 202 ... Timing generating circuit b, 204 ... Control circuit, 206 ... Reference signal generating circuit, 210 ... Second block, 212 ... Multiplexing circuit, 214 ... FIFO circuit, 216 ... Control circuit, 218 ... Timing generation circuit c, 22 ... Delay processing circuit, 6 ... Reception unit, 7 ... ATM adapter, 32 ... Reception device, 320 ... First block, 322 ... Input data control circuit, 324 ... Register circuit, 326 ... CRCC calculation Circuits, 328 ... Addition circuits, 330 ... Memory circuits, 332 ...
Memory circuit, 334 ... Register circuit, 336 ... Register circuit, 338 ... Control circuit, 340 ... Timing generating circuit d, 350 ... Second block, 352 ... Output data control circuit, 354 ... Register circuit, 356 ... Reference signal generating circuit 358 ... Deshuffling circuit, 360 ... Conceal circuit, 362 ... Error correction circuit, 364 ... FI
FO circuit, 366 ... Error correction circuit, 368 ... Switch circuit, 370 ... Timing generation circuit e, 372 ... Reference signal generation circuit, 374 ... Switch circuit, 376 ... P / S circuit, 378 ... Control circuit, 36, 42 ... Clock Controller, 380, 382, 388, 430, 432 ...
Frequency divider circuit, 384 ... Phase comparison circuit, 386 ... Low-pass filter, 38 ... Clock generator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location // H04N 5/262 H04N 7/00 Z

Claims (4)

[Claims] 1. A data transmission system for transmitting video data between a master-side data transmission device and a slave-side data transmission device connected via an asynchronous transmission mode (ATM) communication system, wherein the master The data transmission device on the side includes an independent clock signal generation unit that generates an independent clock signal that is independent of the line clock signal supplied by the ATM communication line and that is synchronized with the video data, and the line clock signal and the independent clock signal. Synchronization data generating means for generating synchronization data indicating a frequency ratio k: m (k and m are integers), and master side transmission for transmitting at least the generated synchronization data to the slave device via the ATM communication system. A data transmission device on the slave side, the data transmission device on the master side via the ATM communication system. Slave side receiving means for receiving the synchronous data transmitted from the slave side, and a dependent clock signal for generating a dependent clock signal dependent on the independent clock signal of the data transmitting device on the master side based on the received synchronous data. Generating means, data generating means for generating the transmission data in synchronization with the generated dependent clock signal, and at least the generated predetermined transmission data for the ATM
A data transmission system having slave side transmission means for transmitting to the master side data transmission device via a communication system. 2. The synchronous data generating means of the data transmission device on the master side is the number m of cycles of the independent clock signal for every k cycles of the line clock signal, or m of the independent clock signal.
Counting means for counting the number k of cycles of the line clock signal for each cycle, and subtraction generation means for generating a synchronous data by subtracting a constant j (j is an integer) from the counted number m of cycles or the number k of cycles The slave clock signal generating means of the slave side data transmission device includes: oscillating means for generating the slave clock signal having a frequency according to a control voltage; and adding the constant j to the received synchronization data. Then, adding means for calculating the number of cycles k or the number of cycles m and 1 / k for dividing the line clock signal into a frequency of 1 / k
k frequency dividing means and 1 / m that divides the dependent clock signal into a frequency of 1 / m
m frequency dividing means, phase comparing means for phase-comparing the divided line clock signal and the dependent clock signal, and a voltage corresponding to the phase difference between the divided line clock signal and the dependent clock signal 2. The data transmission system according to claim 1, further comprising: a control voltage generating unit that generates the control voltage. 3. The data rate of the ATM communication line is 62.
2.08 Mbps or 155.52 Mbps, the frequency of the line clock signal supplied by the ATM communication line is 19.44 MHz, and the video data is a component video signal 4:
2: 2 (D1 video signal; SMPTE-125M) or MPEG2 4: 2: 2 profile video signal, wherein the independent clock signal and the dependent clock signal are
D1 video signal of frequency 27.0 MHz or MPEG
3. The data transmission system according to claim 2, wherein the data is an interface clock signal of a 4: 2: 2 profile video signal of 2, and the frequency ratio m: k is substantially 25:18. 4. The data rate of the ATM communication line is 62.
2.08 Mbps or 155.52 Mbps, the frequency of the line clock signal supplied by the ATM communication line is 19.44 MHz, and the independent clock signal and the dependent clock signal are
An interface clock signal of the SDI system (SMPTE-259M) in the PAL system having a frequency of 17.734475 MHz, wherein the frequency ratio m: k is substantially 1175: 128.
The data transmission system according to claim 2, wherein the data transmission system is any one of 8, 3577: 3921 and 4752: 5209.