JPH0895785A - Branch predicting device - Google Patents

Abstract

PURPOSE: To prevent the execution speed of an instruction from decreasing owing to a reread of the instruction due to misprediction of branching of a CPU. CONSTITUTION: This branch predicting device has a branch flag 1-10 where whether or not branching is done is set before a branch instruction with an instruction in a program, a branch address storage part 1-6 which stores branch destination addresses 1-8 by branch instruction addresses 1-7 generated in the past, and an instruction preread part 1-5 which reads instructions out of a memory 1-2 in order, retrieves a branch address storage part 1-6 with the address of a branch instruction only when it is judged from the branch flag 1-10 whether or not branching is set at the time of a read of the branch instruction and the branching is set, and obtains a branch destination address 1-8 from the entry of a matching branch instruction address 1-7 and reads in instructions following the address in order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU branch prediction device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional CPU branch prediction device.

In FIG. 2, when the program 2-9 uses a branch instruction, the instruction prefetching unit 2-5 in the CPU 2-1 reads this branch instruction. When the branch instruction is read, a search is performed from the branch address storage unit 2-6 with the address of the branch instruction, the branch destination address 2-8 is obtained from the entry having the matching branch instruction address 2-7, and from this branch destination address Subsequent instructions are prefetched in sequence. This is to predict the branch destination by storing the branches that have occurred in the past in the branch address storage unit 2-6 and assuming that the branches having the same address are the same branches.

On the other hand, the instruction analysis section 2-4 is composed of the instruction prefetch section 2
The instruction received from -5 is analyzed and passed to the instruction execution section 2-3. The instruction execution unit 2-3 executes the instruction received from the instruction analysis unit 2-4. In this case, when the received instruction is a branch instruction, it is judged whether the branch destination address 2-8 predicted by the instruction prefetching unit 2-5 is correct as the branch destination address obtained by analysis, and if it is correct, it is left as it is. Take a branch. However, if it is incorrect, all the prefetched instructions are invalidated, the instruction prefetch unit 2-5 prefetches the instruction from the correct address according to the analysis result, and the branch destination address 2-of the branch address storage unit 2-6. Update 8.

[0005]

In the above-described conventional branch prediction device, prediction is performed assuming that the same branch as the past branch result is taken and prefetching is performed, but the prediction is not necessarily correct, and therefore the prediction is not correct. If it comes off,
Since it is necessary to reload the instruction, there is a drawback that the instruction execution speed decreases.

[0006]

A branch prediction apparatus according to the present invention branches according to a branch flag in which the presence or absence of a branch is set in advance by a command in a program and the address of a branch command that occurred in the past. A branch address storage unit that stores the destination address and instructions are sequentially read from the memory,
When a branch instruction is read, the presence or absence of a branch is judged by the branch flag, and only when the branch is set, a search is performed from the branch address storage unit with the address of the branch instruction, and the entry of the matching branch instruction address is searched. An instruction prefetch unit for obtaining a branch destination address and sequentially reading the instructions after the address is provided.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing the configuration of an embodiment of the present invention, the present embodiment is composed of an instruction executing section 1-3 and an instruction analyzing section 1-
4, a CPU 1-1 having an instruction prefetching unit 1-5, a branch address storage unit 1-6 and a branch flag 1-10, and a memory 1-2 storing a program 1-9. The branch address storage unit 1-6 stores a branch destination address 1-8 for each branch address 1-7 generated in the past. The branch flag 1-10 contains the program 1-9.
By the branch flag setting instruction in, the presence / absence of branch is set in advance before the branch instruction.

Next, the operation of this embodiment will be described.

First, the setting of the branch flag 1-10 will be described. The branch flag 1-10 reads, for example, a branch condition of an input / output device from an external port by the program 1-9 and compares it with a constant or variable in the program 1-9. The comparison result is set in the branch flag 1-10 by the instruction for setting the branch flag. Since this setting needs to be performed before the branch instruction step in the program 1-9, the instruction for setting the branch flag is set at the instruction step satisfying such a condition.

By the way, the instruction prefetching unit 1-5 sequentially reads instructions from the memory 1-2 until the branch instructions are read. When the branch instruction is read, the instruction prefetching unit 1-5 determines the presence / absence of a branch based on the contents of the branch flag 1-10. If the branch flag 1-10 indicates a branch, the branch address storage unit 1-6. The branch instruction address is searched, the branch destination address 1-8 is obtained from the entry having the matching branch instruction address 1-7, and the subsequent instructions are sequentially read from the branch destination address. On the other hand, when the branch flag 1-10 does not indicate a branch, the program 1-9 is executed regardless of the branch destination address 1-8, although the branch instruction is executed.
The commands are read in the order of the command step.

The instruction analyzing section 1-4 analyzes the instruction received from the instruction prefetching section 1-5 and transfers it to the instruction executing section 1-3.
The instruction execution unit 1-3 executes the instruction received from the instruction analysis unit 1-4. When the received instruction is a branch instruction, the instruction prefetch unit 1-5 determines whether or not the predicted branch destination address 1-8 is correct, and if correct, the branch is executed as it is. If it is wrong, all the prefetched instructions are invalidated, the instruction prefetch unit 1-5 prefetches the instruction from the correct address, and updates the branch destination address of the branch address storage unit 1-6. The branch flag 1-10 is used by the instruction execution unit 1-
Cleared when 3 executes the instruction.

[0012]

As described above, according to the present invention, the branch destination address is dynamically changed by setting the branch flag in the branch prediction of the CPU and setting it before the program uses the branch instruction. Unless it is a branch, if the branch that has occurred is the second or later branch, the prediction of the branch in the instruction prefetching section will be performed correctly, so that there is an effect that the reduction of the instruction execution speed of the CPU due to the reloading of the instruction can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 1-1,2-1 CPU 1-2, 2-2 memory 1-3, 2-3 instruction execution unit 1-4, 2-4 instruction analysis unit 1-5, 2-5 instruction prefetch unit 1-6, 2-6 Branch address storage unit 1-7, 2-7 Branch instruction address 1-8, 2-8 Branch destination address 1-9, 2-9 Program 1-10 Branch flag

Claims (2)

[Claims] 1. A branch flag in which presence / absence of a branch is set in advance before a branch instruction by an instruction in a program, a branch address storage unit that stores a branch destination address for each address of a branch instruction that occurred in the past, and a memory. From the branch address storage unit to search for the branch instruction address and match only if the branch flag is judged by the branch flag when the branch instruction is read and the branch is set. A branch prediction device having a branch destination address from an entry of a branch instruction address to be read, and an instruction prefetch unit for sequentially reading instructions after the address. 2. The branch according to claim 1, wherein the branch flag is set by a result of comparison between a branch condition of an input / output device read from the outside and a value of a constant or a variable in the program. Prediction device.