JPH0888364A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE: To reduce the time for film forming significantly by a method wherein the thickness of an etching stopper is reduced to a fraction of several number. CONSTITUTION: An n<+> -type thin film semiconductor layer 6 is formed so as to cover an etching stopper 5 and, further, cover the whole surface of a thin film semiconductor layer 4. Moreover, a resist film is formed on the surface of the n<+> -type thin film semiconductor layer 6 to form a natural oxide film on the surface of the layer 6. The resist film 7 is left only on a region on which the n<+> -type thin film semiconductor layer 6 and the resist film and the natural oxide film on the other region are removed. If wet-etching is applied, the region of the n<+> -type thin film semiconductor layer under the natural oxide film 6a corresponding to the remaining part of the resist film 7 is not etched and not removed. With this constitution, the thickness of the etching stopper layer 5 can be reduced to a fraction of several number and the film forming time can be reduced significantly in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Conventional methods for manufacturing thin film transistors include a bottom gate method in which a gate electrode is first formed on an insulating substrate such as a glass substrate, and a top gate method in which a gate electrode is later formed. FIG. 2 is a cross-sectional view showing a part of a manufacturing process of a conventional bottom gate type thin film transistor. First, the gate electrode 2 is formed on the insulating substrate 1, and the gate insulating film 3 such as silicon nitride (SiN) is formed on the entire surface of the insulating substrate 1 including the formed gate electrode 2. Further, a thin film semiconductor layer 4 of an amorphous silicon (Si) layer is formed on the entire surface of the gate insulating film 3. Then, after depositing an etching stopper layer 5 of silicon nitride (SiN), silicon oxide (SiO ₂ ) or the like on the entire surface of the thin film semiconductor layer 4 by CVD or sputtering, only the non-etched region of the thin film semiconductor layer 4 is left. Peel off. Further, an n ⁺ silicon (n ⁺ Si) layer 6 is deposited on the upper surface of the thin film semiconductor layer 4 including the etching stopper layer 5 by plasma CVD. Then, the n ⁺ silicon layer 6 is used as a resist film 7
Mask with. FIG. 2A shows a cross-sectional view after the above steps are completed. After that, dry etching is performed as shown in FIG.
As shown in (b), the unmasked region of the n ⁺ silicon layer 6 is etched. In this case, n ⁺
Since the etching rate selection ratio between the silicon layer 6 and the etching stopper layer 5 made of silicon nitride is only about 10, when the etching uniformity is taken into consideration, as shown in the etching state A of FIG. 5
It is necessary to perform etching processing even on the deep part of the.

[0003]

However, in the above-described conventional method of manufacturing a thin film transistor, since the etching rate selection ratio between the n ⁺ silicon layer and the etching stopper layer which is silicon nitride is only about 10, the etching uniformity can be improved. In order to maintain the etching stopper layer, it is necessary to perform etching processing even in a deep portion of the etching stopper layer, and therefore, the thickness of the etching stopper layer should be at least 500Å to 10
It was necessary to deposit 00Å, and there was a problem that the film formation process of the etching stopper layer took too long. The present invention is intended to solve such a conventional problem, and is excellent in that the time required for the film forming process of the etching stopper layer can be greatly reduced by reducing the thickness of the etching stopper layer to a fraction of the conventional thickness. It is an object to provide a method for manufacturing a thin film transistor.

[0004]

In order to achieve the above object, the present invention forms an etching stopper layer in a predetermined region on the upper surface of a first thin film semiconductor layer, and comprises the first thin film semiconductor layer including the etching stopper layer. A second thin film semiconductor layer containing impurities is formed on the entire upper surface of the second thin film semiconductor, and a resist film is formed on a region of the upper surface of the second thin film semiconductor that is not subjected to etching treatment. It is characterized in that the unetched region is removed by a wet etching solution.

[0005]

According to the present invention, by using the wet etching solution as the etching agent, the thickness of the etching stopper layer can be reduced to a fraction of that of the conventional one.
As a result, the time required for the film forming process of the etching stopper layer can be significantly reduced.

[0006]

1 is a sectional view showing a bottom gate type manufacturing process of a thin film transistor according to the present invention. A method of manufacturing a thin film transistor will be described with reference to these drawings in order. The thin film transistor in this embodiment is used in an active matrix type liquid crystal device.

First, as shown in FIG. 1A, a gate electrode 2 is formed on an insulating substrate 1, and silicon nitride (Si) is formed on the entire surface of the insulating substrate 1 including the formed gate electrode 2.
The gate insulating film 3 such as N) is formed. Further, amorphous silicon (S) is formed as a first semiconductor layer on the entire surface of the gate insulating film 3.
The i) layer thin-film semiconductor layer 4 is formed. Then, an etching stopper layer 5 such as silicon nitride (SiN) or silicon oxide (SiO ₂ ) is formed on the entire surface of the thin film semiconductor layer 4 by CVD.
Alternatively, it is deposited by sputtering. This etching stopper layer 5
The deposited thickness is less than 200Å, preferably about 100Å.

Next, the etching stopper layer 5 is processed with hydrofluoric acid. Thereafter, as shown in FIG. 1B, the etching stopper layer 5 is peeled off, leaving only the region of the thin film semiconductor layer 4 which is not etched. Further, as shown in FIG. 1C, n ⁺ silicon (n ⁺ S) is formed as a second semiconductor layer on the upper surface of the thin film semiconductor layer 4 including the etching stopper layer 5.
i) Deposit layer 6 by plasma CVD. And this n
^{+ The} silicon film 6 is covered with the resist film 7. At this time, a natural oxide film is formed on the entire surface of the n ⁺ silicon layer 6 (this state diagram is not shown). Next, the resist film 7 is exposed and patterned to leave the resist film 7 only in the region where the n ⁺ silicon layer 6 is formed. By treating this with hydrofluoric acid, as shown in FIG. 1D, the natural oxide film in the region of the n ⁺ silicon layer 6 where the resist film 7 is not applied is removed,
The natural oxide film 6a is left only on the surface of the region of the n ⁺ silicon layer 6 where the resist film 7 is applied. After that, the region of the n ⁺ silicon layer 6 which is not masked with the etching agent heated to about 80 ° C. is subjected to etching treatment. As an etching agent, an organic alkali, for example, a monoalkanolamine such as an ethanol compound or a methanol compound is used.

As a result, although the resist film 7 is directly dissolved by the above etching process, a natural oxide film 6a is formed on the surface of the n ⁺ silicon layer 6 on which the resist film 7 is applied, so that this region is It remains without being etched. FIG.
As shown in (e), n of the unmasked area
⁺ Only the silicon layer 6 is etched. Therefore,
Even if the thickness of the etching stopper layer 5 deposited is reduced to 200 Å or less, the etching uniformity can be maintained.

Although the thin film transistor in the above embodiment is of the bottom gate type, the present invention can be applied to a top gate type thin film transistor. Although the thin film transistor used in the liquid crystal device is taken as an example, the present invention is also effective as a method for manufacturing an IC such as a microprocessor or a memory.

[0011]

According to the present invention, a resist film is formed on an unetched region of the upper surface of an n ⁺ thin film semiconductor layer containing impurities, and an organic alkaline agent is used as an etching agent for the n ⁺ thin film semiconductor layer. By making the thickness of the etching stopper layer a fraction of that of the conventional one, it is possible to significantly reduce the time required for the step of forming the etching stopper layer and improve the throughput, which is the number of steps per unit time. You can Furthermore, since the etching stopper layer can be thinned, a thin film transistor having a thinner structure can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a thin film transistor of the invention.

FIG. 2 is a cross-sectional view showing a part of manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

1 Insulating Substrate 2 Gate Electrode 3 Gate Insulating Film 4 Thin Film Semiconductor Layer (First Thin Film Semiconductor Layer) 5 Etching Stopper Layer 6 n ⁺ Thin Film Semiconductor Layer (Second Thin Film Semiconductor Layer) 7 Resist Film

Claims (8)

[Claims] 1. An etching stopper layer is formed in a predetermined region on an upper surface of a first thin film semiconductor layer, and a second thin film semiconductor layer containing impurities is formed on the entire upper surface of the first thin film semiconductor layer including the etching stopper layer. And forming a resist film on a region of the upper surface of the second thin film semiconductor which is not subjected to etching treatment, and removing a region of the second thin film semiconductor layer which is not subjected to the resist film with a wet etching solution. Method of manufacturing thin film transistor. 2. The surface of the second thin film semiconductor layer is oxidized only on the area where the resist film is applied before the area of the second thin film semiconductor layer where the resist film is not applied is removed. The method for manufacturing a thin film transistor according to claim 1, wherein a film is formed. 3. The second wet etching solution
The method of manufacturing a thin film transistor according to claim 1, wherein the resist film is dissolved by the wet etching solution when removing a region of the thin film semiconductor layer where the resist film is not applied. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the wet etching solution is an organic alkaline agent. 5. The method of manufacturing a thin film transistor according to claim 4, wherein a monoalkanolamine such as an ethanol compound or a methanol compound is used as the etching agent. 6. The method of manufacturing a thin film transistor according to claim 1, wherein the first thin film semiconductor layer is composed of an amorphous silicon layer. 7. The method of manufacturing a thin film transistor according to claim 1, wherein the etching stopper layer is deposited to a thickness of about 200Å or less. 8. The method of manufacturing a thin film transistor according to claim 1, wherein the second thin film semiconductor layer is composed of an n ⁺ silicon layer.