JPH0888199A - Method of forming external electrode of surface mount electronic component - Google Patents
Method of forming external electrode of surface mount electronic componentInfo
- Publication number
- JPH0888199A JPH0888199A JP22504894A JP22504894A JPH0888199A JP H0888199 A JPH0888199 A JP H0888199A JP 22504894 A JP22504894 A JP 22504894A JP 22504894 A JP22504894 A JP 22504894A JP H0888199 A JPH0888199 A JP H0888199A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- masking
- masking members
- external electrode
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、表面実装型電子部品、
例えば圧電部品、インダクタ部品、コンデンサ部品、I
C部品等の外部電極形成方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a surface mount type electronic component,
For example, piezoelectric parts, inductor parts, capacitor parts, I
The present invention relates to a method for forming external electrodes such as C parts.
【0002】[0002]
【従来の技術と課題】従来より、表面実装型電子部品に
外部電極を形成する場合には、電子部品の表面に導電性
ペーストの転写等の手段にて形成していた。ところが、
電子部品の小型化あるいは、外部電極数の増加が進むに
つれて、外部電極を従来より精度良く形成する必要が生
じてきた。しかしながら、従来の方法では安定してより
精度の良い外部電極を形成することが困難であった。2. Description of the Related Art Conventionally, when an external electrode is formed on a surface mount type electronic component, it is formed on the surface of the electronic component by means such as transfer of a conductive paste. However,
As electronic components have become smaller and the number of external electrodes has increased, it has become necessary to form the external electrodes more accurately than ever before. However, it has been difficult to form a stable and more accurate external electrode by the conventional method.
【0003】そこで、本発明の課題は、外部電極を精度
良くかつ安定して形成することができる表面実装型電子
部品の外部電極形成方法を提供することにある。Therefore, an object of the present invention is to provide a method of forming an external electrode of a surface mount type electronic component which can form the external electrode with high accuracy and stability.
【0004】[0004]
【課題を解決するための手段と作用】以上の課題を解決
するため、本発明に係る表面実装型電子部品の外部電極
形成方法は、(a)電子部品の一つの面に第1マスキン
グ材を設けると共に、第1マスキング材が設けられた面
に隣接する少なくとも一つの面に第2マスキング材を設
ける工程と、(b)前記第1及び第2マスキング材が設
けられた面に電極膜を形成する工程と、(c)前記第1
及び第2マスキング材を電子部品表面から外して前記第
1及び第2マスキング材表面に形成された余分な電極膜
と共に除去し、前記電子部品表面に所望の外部電極を形
成する工程と、を備えたことを特徴とする。In order to solve the above problems, in the method of forming external electrodes of a surface mount type electronic component according to the present invention, (a) a first masking material is provided on one surface of the electronic component. And a step of providing a second masking material on at least one surface adjacent to the surface provided with the first masking material, and (b) forming an electrode film on the surface provided with the first and second masking materials. And (c) the first
And removing the second masking material from the surface of the electronic component and removing it together with the surplus electrode film formed on the surfaces of the first and second masking materials to form a desired external electrode on the surface of the electronic component. It is characterized by that.
【0005】以上の方法により、第1及び第2マスキン
グ材は電子部品表面の所定の部分を覆い、第1及び第2
マスキング材から露出した部分に精度の良い外部電極が
形成される。また、第1及び第2マスキング材をその表
面に形成された余分な電極膜と共に電子部品表面から外
すだけで外部電極が容易に形成される。By the above method, the first and second masking materials cover predetermined portions of the surface of the electronic component, and the first and second masking materials are provided.
An accurate external electrode is formed on the portion exposed from the masking material. Further, the external electrodes can be easily formed by simply removing the first and second masking materials together with the extra electrode film formed on the surface thereof from the surface of the electronic component.
【0006】[0006]
【実施例】以下、本発明に係る表面実装型電子部品の外
部電極形成方法の実施例について添付図面を参照して説
明する。 [第1実施例、図1〜図5]第1実施例は圧電部品を例
にして説明する。図1に示すように、表面実装型圧電部
品1は、圧電体基板2と、この圧電体基板2を挟んで振
動空間を形成する封止基板7,8とで構成されている。
圧電体基板2はPZT等のセラミックス材からなる。圧
電体基板2としてはPZT等のセラミックス材以外に、
水晶、LiTaO3等であってもよい。圧電体基板2の
上下面には振動電極3,4が設けられている。振動電極
3は圧電体基板2の上面左側隅部に設けた引出し電極5
に電気的に接続し、振動電極4は圧電体基板2の下面右
側隅部に設けた引出し電極6に電気的に接続している。
これらの電極3〜6はスパッタリング、蒸着あるいは印
刷乾燥等の手段にて形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of forming external electrodes of a surface mount type electronic component according to the present invention will be described below with reference to the accompanying drawings. [First Embodiment, FIGS. 1 to 5] The first embodiment will be described by taking a piezoelectric component as an example. As shown in FIG. 1, the surface-mounted piezoelectric component 1 is composed of a piezoelectric substrate 2 and sealing substrates 7 and 8 that sandwich the piezoelectric substrate 2 to form a vibration space.
The piezoelectric substrate 2 is made of a ceramic material such as PZT. As the piezoelectric substrate 2, other than ceramic materials such as PZT,
It may be quartz, LiTaO 3 or the like. Vibration electrodes 3 and 4 are provided on the upper and lower surfaces of the piezoelectric substrate 2. The vibrating electrode 3 is a lead electrode 5 provided on the upper left corner of the piezoelectric substrate 2.
The vibrating electrode 4 is electrically connected to the extraction electrode 6 provided on the lower right corner of the piezoelectric substrate 2.
These electrodes 3 to 6 are formed by means such as sputtering, vapor deposition or print drying.
【0007】封止基板7,8はアルミナ等のセラミック
ス材からなり、それぞれ一方の面に振動空間形成用凹部
7a,8aを設けている。この封止基板7,8は、図2
に示すように、圧電体基板2を間に挟んでエポキシ系の
接着剤等を介して固着され、内部に密閉された振動空間
を有する圧電部品1とされる。The sealing substrates 7 and 8 are made of a ceramic material such as alumina and have vibration space forming recesses 7a and 8a formed on one surface thereof. The sealing substrates 7 and 8 are shown in FIG.
As shown in FIG. 3, the piezoelectric component 1 is fixed with the piezoelectric substrate 2 sandwiched therebetween via an epoxy adhesive or the like, and has a vibration space sealed inside.
【0008】図3に示すように、圧電部品1は、上面及
び下面すなわち封止基板8及び7の表面に、第1マスキ
ング材10,11が密着される。密着する方法として
は、単純に第1マスキング材10,11を封止基板8,
7に当てるだけの方法、接着剤を介して第1マスキング
材10,11を封止基板8,7に接着する方法、あるい
は液体状態の樹脂をスクリーン印刷等の手段にて封止基
板7,8に塗布、乾燥させて封止基板7,8に密着した
第1マスキング材10,11とする方法等がある。第1
マスキング材10,11には手前側の二つの隅部に切欠
き10a,10b、11a,11bが設けられており、
この切欠き10a〜11bからそれぞれ封止基板8及び
7の表面の一部が露出する。As shown in FIG. 3, in the piezoelectric component 1, the first masking materials 10 and 11 are adhered to the upper and lower surfaces, that is, the surfaces of the sealing substrates 8 and 7. As a method of bringing them into close contact, simply use the first masking materials 10 and 11 as the sealing substrate 8,
7 or a method of adhering the first masking material 10 or 11 to the sealing substrate 8 or 7 via an adhesive, or a resin in a liquid state by means of screen printing or the like. There is a method in which the first masking materials 10 and 11 are applied and dried to be in close contact with the sealing substrates 7 and 8. First
The masking materials 10 and 11 are provided with notches 10a, 10b, 11a and 11b at two corners on the front side,
Part of the surfaces of the sealing substrates 8 and 7 is exposed from the notches 10a to 11b.
【0009】次に、第1マスキング材10,11が密着
した面に隣接する面すなわち圧電部品1の端面に、それ
ぞれ第2マスキング材12,13,14,15を密着さ
せる。この場合、圧電部品1の手前側隅部の端面は第2
マスキング材12,13,14から露出する。第1及び
第2マスキング材10〜15の材料としては、金属板、
耐熱性樹脂板、セラミック板等がある。Next, the second masking materials 12, 13, 14, 15 are brought into close contact with the surfaces adjacent to the surfaces with which the first masking materials 10, 11 are in close contact, that is, the end surfaces of the piezoelectric component 1. In this case, the end surface of the front corner of the piezoelectric component 1 is the second
It is exposed from the masking materials 12, 13, and 14. As the material of the first and second masking materials 10 to 15, metal plates,
There are heat-resistant resin plates and ceramic plates.
【0010】次に、図4に示すように、図中矢印方向か
らAg,Au,Pd,Cu,Ni,Cr及びそれらの合
金等の蒸着、スパッタリング又は溶射等の処理が行なわ
れる。処理は各方向同時に行なってもよいし、別々に行
なってもよい。蒸着源又はスパッタリング源又は溶射源
から飛散してきた蒸着金属やスパッタリング金属や溶射
金属は、圧電部品1の表面に達し、電極膜を形成する。
この電極膜は第1及び第2マスキング材10〜15の表
面にも形成される。Next, as shown in FIG. 4, processing such as vapor deposition, sputtering or thermal spraying of Ag, Au, Pd, Cu, Ni, Cr and their alloys is carried out in the direction of the arrow in the figure. The treatments may be performed simultaneously in each direction or separately. The vapor deposition metal, the sputtering metal or the thermal spray metal scattered from the vapor deposition source, the sputtering source or the thermal spray source reaches the surface of the piezoelectric component 1 and forms an electrode film.
This electrode film is also formed on the surfaces of the first and second masking materials 10 to 15.
【0011】次に、図5に示すように、第1及び第2マ
スキング材10〜15を圧電部品1の表面から外して第
1及び第2マスキング材10〜15の表面に形成された
余分な電極膜と共に除去し、圧電部品1の表面に精度の
良い外部電極20,21を形成する。さらに必要があれ
ば、この外部電極20,21の表面にめっき等の処理に
てめっき金属層を設けてもよい。Next, as shown in FIG. 5, the first and second masking materials 10 to 15 are removed from the surface of the piezoelectric component 1, and the extra portions formed on the surfaces of the first and second masking materials 10 to 15 are removed. This is removed together with the electrode film, and the external electrodes 20 and 21 with high accuracy are formed on the surface of the piezoelectric component 1. If necessary, a plating metal layer may be provided on the surfaces of the external electrodes 20 and 21 by a treatment such as plating.
【0012】[第2実施例、図6及び図7]第2実施例
は、マザーボードを利用してバッチ処理を行なうことに
より、量産に適した方法でIC部品を製造する場合につ
いて説明する。図6に示すように、複数のIC部品が帯
状に配置されているIC部品用マザーボード31の手前
側の面及び奥側の面に、第1マスキング材32を密着さ
せる。マザーボード31相互間は第1マスキング材32
を介して密着され、蒸着金属やスパッタリング金属や溶
射金属がマザーボード31相互の隙間に回り込まないよ
うに工夫される。ただし、第2実施例のように複数のマ
ザーボード31を重ね合わせることなく、単品毎にセッ
トしてもよい。第1マスキング材32の両側縁部には所
定の間隔で切欠き32aが設けられており、この切欠き
32aからマザーボード31の手前側の面及び奥側の面
の一部が露出している。[Second Embodiment, FIGS. 6 and 7] A second embodiment will describe a case where an IC component is manufactured by a method suitable for mass production by performing batch processing using a mother board. As shown in FIG. 6, the first masking material 32 is brought into close contact with the front surface and the back surface of the IC component motherboard 31 in which a plurality of IC components are arranged in a strip shape. The first masking material 32 is provided between the mother boards 31.
It is intimately contacted via the vias, and the devised metal, the sputtered metal, and the sprayed metal are devised so as not to go around into the gaps between the mother boards 31. However, it is also possible to set individual motherboards without stacking a plurality of motherboards 31 as in the second embodiment. Notches 32a are provided at predetermined intervals on both side edges of the first masking material 32, and the front surface and the back surface of the motherboard 31 are partially exposed from the notches 32a.
【0013】次に、第1マスキング材32が密着した面
に隣接する面、すなわちマザーボード31の上面及び下
面にそれぞれ短冊状の第2マスキング材33,34を密
着させる。次に、図6中矢印方向からAg,Au,P
d,Cu,Ni,Cr及びそれらの合金等の蒸着、スパ
ッタリング又は溶射等の処理が行なわれる。スパッタリ
ング源等から飛散してきたスパッタリング金属はマザー
ボード31の表面に達し、電極膜を形成する。この電極
膜は第1及び第2マスキング材32〜34の表面にも形
成される。Next, strip-shaped second masking materials 33 and 34 are respectively brought into close contact with the surface adjacent to the surface with which the first masking material 32 is in close contact, that is, the upper surface and the lower surface of the mother board 31. Next, from the arrow direction in FIG.
Processing such as vapor deposition, sputtering or thermal spraying of d, Cu, Ni, Cr and alloys thereof is performed. Sputtering metal scattered from the sputtering source or the like reaches the surface of the mother board 31 and forms an electrode film. This electrode film is also formed on the surfaces of the first and second masking materials 32-34.
【0014】次に、第1及び第2マスキング材32〜3
4をマザーボード31の表面から外して第1及び第2マ
スキング材32〜34の表面に形成された余分な電極膜
と共に除去し、マザーボード31の表面に精度の良い外
部電極38(図7参照)を形成する。次に、マザーボー
ド31を一点鎖線Cに沿って切断し、図7に示した所定
サイズのIC部品36を切り出す。Next, the first and second masking materials 32 to 3
4 is removed from the surface of the mother board 31 and is removed together with the excess electrode film formed on the surfaces of the first and second masking materials 32 to 34, and an accurate external electrode 38 (see FIG. 7) is formed on the surface of the mother board 31. Form. Next, the motherboard 31 is cut along the alternate long and short dash line C to cut out the IC component 36 of a predetermined size shown in FIG.
【0015】[他の実施例]なお、本発明に係る表面実
装型電子部品の外部電極形成方法は前記実施例に限定す
るものではなく、その要旨の範囲内で種々に変形するこ
とができる。前記実施例は圧電部品及びIC部品の場合
について説明したが、抵抗部品、インダクタ部品、コン
デンサ部品等であってもよい。[Other Embodiments] The external electrode forming method of the surface mount type electronic component according to the present invention is not limited to the above embodiment, but can be variously modified within the scope of the invention. Although the above embodiments have described the case of the piezoelectric component and the IC component, the component may be a resistor component, an inductor component, a capacitor component, or the like.
【0016】また、第1及び第2マスキング材の形状、
材質、厚み等は電子部品の仕様に合わせて種々選択され
る。また、前記実施例のように、第1及び第2マスキン
グ材を対向させて電子部品の表面に配設させる必要はな
く、第1及び第2マスキング材をそれぞれ電子部品の一
面のみに配設させるだけであってもよい。Further, the shapes of the first and second masking materials,
The material, thickness, etc. are variously selected according to the specifications of the electronic component. In addition, unlike the above-described embodiment, it is not necessary to face the first and second masking materials to be provided on the surface of the electronic component, and the first and second masking materials are provided only on one surface of the electronic component. May be only.
【0017】[0017]
【発明の効果】以上の説明で明らかなように、本発明に
よれば、電子部品の一つの面に第1マスキング材を設け
ると共に、第1マスキング材が設けられた面に隣接する
少なくとも一つの面に第2マスキング材を設けた後、電
極膜を形成し、さらに第1及び第2マスキング材を電子
部品表面から外して余分な電極膜と共に除去して電子部
品表面に所望の外部電極を形成したので、精度の良い外
部電極を形成することができる。また外部電極の形成に
際してはバッチ処理が可能であり、量産化を容易に図る
ことができる。As is apparent from the above description, according to the present invention, the first masking material is provided on one surface of the electronic component, and at least one surface adjacent to the surface provided with the first masking material is provided. After providing the second masking material on the surface, an electrode film is formed, and the first and second masking materials are removed from the surface of the electronic component and removed together with the excess electrode film to form a desired external electrode on the surface of the electronic component. Therefore, it is possible to form an accurate external electrode. In addition, batch processing can be performed when forming the external electrodes, and mass production can be facilitated.
【図1】本発明に係る表面実装型電子部品の外部電極形
成方法の第1実施例を示す分解斜視図。FIG. 1 is an exploded perspective view showing a first embodiment of a method of forming external electrodes of a surface mount electronic component according to the present invention.
【図2】図1に続く外部電極形成方法を示す斜視図。FIG. 2 is a perspective view showing an external electrode forming method following FIG.
【図3】図2に続く外部電極形成方法を示す斜視図。FIG. 3 is a perspective view showing an external electrode forming method following FIG.
【図4】図3に続く外部電極形成方法を示す斜視図。FIG. 4 is a perspective view showing an external electrode forming method following FIG.
【図5】図4に続く外部電極形成方法を示す斜視図。FIG. 5 is a perspective view showing an external electrode forming method following FIG.
【図6】本発明に係る表面実装型電子部品の外部電極形
成方法の第2実施例を示す斜視図。FIG. 6 is a perspective view showing a second embodiment of a method for forming external electrodes of a surface mount electronic component according to the present invention.
【図7】図6に続く外部電極形成方法を示す斜視図。7 is a perspective view showing an external electrode forming method following FIG.
1…圧電部品 10,11…マスキング材 12,13,14,15…第2マスキング材 20,21…外部電極 31…IC部品用マザーボード 32…第1マスキング材 33,34…第2マスキング材 36…IC部品 38…外部電極 DESCRIPTION OF SYMBOLS 1 ... Piezoelectric component 10, 11 ... Masking material 12, 13, 14, 15 ... 2nd masking material 20, 21 ... External electrode 31 ... IC component motherboard 32 ... 1st masking material 33, 34 ... 2nd masking material 36 ... IC parts 38 ... External electrodes
Claims (1)
を設けると共に、第1マスキング材が設けられた面に隣
接する少なくとも一つの面に第2マスキング材を設ける
工程と、 前記第1及び第2マスキング材が設けられた面に電極膜
を形成する工程と、 前記第1及び第2マスキング材を電子部品表面から外し
て前記第1及び第2マスキング材表面に形成された余分
な電極膜と共に除去し、前記電子部品表面に所望の外部
電極を形成する工程と、 を備えたことを特徴とする表面実装型電子部品の外部電
極形成方法。1. A step of providing a first masking material on one surface of an electronic component and providing a second masking material on at least one surface adjacent to the surface provided with the first masking material, A step of forming an electrode film on the surface provided with the second masking material, and an extra electrode film formed on the surfaces of the first and second masking materials by removing the first and second masking materials from the surface of the electronic component. And a step of forming a desired external electrode on the surface of the electronic component together with the step of removing the external electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22504894A JP3198822B2 (en) | 1994-09-20 | 1994-09-20 | External electrode forming method for surface mount electronic components |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22504894A JP3198822B2 (en) | 1994-09-20 | 1994-09-20 | External electrode forming method for surface mount electronic components |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0888199A true JPH0888199A (en) | 1996-04-02 |
JP3198822B2 JP3198822B2 (en) | 2001-08-13 |
Family
ID=16823227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22504894A Expired - Fee Related JP3198822B2 (en) | 1994-09-20 | 1994-09-20 | External electrode forming method for surface mount electronic components |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3198822B2 (en) |
-
1994
- 1994-09-20 JP JP22504894A patent/JP3198822B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3198822B2 (en) | 2001-08-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1042079A1 (en) | Improved miniature surface mount capacitor and method of making same | |
JP2002064002A (en) | Chip resistor and its manufacturing method | |
JPS5977715A (en) | Chip piezoelectric oscillator component | |
JP2616785B2 (en) | Method of forming external electrodes of multilayer ceramic capacitor | |
JPH0888199A (en) | Method of forming external electrode of surface mount electronic component | |
JPH09181557A (en) | Electronic part | |
JPS59110217A (en) | Piezoelectric oscillating parts in chip shape and its manufacture | |
JP4067923B2 (en) | Manufacturing method of chip resistor | |
JP2001351801A (en) | Chip resistor | |
JPS63172401A (en) | Chip resistor, chip resistor assembly and manufacture of chip resistor | |
JPH10256001A (en) | Chip electronic part | |
JP3772270B2 (en) | Small electronic component manufacturing method and chip resistor | |
JPH01189102A (en) | Manufacture of electrodes of circuit component | |
JP4504577B2 (en) | Manufacturing method of chip resistor | |
JPH01283809A (en) | Chip type electronic parts | |
JPH09116047A (en) | Structure of ceramic package | |
JPH10242794A (en) | Surface mount capacitor incorporating piezoelectric resonator | |
JP2003297670A (en) | Chip type composite part | |
JP2002203739A (en) | Capacitor element | |
JPH1167508A (en) | Composite element and its manufacture | |
JPH0870230A (en) | Production of piezoelectric component | |
JPH05291735A (en) | Printed wiring board | |
JPH10294207A (en) | Composite element and manufacture thereof | |
JPH08172004A (en) | Manufacture of chip resistor | |
JP3257274B2 (en) | Manufacturing method of piezoelectric parts |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080615 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20090615 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20090615 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20100615 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110615 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20120615 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130615 Year of fee payment: 12 |
|
LAPS | Cancellation because of no payment of annual fees |