JPH088704A - High side switch circuit - Google Patents

Abstract

PURPOSE:To keep a surge voltage protecting function and also to reduce the ON resistance of a MOS transistor Tr for a high side switch in order to reduce the power loss of a high side switch circuit. CONSTITUTION:A high side switch circuit contains a high side switch MOS Tr1 and surge input detection circuit 10 which detects the surge voltage of levels higher higher than the maximum rated power voltage. In such a constitution, the voltage boosted by a booster circuit 20 is fed back to the gate of a MOS Tr2 which protects the surge voltage higher than the maximum rated power voltage. Thus the voltage of the Tr2. can be reduced and the voltage supplied to the circuit 20 can be increased up to a level approximately to the power voltage. As a result, the voltage boosted effectively to the power voltage is supplied to the Tr1. Thus it is possible to keep a surge voltage protecting function, to reduce the ON resistance of the Tr1, and also to reduce the power loss of the switch circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high side switch circuit including a high side switch placed on the high side which is a power supply voltage side of a bridge circuit and the like and a drive circuit for the high side switch.

[0002]

2. Description of the Related Art Recently, M0 has been used as a high speed switching element.
S-transistors are widely used, and the use of M0S transistors is well established in bridge circuits such as H-bridge circuits. The circuit configuration is simplified by using complementary elements of different polarities in the bridge circuit, but since the P-channel element is expensive and the performance is inferior, the bridge circuit using only the N-channel element is becoming mainstream. In the case of a bridge circuit configured using all N-channels, the source of the high-side M0S transistor is a so-called floating drive in which the potential changes in the output state, so the voltage applied to the gate is equal to the power supply voltage + M0S transistor. It is necessary to boost the voltage above the threshold value.

Further, if the ON resistance of the M0S transistor is large, the power consumed by the M0S transistor is large, and therefore it is desirable that the ON resistance is as small as possible. Since the on-resistance decreases as the voltage applied to the gate increases, it is desirable to apply a voltage as high as possible to reduce the on-resistance. For these reasons, the high-side switch circuit is provided with a booster circuit that boosts the power supply voltage to drive the high-side M0S transistor, that is, the high-side switch. Further, a protection circuit for protecting this booster circuit from a surge voltage higher than the maximum rated power supply voltage is also required.

FIG. 4 shows an example of a conventional high side switch circuit of this type. The M0S transistor Tr1 is a high side switch, and the source
A zener diode ZD1 for protection against a surge between the drains is connected. The output of the booster circuit 21 is connected to the gate of the M0S transistor Tr1. The booster circuit 21 includes an oscillator 2, a capacitor C2, and a diode D4 provided in a line for transferring charges from a power supply terminal to the capacitor C2 and a diode D5 provided in a line for transferring charges from the capacitor C2 to the gate of the M0S transistor Tr1. It

Between the power supply terminal VDD and the booster circuit 21, a surge voltage protection M0S transistor Tr4 having a voltage higher than the maximum rated power supply voltage is connected. A resistor R2 having a resistance value capable of sufficiently limiting surge current is connected between the power supply terminal VDD and the gate of the MOS transistor Tr4.
Further, a switching M0S transistor Tr5 for surge voltage protection is connected between the gate of the M0S transistor Tr4 and the ground.

The gate of the M0S transistor Tr5 is connected to the output of the surge input detection circuit 10 for detecting a surge voltage higher than the maximum rated power supply voltage. Such a surge input detection circuit 10 is disclosed, for example, in Japanese Patent Application No. 5-550, which has already been filed.
Similar to that disclosed at 84. Zener diode ZD6 between power supply terminal VDD and ground,
The resistor 3 and the resistor 4 are connected in series, and the resistor 3 and the resistor 4 are connected.
The positive input terminal of the comparator 3 is connected to the connection point of. The negative input terminal of the comparator 3 is connected to the reference voltage circuit 4.

Next, the operation of this conventional example will be described. In the booster circuit 21, from the power supply terminal VDD to M0S
The electric charge supplied to the capacitor C2 via the transistor Tr4 and the diode D4 is continuously sent out in one direction by the oscillator 2 via the diode D5, thereby boosting the gate potential of the M0S transistor Tr1.

In the surge input detection circuit 10, the comparator 3 compares the input voltage from the power supply terminal VDD divided by the resistors 3 and 4 with the reference voltage supplied from the reference voltage circuit 2. When a voltage above the reference voltage value is input to the comparator 3, it is determined that a surge voltage above the maximum rated power supply voltage is input to the power supply terminal VDD, and a detection signal is output. This detection signal turns on the M0S transistor Tr5, thus turning off the M0S transistor Tr4, and the booster circuit 21 is protected from the surge voltage.

When the M0S transistor Tr4 is turned off, the surge current flows through the M0S transistor Tr5 to the ground. The resistor R2 functions to limit the surge current to the extent that the MOS transistor Tr5 is not destroyed by this surge current. Therefore, if the resistance value can sufficiently limit the surge current, M
A resistor using a 0S transistor may be used.

[0010]

However, in such a conventional high side switch circuit, in the line for supplying the electric charge to the capacitor C2 of the booster circuit 21, M
A voltage drop corresponding to the threshold value of the 0S transistor Tr4 occurs. Therefore, the capacitor C of the booster circuit 21 is substantially
Since the power supply voltage for supplying the electric charge to 2 decreases, the power supply voltage applied to the power supply terminal VDD cannot be efficiently boosted, and a sufficiently high voltage may be applied to the gate of the M0S transistor Tr1. Therefore, there is a problem that the ON resistance of the M0S transistor Tr1 cannot be reduced to a desired value. Therefore, the present invention, in view of the above conventional problems, while maintaining the surge voltage protection function,
An object of the present invention is to provide a high-side switch circuit in which the on resistance of a M0S transistor for a high-side switch is reduced and power loss is reduced.

[0011]

In order to achieve the above object, the present invention supplies a first M0S transistor for a high side switch and a gate voltage obtained by boosting a power supply voltage to the first M0S transistor. Booster means, surge input detection means for detecting a surge voltage higher than the maximum rated power supply voltage, and a second M provided between the booster means and the power supply terminal and turned off based on the output of the surge input detection means.
In a high-side switch circuit including an OS transistor, a resistor is provided between the gate of the second MOS transistor and a power supply terminal, and the second MO transistor is provided.
A third MO is provided between the gate of the S transistor and the ground.
An S transistor is provided, and the voltage boosted by the boosting means is fed back to the gate of the second MOS transistor via the first diode, and the third M
The output of the surge input detecting means is connected to the gate of the OS transistor, and the second MOS transistor is turned off by turning on the third MOS transistor.

[0012]

In the high side switch circuit having the first M0S transistor for the high side switch and the surge input detecting means for detecting the surge voltage higher than the maximum rated power supply voltage, the voltage boosted by the boosting means is the maximum rated power supply voltage. By feeding back to the gate of the second M0S transistor for surge voltage protection described above, the second M0S transistor is fed back.
It reduces the voltage drop in the S-transistor and increases the voltage supplied to the boosting means to a value close to the power supply voltage.
As a result, the voltage efficiently boosted with respect to the power supply voltage can be supplied to the first M0S transistor. Further, since one boosting means boosts the gate potential of the first M0S transistor and the gate potential of the second M0S transistor, it is not necessary to provide another boosting means.

[0013]

1 is a circuit diagram showing a first embodiment of the present invention. The M0S transistor Tr1 is the same high-side switch as shown in FIG. 4, and a Zener diode ZD1 for gate protection is connected between the drain and source. The output of the booster circuit 20 is connected to the gate of the M0S transistor Tr1. The booster circuit 20 includes an oscillator 1, a capacitor C1 and a power supply terminal, and a capacitor C1.
And a diode D3 provided on the line for transferring charges from the capacitor C1 to the gate of the MOS transistor Tr1. Between the power supply terminal VDD and the booster circuit 20, a M0S transistor T for protection against surge voltage exceeding the maximum rated power supply voltage is provided.
r2 is connected, and the M0S transistor Tr2 is manufactured in the same process as the M0S transistor Tr1 at the time of manufacturing.

Power supply terminal VDD and MOS transistor Tr2
A resistor R1 is connected between the gates of the. The output of the booster circuit 20 is taken out from behind the diode D3, and M
It is fed back to the gate of the 0S transistor Tr2 via the diode 1. Further, a switch M0S transistor Tr3 for protecting the surge voltage is connected between the gate of the M0S transistor Tr2 and the ground. The output of the surge input detection circuit 10 that detects a surge voltage equal to or higher than the maximum rated power supply voltage is connected to the gate of the M0S transistor Tr3. The surge input detection circuit 10 is the same as that shown in FIG.

Further, the resistor R1 has a resistance value capable of sufficiently limiting the surge current, and has a function of limiting the surge current to the extent that the M0S transistor Tr3 is not destroyed by the surge current. Further, since the output of the booster circuit 20 is connected to the power supply terminal VDD through the resistor R1, the resistor R1 is driven by the output of the booster circuit 20. When the point where the resistor R1 is connected to the booster circuit 20 is point A, and the resistance value of the resistor R1 is r1 and the potential at point A is V (A), the other end of the resistor R1 is connected to the power supply voltage. Therefore, V (A) is expressed as V (A) = power supply voltage + I · r1 (1).

When the current flowing from the booster circuit 20 to the resistor R1 is I, the amount of charge transferred by the capacitor C1 is Q, and the oscillation cycle of the oscillator 1 is t, the current flowing to the gate of the M0S transistor is very small. If omitted,
The current I is represented by I = Q / t (2). Here, when r1 is multiplied on both sides of the equation (2), it is expressed as I · r1 = Q · r1 / t (3). At this time, if the voltage between the terminals of the capacitor C1 is V (C) and the capacitance is c1, then Q = c1 · V (C) (4) Substituting equation (4) into equation (3), I · r1 = c1 · V (C) · r1 / t (5) Substituting equation (5) into equation (1), V (A) = power supply voltage It is expressed as + (c1 · r1 / t) · V (C) (6).

Assuming that the time constant in the series circuit of the resistor R1 and the capacitor C1 is τ, τ is expressed as τ = c1 · r1 (7). Substituting equation (7) into equation (6) gives V (A) = power supply voltage + (τ / t) · V (C) (8). From the equation (8), if the period t of the oscillator 1 in the booster circuit 20 is sufficiently smaller than the time constant τ, the potential V (A) is boosted. In this embodiment, the oscillation cycle t = 1.43 μ
Using the resistance value r1 of the resistor R1 = 50 kΩ and the capacitance c1 = 60 pF of the capacitor C1 for sec, the boosting operation was performed without any trouble.

Next, the operation will be described. In the surge input detection circuit 10, when it is determined that a surge voltage equal to or higher than the maximum rated power supply voltage is input to the power supply terminal VDD and a detection signal is output, this detection signal turns on the M0S transistor Tr3, and thus the M0S transistor Tr3 is turned on.
2 is off. This protects the booster circuit 20 from the surge voltage.

In the booster circuit 20, from the power supply terminal VDD to M
The electric charge supplied to the capacitor C1 via the 0S transistor Tr2 and the diode D2 is continuously sent out in one direction by the oscillator 1 via the diode D3, so that the gate potential of the M0S transistor Tr1 and the M0S transistor Tr1 are increased.
The gate potential of the transistor Tr2 is boosted. M0
Also for the S transistor Tr2, the M0S transistor T
Since the high potential boosted by the booster circuit 2 is applied similarly to r1, the voltage drop corresponding to the threshold value of the M0S transistor Tr2 is reduced. M0S transistor Tr2
Is manufactured in the same step as the M0S transistor Tr1 at the time of manufacturing, the thickness of the gate oxide film of the M0S transistor Tr2 is the same as the thickness of the gate oxide film of the M0S transistor Tr1. It is not destroyed even when a voltage is applied. The booster circuit 20 is supplied with a voltage almost equal to the power supply voltage. The voltage boosted by the booster circuit 20 is applied to the gate of the M0S transistor Tr1.

As a result, the power supply terminal VDD and the booster circuit 20
The voltage drop corresponding to the threshold value in the M0S transistor Tr2 installed between the two is reduced, and the voltage supplied to the booster circuit 20 is increased to a value close to the power supply voltage. As a result, the voltage efficiently boosted with respect to the power supply voltage can be supplied to the M0S transistor Tr1 for the high side switch. Further, since one boosting circuit 20 boosts the gate potential of the M0S transistor Tr1 and the gate potential of the M0S transistor Tr2, it is not necessary to provide another boosting circuit.

Since this embodiment is constructed as described above, the surge voltage protection function is maintained and the ON resistance of the M0S transistor for the high side switch is reduced without increasing the circuit to reduce power loss. Can be reduced.

Next, FIG. 2 shows a second embodiment of the present invention.
M0S transistor Tr1, Zener diode ZD1,
The booster circuit 20, the M0S transistor Tr2, the resistor R1, and the surge detection circuit 10 are configured and operate in the same manner as in the first embodiment. Here, in the present embodiment, the boosted output of the booster circuit 20 is taken out from before the diode D3, and M0
It is fed back to the gate of the S transistor Tr2 via the diode 1.

By extracting the boosted output from the front side of the diode D3, the boosted output applied to the gate of the M0S transistor Tr2 can be increased by the amount of the forward voltage drop of the diode D3, and the threshold of the M0S transistor Tr2 can be increased. The voltage drop corresponding to the value can be reduced. This is particularly effective when the forward voltage drop in the diode D3 is large.

As a result, the power supply terminal VDD and the booster circuit 20
The voltage drop corresponding to the threshold value in the M0S transistor Tr2 installed between the two is increased, the voltage supplied to the booster circuit 20 is increased to a value close to the power supply voltage, and the voltage efficiently boosted with respect to the power supply voltage. Can be supplied to the MOS transistor Tr1 for the high side switch.

Since this embodiment is configured as described above, it is possible to maintain the surge voltage protection function, reduce the ON resistance of the M0S transistor for the high side switch, and reduce the power loss.

Next, FIG. 3 shows a third embodiment of the present invention.
M0S transistor Tr4 and M0S transistor T
r5 is a surge protection M0S transistor connected in series with a common gate. Other configurations and operations are the same as those in the first embodiment. The boosted voltage can be taken out from before the diode D3 as in the second embodiment. Since the drain-source breakdown voltage of the M0S transistor is increased by connecting in series, even when the surge voltage is high, the M0S transistors Tr4 and M4
The 0S transistor Tr5 is not destroyed.

[0027]

As described above, according to the present invention, in the high side switch circuit including the first M0S transistor for the high side switch and the surge input detecting means for detecting the surge voltage higher than the maximum rated power supply voltage, the boosting means is provided. By feeding back the voltage boosted by the above to the gate of the second M0S transistor for surge voltage protection which is equal to or higher than the maximum rated power supply voltage, the voltage drop in the second M0S transistor is reduced and the voltage supplied to the boosting means. Is increased to a value close to the power supply voltage. As a result, the voltage efficiently boosted with respect to the power supply voltage can be supplied to the first M0S transistor. Further, since one boosting means boosts the gate potential of the first M0S transistor and the gate potential of the second M0S transistor, it is not necessary to provide another boosting means. This makes it possible to maintain the surge voltage protection function, reduce the on-resistance of the M0S transistor for the high-side switch, and reduce the power loss without increasing the number of circuits.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment.

FIG. 3 is a diagram showing a third embodiment.

FIG. 4 is a diagram showing a conventional high side switch circuit.

[Explanation of symbols]

1, 2 Oscillator 3 Comparator 4 Reference voltage circuit 10 Surge input detection circuit 20, 21 Booster circuit C1, C2 Capacitors D1, D2, D3, D4, D5 Diodes R1, R2, R3, R4 Resistors Tr1, Tr2, Tr3, Tr4 , Tr5 M0S transistor ZD1, ZD6 Zener diode VDD Power supply terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Claison Tronnamchai 2 Takaracho, Kanagawa-ku, Yokohama, Kanagawa Nissan Motor Co., Ltd.

Claims (5)

[Claims] 1. A first M0S transistor for a high-side switch, boosting means for supplying a gate voltage obtained by boosting the power supply voltage to the first M0S transistor, and surge for detecting a surge voltage higher than a maximum rated power supply voltage. A second M provided between the input detection means and the boosting means and the power supply terminal and turned off based on the output of the surge input detection means.
In a high-side switch circuit including an OS transistor, a resistor is provided between the gate of the second MOS transistor and a power supply terminal, and the second MO transistor is provided.
A third MO is provided between the gate of the S transistor and the ground.
An S transistor is provided, and the voltage boosted by the boosting means is fed back to the gate of the second MOS transistor via the first diode, and the third M
The output of the surge input detection means is connected to the gate of the OS transistor, and the second MOS transistor is turned off by turning on the third MOS transistor. Switch circuit. 2. The high-side switch circuit according to claim 1, wherein the second M0S transistor is manufactured in the same process as the first M0S transistor. 3. The boosting means includes an oscillator, a capacitor, a second diode provided in a line for transferring charge from the power supply terminal to the capacitor, and a charge from the capacitor to a gate of the first M0S transistor. And a third diode provided on a line for transferring the voltage, the voltage boosted by the voltage boosting means is taken out after the third diode, and the second M0S transistor is output via the first diode. 3. The high side switch circuit according to claim 1, wherein the high side switch circuit is fed back to the gate of. 4. The boosting means includes an oscillator, a capacitor, a second diode provided in a line for transferring charge from the power supply terminal to the capacitor, and a charge from the capacitor to the gate of the first M0S transistor. And a third diode provided in a line for transferring the voltage, the voltage boosted by the voltage boosting means is taken out before the third diode, and the second M0S transistor is passed through the first diode. 3. The high side switch circuit according to claim 1, wherein the high side switch circuit is fed back to the gate of. 5. The second M0S transistor is formed by two M0S transistors connected in series with a common gate.
Alternatively, the high side switch circuit described in 4.