JPH0878849A - Ceramic multilayered circuit board and its manufacture - Google Patents
Ceramic multilayered circuit board and its manufactureInfo
- Publication number
- JPH0878849A JPH0878849A JP6210974A JP21097494A JPH0878849A JP H0878849 A JPH0878849 A JP H0878849A JP 6210974 A JP6210974 A JP 6210974A JP 21097494 A JP21097494 A JP 21097494A JP H0878849 A JPH0878849 A JP H0878849A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- circuit board
- insulating layer
- substrate
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高密度にチップを実装
するに好適なセラミック多層回路基板およびその製法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multilayer circuit board suitable for mounting chips at high density and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、ハイブリッドＩＣ等の半導体実装
用の基板には、高密度化の要求から基板内部に配線パタ
ーンを持つセラミック多層回路基板が用いられてきた。
この種の多層回路基板は、例えば図９に示す工程を有す
る製法により作製される。すなわち、まず、複数のグリ
ーンシートそれぞれに形成されたビアホールに導体ペー
ストを充填する（ビアフィル）。次に、各グリーンシー
ト上に所定の配線回路すなわち導体パターンをスクリー
ン印刷する。その後、これらグリーンシートを乾燥→積
層→脱脂→焼成の各工程で処理することによって、グリ
ーンシートが焼成されてなる絶縁層の内部に多層にわた
って回路が形成された多層回路基板を作製する。セラミ
ック多層回路基板は配線材料により次の２つに分類する
ことができる。高温焼成多層回路基板と低温焼成多層回
路基板である。多層回路基板の絶縁層は、その内部の配
線と同時に焼成されるため、配線材料により限定され
る。高温焼成多層回路基板は、１３００℃以上と高い融
点をもつＷやＭｏ等からなる配線を有し、絶縁層材料が
主にアルミナ、ムライト、ＡｌＮ等からなる基板であ
る。ＷやＭｏは配線抵抗が高いという欠点を有するた
め、「機能性セラミックス」（社団法人 日本ファイン
セラミック協会出版）７２〜８４頁に記載されているよ
うに、配線抵抗の低いＡｇやＣｕを配線材料とした低温
焼成多層回路基板の開発が盛んになった。特に、配線が
Ａｇ系材料であるセラミック多層回路基板は大気中で焼
成可能であるので作製が容易である。したがって、上記
「機能性セラミックス」７２〜８４頁に示されるように
Ａｇ系低温焼成多層回路基板は最も好ましいシステムと
言える。2. Description of the Related Art In recent years, as a substrate for mounting a semiconductor such as a hybrid IC, a ceramic multilayer circuit substrate having a wiring pattern inside the substrate has been used because of the demand for higher density.
This type of multilayer circuit board is manufactured by a manufacturing method including the steps shown in FIG. 9, for example. That is, first, the conductive paste is filled in the via holes formed in each of the plurality of green sheets (via fill). Next, a predetermined wiring circuit, that is, a conductor pattern is screen-printed on each green sheet. After that, these green sheets are processed in the steps of drying → lamination → degreasing → firing to produce a multilayer circuit board in which circuits are formed in multiple layers inside the insulating layer formed by firing the green sheets. Ceramic multilayer circuit boards can be classified into the following two types depending on the wiring material. These are a high temperature baked multilayer circuit board and a low temperature baked multilayer circuit board. The insulating layer of the multi-layer circuit board is fired at the same time as the wiring inside, so that it is limited by the wiring material. The high temperature fired multilayer circuit board is a board having wirings made of W or Mo having a high melting point of 1300 ° C. or higher, and an insulating layer material mainly made of alumina, mullite, AlN or the like. Since W and Mo have the drawback of having a high wiring resistance, as described in "Functional Ceramics" (published by Japan Fine Ceramic Society), pages 72 to 84, Ag and Cu having a low wiring resistance are used as wiring materials. The development of low-temperature fired multilayer circuit boards became popular. In particular, a ceramic multi-layer circuit board whose wiring is an Ag-based material can be fired in the atmosphere, so that it is easy to manufacture. Therefore, it can be said that the Ag-based low temperature firing multilayer circuit board is the most preferable system as shown in "Functional Ceramics" on pages 72 to 84.
【０００３】ところで、より高密度化を実現するには、
ベアチップの基板への搭載が重要となる。ベアチップと
基板の回路とを接続する手段としてはワイヤボンディン
グによる接続が好ましく、良好なワイヤボンディングを
実現するには基板上に形成されたＡｕ，Ｐｔ，Ａｌ，も
しくはＣｕパッドが必要となる。さらに低コスト化のた
めにはパッドを厚膜で形成することが好ましい。By the way, in order to achieve higher density,
It is important to mount the bare chip on the substrate. As a means for connecting the bare chip and the circuit on the substrate, connection by wire bonding is preferable, and Au, Pt, Al, or Cu pads formed on the substrate are required to realize good wire bonding. Further, in order to reduce the cost, it is preferable to form the pad with a thick film.
【０００４】[0004]
【発明が解決しようとする課題】しかし、Ａｇ系低温焼
成多層回路基板ではＡｕ，Ｐｔ，Ａｌ，もしくはＣｕパ
ッドを厚膜で形成しようとすると絶縁層中に気泡が発生
し、回路基板として機能しなくなる。以下にそのメカニ
ズムについて説明する。ワイヤボンディング用のパッド
は、Ａｇの内層配線を有する基板上にペーストを印刷、
焼成することにより作製される。一般的に、Ａｇ系のセ
ラミック多層回路基板の絶縁層にはガラスが用いられ
る。パッドが存在しない時、焼成中、絶縁層内部の配線
からガラス中にＡｇが溶解し、Ａｇ0とＡｇイオンが平
衡を保って存在している。この時、例えばＡｕが存在す
ると、Ａｇ0がＡｕに固溶することによりＡｇ0とＡｇイ
オンの平衡が崩れる。そこで、平衡状態に戻すためにガ
ラスが還元され、酸素が発生する。この結果、絶縁層中
に酸素の気泡が生じ、基板として機能しなくなってしま
う。これは、パッドがＰｔ，Ｃｕ，Ａｌからなる時も同
様である。However, when an Au, Pt, Al, or Cu pad is formed as a thick film in an Ag-based low-temperature fired multilayer circuit board, bubbles are generated in the insulating layer and the circuit board functions as a circuit board. Disappear. The mechanism will be described below. For the wire bonding pad, paste is printed on the substrate having Ag inner layer wiring,
It is produced by firing. Generally, glass is used for an insulating layer of an Ag-based ceramic multilayer circuit board. When the pad is not present, Ag is dissolved from the wiring inside the insulating layer into the glass during firing, and Ag 0 and Ag ions are present in equilibrium. At this time, for example, when Au is present, Ag 0 is dissolved in Au as a solid solution, and the equilibrium between Ag 0 and Ag ions is broken. Then, the glass is reduced to generate equilibrium and oxygen is generated. As a result, oxygen bubbles are generated in the insulating layer, and the substrate does not function as a substrate. This is the same when the pad is made of Pt, Cu, Al.
【０００５】従来技術による上記課題の解決は困難であ
った。例えば、絶縁層をＡｇの拡散係数の小さな材質に
することにより解決しようとしたとする。確かに、絶縁
層のＡｇの拡散係数が小さければ、パッドに固溶するＡ
ｇの量を抑えることができ、反応を抑制できる。しか
し、セラミック多層回路基板では、絶縁層は焼結により
緻密化される。焼結は拡散により進行するので、拡散係
数が小さいと焼結温度が高くなる。Ａｇ配線は絶縁層内
部に存在するために、絶縁層を焼成するときは必ずその
雰囲気に曝される。したがって、Ａｇの拡散を防止でき
るような材質の絶縁層の焼結温度では、Ａｇ配線が過焼
結もしくは融解してしまい、断線などが生じ、信頼性が
著しく低下する。したがって、従来技術では容易にこの
課題を解決することはできなかった。It has been difficult to solve the above-mentioned problems by the prior art. For example, assume that the problem is solved by using a material having a small Ag diffusion coefficient for the insulating layer. Certainly, if the diffusion coefficient of Ag in the insulating layer is small, A
The amount of g can be suppressed and the reaction can be suppressed. However, in the ceramic multilayer circuit board, the insulating layer is densified by sintering. Since sintering proceeds by diffusion, if the diffusion coefficient is small, the sintering temperature will be high. Since the Ag wiring exists inside the insulating layer, it is always exposed to the atmosphere when the insulating layer is fired. Therefore, at the sintering temperature of the insulating layer made of a material capable of preventing the diffusion of Ag, the Ag wiring is over-sintered or melted, causing disconnection or the like, resulting in a significant decrease in reliability. Therefore, the conventional technique could not easily solve this problem.
【０００６】本発明はこうした問題点を解決して、Ａｇ
系配線回路を内部に有する絶縁層をガラスで構成しなが
ら、Ａｕ、Ｐｔ、Ｃｕ、Ａｌからなる、ワイヤボンディ
ング用パッドを有するセラミック多層回路基板及びその
製法を提供することを目的とする。The present invention solves these problems and provides Ag
An object of the present invention is to provide a ceramic multilayer circuit board having a wire bonding pad made of Au, Pt, Cu, and Al, and a method for manufacturing the same, while an insulating layer having a system wiring circuit inside is made of glass.
【０００７】[0007]
【課題を解決するための手段】本発明は大きく分類して
次の２つの柱からなる。絶縁層の内層配線を構成する
Ａｇが絶縁層表面のパッドにまで拡散することを阻止す
るためにバリア層を設ける。このバリア層を薄くす
る。The present invention is roughly classified into the following two pillars. A barrier layer is provided to prevent Ag constituting the inner wiring of the insulating layer from diffusing to the pad on the surface of the insulating layer. Thin this barrier layer.
【０００８】まず、について述べる。本発明の特徴
は、前もって焼結した高融点のセラミック板をバリア層
とし、このセラミックス板上にパッドを形成することに
より課題を解決する点にある。First, the following will be described. A feature of the present invention is to solve the problem by forming a high melting point ceramic plate that has been sintered in advance as a barrier layer and forming a pad on the ceramic plate.
【０００９】本発明の第１の多層回路基板は、基板内に
Ａｇ系導体からなる回路が多層状に形成され、基板上面
には該基板に搭載されるチップと結線されるＡｕ，Ｐ
ｔ，ＣｕもしくはＡｌからなるパッドが形成されたセラ
ミック多層回路基板であって、回路が形成された基板部
分は、融点もしくは軟化点が５２５〜８００℃であるガ
ラス層からなり、パッドが形成された基板部分は、融点
もしくは軟化点が１２００℃以上である高融点セラミッ
ク絶縁層からなることを特徴とする。そして、パッドが
形成された基板部分を構成する高融点セラミック絶縁層
は、回路が内部に形成されたガラス層上全面をおおう一
枚板で構成する、あるいは、ガラス層上に２つ以上に分
割し、この分割された高融点セラミック絶縁層上に１つ
以上のパッドを有するものとする。According to the first multilayer circuit board of the present invention, a circuit composed of Ag-based conductors is formed in a multilayer shape in the board, and Au, P connected to a chip mounted on the board is connected to the upper surface of the board.
A ceramic multi-layer circuit board having pads formed of t, Cu or Al, in which a board portion is made of a glass layer having a melting point or a softening point of 525 to 800 ° C., and pads are formed. The substrate portion is characterized by being made of a high melting point ceramic insulating layer having a melting point or a softening point of 1200 ° C. or higher. The high-melting-point ceramic insulating layer that constitutes the substrate portion on which the pad is formed is formed of a single plate that covers the entire surface of the glass layer in which the circuit is formed, or is divided into two or more on the glass layer. However, one or more pads are provided on the divided high melting point ceramic insulating layer.
【００１０】本発明の別の多層回路基板は、上記本発明
の多層回路基板におけるように、パッドが形成された基
板部分を構成する高融点セラミック絶縁層を、回路が形
成されたガラス層上全面をおおう一枚板で構成するとと
もに、この低融点セラミック絶縁層の中に、融点もしく
は軟化点が１２００℃以上のもう一つの高融点セラミッ
ク絶縁層を一層含めたことを特徴とする。そしてガラス
層に含む高融点セラミック絶縁層を、ガラス層の最下部
を占めるように配置する、あるいはガラス層の厚さ方向
の中央部を占めるように配置するのがよい。Another multilayer circuit board of the present invention is the same as the above-mentioned multilayer circuit board of the present invention, in which the high melting point ceramic insulating layer forming the board portion having the pad is entirely covered on the glass layer having the circuit formed thereon. The low melting point ceramic insulating layer further includes another high melting point ceramic insulating layer having a melting point or a softening point of 1200 ° C. or higher. The high melting point ceramic insulating layer included in the glass layer is preferably arranged so as to occupy the lowermost portion of the glass layer or occupy the central portion in the thickness direction of the glass layer.
【００１１】また、本発明のまた別の多層回路基板は、
基板内にＡｇ系導体からなる回路が多層状に形成され、
基板上面にはこの搭載されるチップと結線されるＡｕ，
Ｐｔ，ＣｕもしくはＡｌからなるパッドが形成されたセ
ラミック多層回路基板であって、パッドが表側に形成さ
れた基板部分は、融点もしくは軟化点が１２００℃以上
である高融点セラミック絶縁層からなり、回路が形成さ
れた基板部分は、融点もしくは軟化点が５２５〜８００
℃であるガラス層からなり、かつ回路が形成された基板
部分の層の半分が高融点セラミック絶縁層の裏側に、残
りの半分がパッドの位置に対応して該パッドを入れる穴
を設けて高融点セラミック絶縁層の表側に設けられたこ
とを特徴とする。Another multilayer circuit board of the present invention is
Circuits made of Ag-based conductors are formed in multiple layers in the substrate,
Au connected to the chip to be mounted on the upper surface of the substrate,
A ceramic multi-layer circuit board having pads formed of Pt, Cu, or Al, wherein the board portion having the pads formed on the front side is formed of a high-melting-point ceramic insulating layer having a melting point or a softening point of 1200 ° C. or higher. The substrate portion on which is formed has a melting point or softening point of 525 to 800.
Half of the substrate layer on which the circuit is formed, which consists of a glass layer at a temperature of ℃, is provided on the back side of the high melting point ceramic insulating layer, and the other half is provided with a hole for inserting the pad corresponding to the position of the pad. The melting point ceramic insulating layer is provided on the front side.
【００１２】本発明の多層回路基板の製法は、基板内に
Ａｇ系導体からなる回路が多層状に形成され、基板上面
には該基板に搭載されるチップと結線されるＡｕ，Ｐ
ｔ，ＣｕもしくはＡｌからなるパッドが形成されたセラ
ミック多層回路基板の製法であって、(1)焼結済みで１
２００℃以上の融点もしくは軟化点を有する高融点絶縁
板にビアホールを形成し、(2)このビアホールにＡｇペ
ーストを充填し、(3)次いで高融点絶縁板の一方の面に
ビアホール中のＡｇペーストと接続して、パッドとなる
べきＡｕ，Ｐｔ，ＣｕもしくはＡｌのペーストの膜を形
成する一方、(4)焼成により融点もしくは軟化点が５２
５〜８００℃のガラス層となる複数のグリーンシートそ
れぞれにビアホールを形成し、(5)各グリーンシートの
ビアホールにＡｇペーストを充填し、(6)各グリーンシ
ート上にＡｇペーストにより配線回路パターンを印刷
し、(7)この印刷したグリーンシートを積層し、さらに
このグリーンシートの積層体と、パッドとなるべきペー
ストの膜を形成した高融点絶縁板とを組合せ、(8)脱脂
した後に(9)ガラス層の融点で焼成することを特徴とす
る。According to the method for manufacturing a multilayer circuit board of the present invention, a circuit composed of Ag-based conductors is formed in a multilayer shape in the board, and Au, P connected to a chip mounted on the board is connected to the upper surface of the board.
A method for manufacturing a ceramic multi-layer circuit board on which pads made of t, Cu, or Al are formed.
A via hole is formed in a high melting point insulating plate having a melting point or a softening point of 200 ° C. or higher, (2) this via hole is filled with Ag paste, and (3) then one side of the high melting point insulating plate is filled with Ag paste in the via hole. While forming a paste film of Au, Pt, Cu or Al to be a pad, the melting point or softening point is 52 by baking (4).
A via hole is formed in each of a plurality of green sheets forming a glass layer of 5 to 800 ° C., (5) the via hole of each green sheet is filled with Ag paste, and (6) a wiring circuit pattern is formed on each green sheet with Ag paste. After printing, (7) stacking the printed green sheets, and further combining the stacked body of the green sheets and a high melting point insulating plate on which a paste film to be a pad is formed, (8) after degreasing (9 ) It is characterized by firing at the melting point of the glass layer.
【００１３】次に、について述べる。製法によって
は、焼成中にガラス絶縁層が焼結収縮し、バリア層であ
ると焼結済の高融点絶縁板に曲げ応力がかかることがあ
る。バリア層を薄くすると、バリア層がガラス絶縁層の
焼結収縮により発生する曲げ応力に耐え切れなくなる。
はバリア層を薄くできないという課題を、曲げ応力を
圧縮応力に変換することにより解決しようとする手段で
ある。より具体的には次の手段により課題を解決でき
る。Next, the following will be described. Depending on the manufacturing method, the glass insulating layer may sinter and shrink during firing, and the barrier layer may cause bending stress on the sintered high melting point insulating plate. When the barrier layer is made thin, the barrier layer cannot withstand the bending stress generated by the sintering shrinkage of the glass insulating layer.
Is a means for solving the problem that the barrier layer cannot be thinned by converting bending stress into compressive stress. More specifically, the problem can be solved by the following means.
【００１４】多層回路基板の表側全面にパッドが形成さ
れた一つの高融点セラミック絶縁層を設けるとともに、
裏面全面にもう一つの高融点セラミック絶縁層を設け
る。または、多層回路基板の表側全面にパッドが形成さ
れた一つの高融点セラミック絶縁層を設けるとともに、
多層回路が形成された低融点セラミック絶縁層の中に、
望ましくはこの低融点セラミック絶縁層の厚さ方向の中
央部を占めるようにもう一つの高融点セラミック絶縁層
を設ける。In addition to providing one high melting point ceramic insulating layer having pads formed on the entire front surface of the multilayer circuit board,
Another high melting point ceramic insulating layer is provided on the entire back surface. Or, while providing one high melting point ceramic insulating layer with pads formed on the entire front surface of the multilayer circuit board,
In the low melting point ceramic insulating layer where the multilayer circuit is formed,
Desirably, another high melting point ceramic insulating layer is provided so as to occupy the central portion in the thickness direction of the low melting point ceramic insulating layer.
【００１５】その他、多層回路基板を、パッドが表側に
形成された高融点セラミック絶縁層の裏側に回路が形成
された基板部分の層の半分を、残りの半分をパッドの位
置に対応して該パッドを入れる穴を設けて高融点セラミ
ック絶縁層の表側に設ける。In addition, a multi-layered circuit board is constructed such that half of the layers of the board portion on which the circuit is formed on the back side of the high melting point ceramic insulating layer on which the pads are formed on the front side, and the other half corresponding to the position of the pad. A hole for inserting a pad is provided on the front side of the high melting point ceramic insulating layer.
【００１６】但し、このように低融点セラミック絶縁層
の厚さ方向の中央部に高融点セラミック絶縁層を設ける
場合、バリア層となる高融点セラミック絶縁層の強度に
よっても多少異なるものの、低融点セラミック絶縁層の
厚さ方向の中心からバリア層の厚さ程度のずれは許容さ
れることが経験的にわかっている。さらに、上記の手段
により作製したセラミック多層回路基板のパッドへ直接
ワイヤボンディングすることが可能であり、ベアチップ
を搭載したマルチチップモジュールを作製できる。However, when the high melting point ceramic insulating layer is provided at the central portion in the thickness direction of the low melting point ceramic insulating layer as described above, the low melting point ceramic insulating layer is somewhat different depending on the strength of the high melting point ceramic insulating layer. It has been empirically known that a deviation of the thickness of the barrier layer from the center of the insulating layer in the thickness direction is allowed. Furthermore, it is possible to wire-bond directly to the pads of the ceramic multilayer circuit board manufactured by the above means, and it is possible to manufacture a multi-chip module on which a bare chip is mounted.
【００１７】[0017]
【作用】本発明は大きく分類して次の２つの柱からな
る。バリア層の形成手段。バリア層の薄化の手段。
まず、の作用効果について説明する。本発明のポイン
トは、バリア層を融点・もしくは軟化点が１２００℃以
上である焼結済みのセラミックとし、この焼結済みセラ
ミックス上にパッドを形成する点にある。The present invention is roughly classified into the following two pillars. Barrier layer forming means. Means for thinning the barrier layer.
First, the function and effect of will be described. The point of the present invention is that the barrier layer is a sintered ceramic having a melting point / softening point of 1200 ° C. or higher, and a pad is formed on the sintered ceramic.
【００１８】まず、融点もしくは軟化点が１２００℃で
あることの作用効果について述べる。パッドへのＡｇの
固溶を防ぐには基板内部の配線回路と基板表面のパッド
間にバリア層を設け、配線を構成するＡｇのパッドへの
拡散を防止すれば良い。バリア層が機能するにはＡｇの
拡散係数が小さければ良い。拡散係数はバリア層の融点
もしくは軟化点と相関がある。具体的には、Ａｇの拡散
係数を十分小さくするにはバリア層の融点もしくは軟化
点を１２００℃以上とすることが好ましい。例えば、バ
リア層の材料としてはアルミナ、ＡｌＮ，ＳｉＣ，ムラ
イト等を利用できる。First, the function and effect of the melting point or softening point of 1200 ° C. will be described. In order to prevent Ag from forming a solid solution in the pad, a barrier layer may be provided between the wiring circuit inside the substrate and the pad on the surface of the substrate to prevent Ag constituting the wiring from diffusing into the pad. For the barrier layer to function, it is sufficient if the diffusion coefficient of Ag is small. The diffusion coefficient correlates with the melting point or softening point of the barrier layer. Specifically, the melting point or softening point of the barrier layer is preferably 1200 ° C. or higher in order to sufficiently reduce the diffusion coefficient of Ag. For example, alumina, AlN, SiC, mullite or the like can be used as the material of the barrier layer.
【００１９】次に、バリア層を焼結済みのセラミック板
としたことによる作用効果を説明する。基板は配線にＡ
ｇを使用しているので９００℃以上の高温に曝すことは
できない。融点１２００℃以上の物質を９００℃以下の
温度で緻密化させるのは困難である。したがって、未焼
結のバリア層を絶縁層と接着した後に焼成したのでは、
バリア層を緻密化することができない。ガラス絶縁層へ
の積層前にバリア層を焼結することにより、バリア層が
緻密となり、Ａｇの拡散速度が小さいことと合わせて、
Ａｇのパッドへの拡散を防止できる。Next, the function and effect of using the sintered ceramic plate as the barrier layer will be described. The board is A for wiring
Since g is used, it cannot be exposed to a high temperature of 900 ° C. or higher. It is difficult to densify a substance having a melting point of 1200 ° C. or higher at a temperature of 900 ° C. or lower. Therefore, if the unsintered barrier layer is fired after being bonded to the insulating layer,
The barrier layer cannot be densified. By sintering the barrier layer before stacking it on the glass insulating layer, the barrier layer becomes dense and the Ag diffusion rate is low,
It is possible to prevent Ag from diffusing into the pad.
【００２０】次に、バリア層とパッドの間に他の絶縁層
を挾まず、バリア層上に直接パッドを形成することの作
用効果について説明する。パッドは基板配線と電気的に
接続されなければならない。したがって、パッド・バリ
ア間に絶縁層が存在する場合、この絶縁層中にも配線が
必要となる。しかし、配線に原料及び製造コストの安い
Ａｇ配線が使用できないため大幅なコストアップとな
る。したがって、バリア層上に直接パッドを形成するこ
とが好ましい。Next, the function and effect of forming the pad directly on the barrier layer without sandwiching another insulating layer between the barrier layer and the pad will be described. The pad must be electrically connected to the board wiring. Therefore, if an insulating layer exists between the pads and barriers, wiring is also required in this insulating layer. However, Ag wiring, which is low in raw material and manufacturing cost, cannot be used for wiring, resulting in a significant increase in cost. Therefore, it is preferable to form the pad directly on the barrier layer.
【００２１】但し、パッドごとにバリア層を形成する
と、パッド位置にパッドを配置するプロセス他回路
とパッドの電気的接続の確保等、プロセスが複雑化して
しまう。複数のパッドのバリア層を一枚の焼結済みセラ
ミックスで兼用することによりプロセス工程を低減する
ことができる。更に、バリア層と絶縁層はしっかり接着
することが重要である。一般的に接着強度は接着面積に
比例する。したがって、絶縁層片面の全面を１枚のバリ
ア層で覆うことが最も好ましい。However, if the barrier layer is formed for each pad, the process becomes complicated, such as the process of arranging the pad at the pad position and the electrical connection between the circuit and the pad. By using one sintered ceramics for the barrier layers of a plurality of pads, the process steps can be reduced. Furthermore, it is important that the barrier layer and the insulating layer are firmly adhered. Generally, the adhesive strength is proportional to the adhesive area. Therefore, it is most preferable to cover the entire one surface of the insulating layer with one barrier layer.
【００２２】ガラス絶縁層とバリア層すなわち焼結済み
セラミックの接着は、次の手段により行うことができ
る。まず、ガラス絶縁層を焼結させる。その後、焼結済
みセラミックスであるバリア層を積層し、加圧しながら
焼成することによりガラス絶縁層とバリア層を接着する
ことができる。他に公知の技術である製法：ア）焼結済
みセラミックに未焼成絶縁層用グリーンシートを圧着
し、その後焼成する、イ）焼結済みセラミックに絶縁層
用ペーストをスクリーン印刷し、その後焼成する、等に
よっても可能である。但し、公知の技術ア）イ）では、
焼成中ガラス絶縁層が焼結することにより、バリア層に
曲げ応力がかかる。The adhesion of the glass insulating layer and the barrier layer, that is, the sintered ceramic can be performed by the following means. First, the glass insulating layer is sintered. After that, the glass insulating layer and the barrier layer can be bonded to each other by laminating a barrier layer which is a sintered ceramics and firing it while applying pressure. Another known technique: a) Sintering ceramics is pressed with a green sheet for an unsintered insulating layer and then fired. B) Screen-printing an insulating layer paste on the sintered ceramics and then firing. , Etc. are also possible. However, in the known technology a) b),
Bending stress is applied to the barrier layer by sintering the glass insulating layer during firing.
【００２３】したがって、公知の技術ア）イ）により本
発明を実現するには、ガラス絶縁層の焼結時に生じる曲
げ応力に耐えられるようバリア層を厚くしなければなら
ない。しかし、世の中のニーズは軽少短薄化の傾向にあ
り、バリア層を厚くすることは好ましくない。そこで、
「課題を解決するための手段」に述べたの手段が重要
となる。バリア層は圧縮応力には強いが曲げ応力に極め
て弱い。はその曲げ応力を回避し、圧縮応力とするた
めの手段である。本発明は、高融点セラミック絶縁層を
多層回路基板の厚さ方向中心の平面に関して対称に配置
した点に特徴がある。例えば多層回路基板の上面にのみ
バリア層である高融点セラミック絶縁層を設けた場合、
この高融点セラミック絶縁層を薄くすると絶縁の収縮に
より曲げ応力がかかり基板が破断してしまう。しかし、
多層回路基板の表側全面に一つの高融点セラミック絶縁
層を設けるとともに、裏面全面にもう一つの高融点セラ
ミック絶縁層を設ければ、焼成中に生ずる絶縁層の収縮
による曲げ応力の総和は小さくなりバリア層を薄くする
ことが可能である。バリア層は圧縮応力には強いので薄
くすることが可能である（後述の図７参照）。また多層
回路基板の表側全面一つの高融点セラミック絶縁層を設
けるとともに、多層回路が形成された低融点セラミック
絶縁層の中にもう一つの高融点セラミック絶縁層を設け
れば、アルミナ板１を余分に形成することにより更に強
度を高くすることができる（後述の図８参照）。さらに
高融点セラミック絶縁層を中心になるように高融点セラ
ミック絶縁層の表裏に、それぞれに回路が形成された基
板部分の層の半分づつ設ければ、バリア層層両側にの絶
縁層の収縮による応力は上下で釣合い、バリア層に圧縮
応力が加わるものの曲げ応力は無視できる（後述の図６
参照）。Therefore, in order to realize the present invention by the known techniques a) a), the barrier layer must be thick enough to withstand the bending stress generated during the sintering of the glass insulating layer. However, the needs of the world tend to be small, short and thin, and it is not preferable to thicken the barrier layer. Therefore,
The measures described in "Means for solving problems" are important. The barrier layer is strong against compressive stress but extremely weak against bending stress. Is a means for avoiding the bending stress and making it a compressive stress. The present invention is characterized in that the high melting point ceramic insulating layers are arranged symmetrically with respect to the plane of the center of the multilayer circuit board in the thickness direction. For example, when a high melting point ceramic insulating layer that is a barrier layer is provided only on the upper surface of the multilayer circuit board,
If this high melting point ceramic insulating layer is made thin, bending stress is applied due to contraction of the insulation, and the substrate is broken. But,
If one high-melting-point ceramic insulating layer is provided on the entire front surface of the multilayer circuit board and another high-melting-point ceramic insulating layer is provided on the entire back surface, the total bending stress due to shrinkage of the insulating layer generated during firing becomes small. It is possible to make the barrier layer thin. Since the barrier layer is strong against compressive stress, it can be made thin (see FIG. 7 described later). Further, if one high melting point ceramic insulating layer is provided on the entire front surface of the multilayer circuit board and another high melting point ceramic insulating layer is provided in the low melting point ceramic insulating layer having the multilayer circuit, the alumina plate 1 is not used. The strength can be further increased by forming it (see FIG. 8 described later). Further, by providing half of the layers of the substrate portion where the circuit is formed on the front and back of the high-melting point ceramic insulating layer so that the high-melting point ceramic insulating layer is at the center, the insulating layers on both sides of the barrier layer may shrink. The stress balances up and down, and compressive stress is applied to the barrier layer, but bending stress can be ignored (see FIG. 6 described later).
reference).
【００２４】[0024]
【実施例】以下、本発明のセラミック多層回路基板の製
法を実施例によりさらに詳細に説明するが、本発明はこ
れらに限定されない。EXAMPLES The method for producing the ceramic multilayer circuit board of the present invention will be described in more detail below with reference to examples, but the present invention is not limited thereto.
【００２５】〔実施例１〕本実施例を図１および図２を
用いて説明する。図１はチップを実装した多層回路基板
の構成を示す図で図２のI−I断面図、図２は図１の上面
図である。まず、平均粒径２μｍのＡｇ粉末とＢｉ2Ｏ3
粉末の重量比１０対２の混合物に、アクリル樹脂／ブチ
ルカルビトールアセテートからなるビヒクルを適量加
え、３本ロールを用いて室温で混練し、スクリーン印刷
に好適なＡｇ導体ペーストを調整した。またＡｇ導体ペ
ーストと同様な方法でＡｕペーストを作製した。[Embodiment 1] This embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing the structure of a multilayer circuit board on which chips are mounted, and is a sectional view taken along the line II of FIG. 2, and FIG. 2 is a top view of FIG. First, Ag powder having an average particle size of 2 μm and Bi 2 O 3
An appropriate amount of a vehicle composed of acrylic resin / butyl carbitol acetate was added to a mixture having a powder weight ratio of 10: 2, and kneaded at room temperature using a three-roll mill to prepare an Ag conductor paste suitable for screen printing. An Au paste was prepared in the same manner as the Ag conductor paste.
【００２６】次に、硼硅酸鉛ガラスと、フリットとして
のアルミナ粉末にポリビニルブチラール等の有機溶剤を
加えて撹拌し、でいしょう化状態とした。このでいしょ
うをドクターブレードを用いたキャスティング成膜法に
よって１００×１００(ｍｍ)角の未焼成のグリーンシー
トを複数枚形成した。これらグリーンシートは焼成され
てガラスの絶縁層２となる。Next, an organic solvent such as polyvinyl butyral was added to lead borosilicate glass and alumina powder as a frit, and the mixture was agitated to obtain a dimerized state. A plurality of 100 × 100 (mm) square unfired green sheets were formed on this cake by a casting film forming method using a doctor blade. These green sheets are fired to form the glass insulating layer 2.
【００２７】この様にして形成したグリーンシートに垂
直方向にパンチャーを用いて、直径２００μｍの穴（ビ
アホール）を複数個形成し、これらビアホールにビア導
体４となるべくＡｇ導体ペーストを充填した。その後に
各グリーンシート上に、ビアホールに充填したＡｇ導体
ペーストと接続するように、Ａｇ導体ペーストを用いて
スクリーン印刷で配線パターンを形成した。次に配線パ
ターンを形成した複数のグリーンシートを、図１におい
て１点鎖線で示すよう、順次積み重ねた。A plurality of holes (via holes) having a diameter of 200 μm were formed in the green sheet thus formed by using a puncher in the vertical direction, and these via holes were filled with Ag conductor paste so as to become the via conductors 4. After that, a wiring pattern was formed on each green sheet by screen printing using the Ag conductor paste so as to be connected to the Ag conductor paste filled in the via holes. Next, a plurality of green sheets having a wiring pattern formed thereon were sequentially stacked as shown by the chain line in FIG.
【００２８】一方、０．６５ｍｍ厚さ、１１０×１１０
(ｍｍ)角の焼結した高融点セラミック層となるアルミナ
板１にビアホールを形成し、ビア導体４となるべきＡｇ
導体ペーストを充填した。なおアルミナ板１は１６００
℃で焼成した。次に、積み重ねたグリーンシートの最上
面に電気的に接続するようにアルミナ板１を重ね、熱プ
レス機などを用いて温度１２０℃、圧力２００ｋｇ／ｃ
ｍ2の条件で上下面から熱圧着し、積層体を得た。この
積層体のアルミナ板１上に、このアルミナ板１のビアホ
ール中のＡｇ導体ペーストと接続する様に、Ａｕペース
トを用いて一辺が１.５ｍｍの正方形の厚膜をスクリー
ン印刷により形成した。それから、このアルミナ板１を
載せた積層体を空気中、約４００℃で１時間加熱して脱
脂を行った後、８５０℃で１０分間焼成し、かくして多
層のＡｇ厚膜配線５とそれら配線５をつなビア導体４を
絶縁層２内部に有し、Ａｕパッド３を絶縁層２表面に有
する多層回路基板を作製した。焼成の結果、絶縁層２内
に気泡の発生は認められなかった。また、Ａｕパッド３
もめくれ上がることなく形成され、アルミナ板１とパッ
ド３との接着強度は２.２kgfあった。アルミナ板１と絶
縁層２の接着強度は十分大きかった。On the other hand, a thickness of 0.65 mm, 110 × 110
Ag which should be a via conductor 4 by forming a via hole in the alumina plate 1 which becomes a sintered high melting point ceramic layer of (mm) square
Filled with conductor paste. The alumina plate 1 is 1600
Baked at ° C. Next, the alumina plate 1 is stacked on the uppermost surface of the stacked green sheets so as to be electrically connected, and the temperature is 120 ° C. and the pressure is 200 kg / c using a heat press machine or the like.
Thermocompression bonding was performed from the upper and lower surfaces under the condition of m 2 to obtain a laminate. On the alumina plate 1 of this laminate, a square thick film having a side of 1.5 mm was formed by screen printing using Au paste so as to be connected to the Ag conductor paste in the via hole of the alumina plate 1. Then, the laminated body on which the alumina plate 1 is placed is heated in air at about 400 ° C. for 1 hour to be degreased and then baked at 850 ° C. for 10 minutes, and thus the multilayer Ag thick film wiring 5 and those wirings 5 are formed. A multi-layer circuit board having the connecting via conductor 4 inside the insulating layer 2 and the Au pad 3 on the surface of the insulating layer 2 was produced. As a result of firing, generation of bubbles was not recognized in the insulating layer 2. Also, the Au pad 3
It was formed without curling up, and the adhesive strength between the alumina plate 1 and the pad 3 was 2.2 kgf. The adhesive strength between the alumina plate 1 and the insulating layer 2 was sufficiently high.
【００２９】上記のように作製した多層回路基板上のＡ
ｕパッド３とこの基板上に取り付けたチップ６とをＡｕ
線７を用いてワイヤボンディングすることに成功した。
本実施例では、アルミナ板１を用いたが、代わりに融点
が１２００℃以上の他のセラミックス例えば、ＡｌＮ，
ＳｉＣ，ムライト等をバリア層としても良い。A on the multilayer circuit board manufactured as described above
The u pad 3 and the chip 6 mounted on this substrate are Au
The wire bonding was successful using the wire 7.
In this example, the alumina plate 1 was used, but instead, another ceramic having a melting point of 1200 ° C. or higher, such as AlN,
The barrier layer may be made of SiC, mullite, or the like.
【００３０】〔実施例２〕本実施例を図３、図４により
説明する。図３はチップを実装した多層回路基板の構成
を示す図で図４のIII−III縦断面図、図４は図３の上面
図である。実施例１と同様に、Ａｇ粉末、Ｂｉ2Ｏ3粉末
およびアクリル樹脂／ブチルカルビトールアセテートか
らＡｇ導体ペーストを作製し、そしてＡｕペーストも同
様な方法で作製した。また実施例１と同様に硼硅酸鉛ガ
ラス、アルミナ粉末およびポリビニルブチラール等の有
機溶剤から、１００×１００(ｍｍ)角の未焼成のグリー
ンシートを複数枚形成した。[Embodiment 2] This embodiment will be described with reference to FIGS. FIG. 3 is a view showing the structure of a multilayer circuit board on which chips are mounted, which is a vertical sectional view taken along line III-III of FIG. 4, and FIG. Similar to Example 1, an Ag conductor paste was prepared from Ag powder, Bi 2 O 3 powder and acrylic resin / butyl carbitol acetate, and an Au paste was prepared in the same manner. In the same manner as in Example 1, a plurality of unburned green sheets of 100 × 100 (mm) square were formed from lead borosilicate glass, alumina powder, and an organic solvent such as polyvinyl butyral.
【００３１】これらグリーンシートに垂直方向にパンチ
ャーを用いて、直径２００μｍの穴（ビアホール）を複
数個形成し、これらビアホールにビア導体４となるべき
Ａｇ導体ペーストを充填した。その後にグリーンシート
上に、ビアホール中のＡｇ導体ペーストと接続するよう
にＡｇ導体ペーストを用いてスクリーン印刷で配線パタ
ーンを形成した。配線パターンを形成したグリーンシー
トを順次積み重ね、熱プレス機などを用いて温度１２０
℃、圧力２００ｋｇ／ｃｍ2の条件で上下面から熱圧着
し、積層体を得た。A plurality of holes (via holes) having a diameter of 200 μm were formed in these green sheets in the vertical direction by using a puncher, and these via holes were filled with Ag conductor paste to be the via conductors 4. After that, a wiring pattern was formed on the green sheet by screen printing using the Ag conductor paste so as to be connected to the Ag conductor paste in the via hole. Green sheets on which wiring patterns are formed are sequentially stacked, and the temperature is set to 120 by using a heat press machine or the like.
A laminate was obtained by thermocompression bonding from the upper and lower surfaces under the conditions of ° C and a pressure of 200 kg / cm 2 .
【００３２】一方、表面にＡｕパッド３を、側面にＡｇ
系厚膜導体９を形成した、０．６５ｍｍ厚、１．６×
０．８(ｍｍ)角のアルミナ小片８を焼結により作製し
た。次に、このアルミナ小片８を、上記積層体の最上面
に形成されたＡｇ導体ペーストの配線パターン上に、チ
ップマウンターを用いて搭載した。アルミナ小片８を搭
載した積層体を空気中、約４００℃で１時間加熱して脱
脂を行った後、８５０℃で１０分間焼成して、多層回路
基板を作成した。焼成の結果、グリーンシートが焼成さ
れてなる絶縁層２内に気泡の発生は認められなかった。
そしてアルミナ小片８と絶縁層２の接合強度は0.5kgfで
あった。On the other hand, the Au pad 3 is provided on the front surface and the Ag pad 3 is provided on the side surface.
Formed thick system film conductor 9, 0.65 mm thick, 1.6 ×
A small piece of alumina 8 having a corner of 0.8 (mm) was produced by sintering. Next, this alumina small piece 8 was mounted on the wiring pattern of Ag conductor paste formed on the uppermost surface of the above-mentioned laminated body using a chip mounter. The laminated body having the alumina pieces 8 mounted thereon was heated in air at about 400 ° C. for 1 hour for degreasing, and then baked at 850 ° C. for 10 minutes to prepare a multilayer circuit board. As a result of firing, no bubbles were observed in the insulating layer 2 formed by firing the green sheet.
The bonding strength between the alumina piece 8 and the insulating layer 2 was 0.5 kgf.
【００３３】上記のように作製した多層回路基板上のＡ
ｕパッド３とこの基板上に取り付けたチップ６とをＡｕ
線７を用いてワイヤボンディングすることに成功した。
本実施例では、アルミナ製小片８を用いたが、融点が１
２００℃以上の他のセラミックス小片、例えば、Ａｌ
Ｎ，ＳｉＣ，ムライト製のものを用いても良い。A on the multilayer circuit board produced as described above
The u pad 3 and the chip 6 mounted on this substrate are Au
The wire bonding was successful using the wire 7.
In this example, the alumina small piece 8 was used, but the melting point was 1
Other ceramic pieces above 200 ° C, eg Al
You may use the thing made from N, SiC, and mullite.
【００３４】〔実施例３〕本実施例を図５を用いて説明
する。図５はチップを実装した多層回路基板の上面図で
ある。実施例１と同様に、Ａｇ粉末、Ｂｉ2Ｏ3粉末およ
びアクリル樹脂／ブチルカルビトールアセテートからＡ
ｇ導体ペーストを作製し、そしてＡｕペーストも同様な
方法で作製した。また実施例１と同様に硼硅酸鉛ガラ
ス、アルミナ粉末およびポリビニルブチラール等の有機
溶剤から、１００×１００(ｍｍ)角の未焼成のグリーン
シートを複数枚形成した。[Embodiment 3] This embodiment will be described with reference to FIG. FIG. 5 is a top view of a multilayer circuit board on which chips are mounted. As in Example 1, Ag powder, Bi 2 O 3 powder and acrylic resin / butyl carbitol acetate
A g conductor paste was made, and an Au paste was made in a similar manner. In the same manner as in Example 1, a plurality of unburned green sheets of 100 × 100 (mm) square were formed from lead borosilicate glass, alumina powder, and an organic solvent such as polyvinyl butyral.
【００３５】これらグリーンシートに垂直方向にパンチ
ャーを用いて、直径２００μｍのビアホールを複数個形
成し、各ビアホールにビア導体４となるべきＡｇ導体ペ
ーストを充填した。その後にビアホール中のＡｇ導体ペ
ーストと接続するようＡｇ導体ペーストを用いてスクリ
ーン印刷でＡｇ厚膜配線５回路のパターンを形成した。
配線パターンを形成したグリーンシートを順次積み重
ね、熱プレス機などを用いて温度１２０℃、圧力２００
ｋｇ／ｃｍ2の条件で上下面から熱圧着し、積層体を得
た。A plurality of via holes having a diameter of 200 μm were formed on these green sheets by using a puncher in the vertical direction, and each via hole was filled with an Ag conductor paste to be the via conductor 4. After that, a pattern of 5 circuits of Ag thick film wiring was formed by screen printing using the Ag conductor paste so as to be connected to the Ag conductor paste in the via hole.
Green sheets on which wiring patterns are formed are sequentially stacked, and the temperature is 120 ° C and the pressure is 200 using a heat press machine or the like.
Thermocompression bonding was performed from the upper and lower surfaces under the condition of kg / cm 2 to obtain a laminate.
【００３６】一方、０.６５ｍｍ厚で１.６×４.８(ｍ
ｍ)角の焼成済みアルミナ板１１の２枚にそれぞれ５個
のビアホールを形成し、各ビアホールに、焼成するとビ
ア導体４となるＡｇ導体ペーストを充填した。各アルミ
ナ板１１上に、ビアホール中のＡｇ導体ペーストと接続
するようＡｕペーストを用いて一辺が０.８ｍｍの正方
形の厚膜を、スクリーン印刷によりそれぞれ５つ形成し
た。On the other hand, the thickness of 0.65 mm is 1.6 × 4.8 (m
m) Five via holes were formed in each of the two squared alumina plates 11, and each via hole was filled with an Ag conductor paste that becomes a via conductor 4 when fired. On each alumina plate 11, five square thick films each having a side of 0.8 mm were formed by screen printing using Au paste so as to be connected to the Ag conductor paste in the via holes.
【００３７】次にグリーンシートの積層体の最上面に２
つのアルミナ板１１を、それぞれ積層体中の配線と電気
的に接続するよう重ねて、熱プレス機などを用いて温度
１２０℃、圧力２００ｋｇ／ｃｍ2の条件で上下面から
熱圧着し、空気中、約４００℃で１時間の脱脂を行った
後、８５０℃で１０分間焼成して、多層回路基板を作製
した。焼成の結果、絶縁層２内に気泡の発生は認められ
なかった。またＡｕパッド３もめくれ上がることなく形
成され、アルミナ板１１と絶縁層２の接合強度は２.５k
gfあった。Next, 2 is formed on the uppermost surface of the stack of green sheets.
The two alumina plates 11 are stacked so as to be electrically connected to the wirings in the laminate, and thermocompression-bonded from the upper and lower surfaces under the conditions of a temperature of 120 ° C. and a pressure of 200 kg / cm 2 by using a heat press machine, etc. After degreasing at about 400 ° C. for 1 hour, baking was performed at 850 ° C. for 10 minutes to produce a multilayer circuit board. As a result of firing, generation of bubbles was not recognized in the insulating layer 2. Further, the Au pad 3 is also formed without turning up, and the bonding strength between the alumina plate 11 and the insulating layer 2 is 2.5 k.
There was gf.
【００３８】更に、この多層回路基板上のＡｕパッド３
とこの基板上に取り付けたチップ６とをＡｕ線７を用い
てワイヤボンディングすることに成功した。本実施例で
は、アルミナ板１を用いたが、代わりに融点が１２００
℃以上の他のセラミックス例えば、ＡｌＮ，ＳｉＣ，ム
ライト等をバリア層としても良い。Further, the Au pad 3 on this multilayer circuit board
It succeeded in wire-bonding the chip 6 mounted on this substrate with the Au wire 7. In this example, the alumina plate 1 was used, but instead, the melting point was 1200.
Other ceramics having a temperature of ℃ or more, such as AlN, SiC, mullite may be used as the barrier layer.
【００３９】〔実施例４〕本実施例を図６を用いて説明
する。図６はチップを実装した多層回路基板の縦断面図
である。実施例１と同様に、Ａｇ粉末、Ｂｉ2Ｏ3粉末お
よびアクリル樹脂／ブチルカルビトールアセテートから
Ａｇ導体ペーストを作製し、そしてＡｕペーストも同様
な方法で作製した。また実施例１と同様に硼硅酸鉛ガラ
ス、アルミナ粉末およびポリビニルブチラール等の有機
溶剤から、１００×１００(ｍｍ)の未焼成のグリーンシ
ートを４枚形成した。[Embodiment 4] This embodiment will be described with reference to FIG. FIG. 6 is a vertical sectional view of a multilayer circuit board on which chips are mounted. Similar to Example 1, an Ag conductor paste was prepared from Ag powder, Bi 2 O 3 powder and acrylic resin / butyl carbitol acetate, and an Au paste was prepared in the same manner. Further, as in Example 1, four 100 × 100 (mm) unfired green sheets were formed from lead borosilicate glass, alumina powder, and an organic solvent such as polyvinyl butyral.
【００４０】これらグリーンシートに垂直方向にパンチ
ャーを用いて、直径２００μｍのビアホールを複数個形
成し、各ビアホールにビア導体４となるべきＡｇ導体ペ
ーストを充填した。その後、各グリーンシートに、それ
ぞれビアホール中のＡｇ導体ペーストと接続するように
Ａｇ導体ペーストを用いてスクリーン印刷でＡｇ厚膜配
線５の回路パターンを形成した。A plurality of via holes having a diameter of 200 μm were formed in these green sheets in the vertical direction using a puncher, and each via hole was filled with an Ag conductor paste to be the via conductor 4. After that, a circuit pattern of the Ag thick film wiring 5 was formed on each green sheet by screen printing using the Ag conductor paste so as to be connected to the Ag conductor paste in the via hole.
【００４１】一方、０.０５ｍｍ厚で１１０×１１０(ｍ
ｍ)角の焼成したアルミナ板１にビアホールを形成し、
そのビアホールにビア導体４となるべきＡｇ導体ペース
トを充填した。さらにビアホール中のＡｇ導体ペースト
と接続するようＡｕペーストを用いて一辺が１.５ｍｍ
の正方形の厚膜をスクリーン印刷により形成した。さら
に上記４枚のグリーンシートの内の２枚に、アルミナ板
１に形成したのＡｕペースト膜の位置に対応して、大き
めの穴をくり抜いた。On the other hand, with a thickness of 0.05 mm, 110 × 110 (m
m) forming a via hole in the square fired alumina plate 1,
The via hole was filled with an Ag conductor paste to be the via conductor 4. Furthermore, using Au paste to connect with the Ag conductor paste in the via hole, one side is 1.5 mm.
The square thick film of was formed by screen printing. Further, large holes were cut out in two of the four green sheets corresponding to the position of the Au paste film formed on the alumina plate 1.
【００４２】次に、配線５の回路パターンを形成した４
枚のうちの２枚のグリーンシートを重ね、その上にアル
ミナ板１を、Ａｕペースト膜を上にして載置し、さらに
アルミナ板１上に、Ａｕペースト膜の位置に対応して大
きめの穴をくり抜いたグリーンシートの２枚を重ねた。
熱プレス機などを用いて温度１２０℃、圧力２００ｋｇ
／ｃｍ2の条件で上下面から熱圧着し、積層体を得た。
それから、空気中、約４００℃で１時間の脱脂を行った
後、８５０℃で１０分間焼成して、多層回路基板を作製
した。焼成の結果、基板に反りは発生せず、また、焼成
中に破断することも無かった。更に絶縁層内に気泡の発
生は認められなかった。また、Ａｕパッド３もめくれ上
がることなく形成され、アルミナ板１との接着強度は
２.２ kgfあった。Next, the circuit pattern of the wiring 5 was formed 4
Two of the green sheets are stacked, the alumina plate 1 is placed on top of it, and a large hole corresponding to the position of the Au paste film is placed on the alumina plate 1. Two green sheets that were hollowed out were stacked.
Using a hot press machine, temperature 120 ℃, pressure 200kg
The laminate was obtained by thermocompression bonding from the upper and lower surfaces under the condition of / cm 2 .
Then, after degreasing in air at about 400 ° C. for 1 hour, firing was performed at 850 ° C. for 10 minutes to prepare a multilayer circuit board. As a result of the firing, the substrate did not warp and did not break during firing. Furthermore, no bubbles were observed in the insulating layer. The Au pad 3 was also formed without turning up, and the adhesive strength with the alumina plate 1 was 2.2 kgf.
【００４３】更に、この多層回路基板上のＡｕパッド３
とこの基板上に取り付けたチップ６とをＡｕ線７を用い
てワイヤボンディングすることに成功した。本実施例で
は、アルミナ板１を用いたが、代わりに融点が１２００
℃以上の他のセラミックス例えば、ＡｌＮ，ＳｉＣ，ム
ライト等をバリア層としても良い。Further, the Au pad 3 on this multilayer circuit board is used.
It succeeded in wire-bonding the chip 6 mounted on this substrate with the Au wire 7. In this example, the alumina plate 1 was used, but instead, the melting point was 1200.
Other ceramics having a temperature of ℃ or more, such as AlN, SiC, mullite may be used as the barrier layer.
【００４４】〔実施例５〕図７を用いて本実施例を説明
する。図７はチップを実装した多層回路基板の断面図で
ある。実施例１と同様に、Ａｇ粉末、Ｂｉ2Ｏ3粉末およ
びアクリル樹脂／ブチルカルビトールアセテートからＡ
ｇ導体ペーストを作製し、そしてＡｕペーストも同様な
方法で作製した。また実施例１と同様に硼硅酸鉛ガラ
ス、アルミナ粉末およびポリビニルブチラール等の有機
溶剤から、１０ｃｍ×１０ｃｍの未焼成のグリーンシー
トを複数枚形成した。[Embodiment 5] This embodiment will be described with reference to FIG. FIG. 7 is a sectional view of a multilayer circuit board on which chips are mounted. As in Example 1, Ag powder, Bi 2 O 3 powder and acrylic resin / butyl carbitol acetate
A g conductor paste was made, and an Au paste was made in a similar manner. Further, in the same manner as in Example 1, a plurality of unfired green sheets of 10 cm × 10 cm were formed from lead borosilicate glass, alumina powder, and an organic solvent such as polyvinyl butyral.
【００４５】これらグリーンシートに垂直方向にパンチ
ャーを用いて、直径２００μｍのビアホールを複数個形
成し、ビア導体４となるべきＡｇ導体ペーストを充填し
た。その後に各グリーンシート上にビアホール中のＡｇ
導体ペーストと接続するように、Ａｇ導体ペーストを用
いてスクリーン印刷で配線パターンを形成した。それか
ら、配線パターンを形成した複数のグリーンシートを順
次積み重ねた。A plurality of via holes each having a diameter of 200 μm were formed on these green sheets by using a puncher in the vertical direction and filled with Ag conductor paste to be the via conductors 4. After that, Ag in the via hole on each green sheet
A wiring pattern was formed by screen printing using Ag conductor paste so as to be connected to the conductor paste. Then, a plurality of green sheets having a wiring pattern were sequentially stacked.
【００４６】一方、０.０５ｍｍ厚、１1０×１1０(ｍ
ｍ)角で焼成した２枚のアルミナ板１にビアホールを形
成し、ビア導体４となるべくＡｇ導体ペーストを充填し
た。次に、積み重ねたグリーンシートの両面にそれぞれ
アルミナ板１を電気的に接続するように重ねて、熱プレ
ス機などを用いて温度１２０℃、圧力２００ｋｇ／ｃｍ
2の条件で上下面から熱圧着し、積層体を得た。この積
層体のアルミナ板１上にこのアルミナ板１のビアホール
中のＡｇ導体ペーストと接続する様に、Ａｕペーストを
用いて、一辺が１.５ｍｍの正方形の厚膜を、スクリー
ン印刷により形成した。この後、空気中、約４００℃で
６時間の脱脂を行った後、８５０℃で１０分間焼成し
て、多層回路基板を作製した。焼成の結果、基板はやや
中央部に凹みが認められるものの焼成中に破断すること
は無かった。また、絶縁層２内に気泡の発生は認められ
なかった。また、Ａｕパッド３もめくれ上がることなく
形成され、アルミナ板１とパッド３との接着強度は２.
２kgfあった。アルミナ板１と絶縁層２の接着強度は十
分大きかった。On the other hand, a thickness of 0.05 mm, 110 × 110 (m
m) Via holes were formed in the two alumina plates 1 fired at the corners, and the via conductors 4 were filled with Ag conductor paste as much as possible. Next, the alumina sheets 1 are stacked on both sides of the stacked green sheets so as to be electrically connected to each other, and the temperature is 120 ° C. and the pressure is 200 kg / cm by using a heat press machine or the like.
Thermocompression bonding was performed from the upper and lower surfaces under the condition of 2 to obtain a laminate. On the alumina plate 1 of this laminated body, a square thick film having a side of 1.5 mm was formed by screen printing using Au paste so as to be connected to the Ag conductor paste in the via hole of the alumina plate 1. After that, degreasing was performed in air at about 400 ° C. for 6 hours, and then firing was performed at 850 ° C. for 10 minutes to produce a multilayer circuit board. As a result of the baking, the substrate had a slight depression in the center, but was not broken during the baking. In addition, generation of bubbles was not recognized in the insulating layer 2. Further, the Au pad 3 is also formed without turning up, and the adhesive strength between the alumina plate 1 and the pad 3 is 2.
It was 2 kgf. The adhesive strength between the alumina plate 1 and the insulating layer 2 was sufficiently high.
【００４７】更に、この多層回路基板上のＡｕパッド３
とこの基板上に取り付けたチップ６とをＡｕ線７を用い
てワイヤボンディングすることに成功した。本実施例で
は、アルミナ板１を用いたが、代わりに融点が１２００
℃以上の他のセラミックス例えば、ＡｌＮ，ＳｉＣ，ム
ライト等をバリア層としても良い。Further, the Au pad 3 on this multilayer circuit board
It succeeded in wire-bonding the chip 6 mounted on this substrate with the Au wire 7. In this example, the alumina plate 1 was used, but instead, the melting point was 1200.
Other ceramics having a temperature of ℃ or more, such as AlN, SiC, mullite may be used as the barrier layer.
【００４８】〔実施例６〕図８を用いて本実施例を説明
する。図８はチップを実装した多層回路基板の断面図で
ある。実施例５（図７）のグリーンシートの積層工程に
おいて０.０５ｍｍ厚、１1０×１1０(ｍｍ)角のアルミ
ナ板１を積層体の層間に余分に挿入したが、焼成中基板
が破断することは無かった。そしてアルミナ板１を積層
体のいずれの層間に挿入しても問題がなかった。[Sixth Embodiment] This embodiment will be described with reference to FIG. FIG. 8 is a sectional view of a multilayer circuit board on which chips are mounted. In the green sheet laminating process of Example 5 (FIG. 7), an alumina plate 1 having a thickness of 0.05 mm and a size of 110 × 110 (mm) square was excessively inserted between the layers of the laminate, but the substrate was not broken during firing. There was no There was no problem in inserting the alumina plate 1 between any layers of the laminate.
【００４９】〔対象例〕実施例１(図１)において、厚さ
０.６５ｍｍのアルミナ板の代わりに０.０５ｍｍのアル
ミナ板１を用いて基板を作製しようとしたが、焼成工程
において基板が破断してしまった。[Target Example] In Example 1 (FIG. 1), an attempt was made to use a 0.05 mm alumina plate 1 instead of the 0.65 mm thick alumina plate. It broke.
【００５０】〔実施例７〕実施例１と同様に、Ａｇ粉
末、Ｂｉ2Ｏ3粉末およびアクリル樹脂／ブチルカルビト
ールアセテートからＡｇ導体ペーストを作製し、そして
Ａｕペーストも同様な方法で作製した。また実施例１と
同様に硼硅酸鉛ガラス、アルミナ粉末およびポリビニル
ブチラール等の有機溶剤から、１００×１００(ｍｍ)角
の未焼成のグリーンシートを複数枚形成した。Example 7 As in Example 1, an Ag conductor paste was prepared from Ag powder, Bi 2 O 3 powder and acrylic resin / butyl carbitol acetate, and an Au paste was prepared in the same manner. In the same manner as in Example 1, a plurality of unburned green sheets of 100 × 100 (mm) square were formed from lead borosilicate glass, alumina powder, and an organic solvent such as polyvinyl butyral.
【００５１】これらグリーンシートに垂直方向にパンチ
ャーを用いて、直径２００μｍのビアホールを複数個形
成し、ビア導体４となるべきＡｇ導体ペーストを充填し
た。その後に、各グリーンシート上にビアホール中のＡ
ｇ導体ペーストと接続するようＡｇ導体ペーストを用い
てスクリーン印刷で配線パターンを形成した。次に配線
パターンを形成した複数のグリーンシートを順次積み重
ねた。熱プレス機などを用いて温度１２０℃、圧力２０
０ｋｇ／ｃｍ2の条件で上下面から熱圧着し、積層体を
得た。この積層体を、空気中、約４００℃で１時間の脱
脂を行った後、８５０℃で１０分間焼成し、焼結体を得
た。A plurality of via holes having a diameter of 200 μm were formed on these green sheets in the vertical direction by using a puncher, and Ag conductor paste to be the via conductors 4 was filled therein. After that, A in the via hole on each green sheet
A wiring pattern was formed by screen printing using Ag conductor paste so as to be connected to the g conductor paste. Next, a plurality of green sheets having a wiring pattern were sequentially stacked. Using a heat press machine, temperature 120 ℃, pressure 20
Thermocompression bonding was performed from the upper and lower surfaces under the condition of 0 kg / cm 2 to obtain a laminate. This laminated body was degreased in air at about 400 ° C. for 1 hour and then fired at 850 ° C. for 10 minutes to obtain a sintered body.
【００５２】一方、厚さ０．６５ｍｍ、１１０×１１０
(ｍｍ)各で焼成したアルミナ板１にビアホールを形成
し、ビア導体４となるべきＡｇ導体ペーストを充填し
た。それからアルミナ板１のビアホール中のＡｇ導体ペ
ーストに接続する様に、Ａｕペーストを用いて一辺１.
５ｍｍの正方形の厚膜をスクリーン印刷により形成し
た。On the other hand, thickness 0.65 mm, 110 × 110
(mm) A via hole was formed in the alumina plate 1 fired in each, and an Ag conductor paste to be the via conductor 4 was filled. Then, use Au paste to connect to the Ag conductor paste in the via hole of the alumina plate 1.
A 5 mm square thick film was formed by screen printing.
【００５３】次に、上記の焼結体に電気的に接続するよ
うに上記Ａｕ膜を形成したアルミナ板１を重ね、加圧し
ながら、８５０℃で１０分間焼成した。このように焼結
体同士を焼成した結果、絶縁層内に気泡の発生は認めら
れなかった。また、Ａｕパッド３もめくれ上がることな
く形成され、基板とパッド３との接着強度は２.２kgfあ
った。アルミナ板１と絶縁層２の接着強度は十分大きか
った。Next, the alumina plate 1 on which the Au film was formed so as to be electrically connected to the above-mentioned sintered body was stacked, and was baked at 850 ° C. for 10 minutes while applying pressure. As a result of firing the sintered bodies together in this way, generation of bubbles was not recognized in the insulating layer. Further, the Au pad 3 was also formed without turning up, and the adhesive strength between the substrate and the pad 3 was 2.2 kgf. The adhesive strength between the alumina plate 1 and the insulating layer 2 was sufficiently high.
【００５４】更に、この多層回路基板上のＡｕパッド３
とこの基板上に取り付けたチップ６とをＡｕ線７を用い
てワイヤボンディングすることに成功した。本実施例で
は、アルミナ板１を用いたが、代わりに融点が１２００
℃以上の他のセラミックス例えば、ＡｌＮ，ＳｉＣ，ム
ライト等をバリア層としても良い。Further, the Au pad 3 on this multilayer circuit board
It succeeded in wire-bonding the chip 6 mounted on this substrate with the Au wire 7. In this example, the alumina plate 1 was used, but instead, the melting point was 1200.
Other ceramics having a temperature of ℃ or more, such as AlN, SiC, mullite may be used as the barrier layer.
【００５５】〔実施例８〕実施例１の多層回路基板を使
用し、表面に複数のベアチップを実装したマルチチップ
モジュールを作製した。そして、このマルチチップモジ
ュールが正常に動作することを確認した。[Embodiment 8] Using the multilayer circuit board of Embodiment 1, a multi-chip module having a plurality of bare chips mounted on its surface was manufactured. Then, it was confirmed that this multichip module operates normally.
【００５６】[0056]
【発明の効果】本発明によれば、ワイヤボンディング用
パッドを、１２００℃以上の融点もしくは軟化点をもつ
焼結済みセラミックス上に形成することにより、Ａｇ系
配線回路を有する低温焼成多層回路基板への厚膜ワイヤ
ボンディングの形成を可能とする。その結果、前記多層
回路基板への良好なワイヤボンディングが可能となり、
ベアチップ搭載やマルチチップもジュールを実現でき
る。According to the present invention, a wire bonding pad is formed on a sintered ceramic having a melting point or a softening point of 1200 ° C. or higher, thereby forming a low temperature fired multilayer circuit board having an Ag-based wiring circuit. It enables the formation of thick film wire bonding. As a result, good wire bonding to the multilayer circuit board becomes possible,
Bare chips and multi-chips can be used as joules.
【図１】一枚板バリア層付き多層回路基板の構成を示す
断面図である。FIG. 1 is a cross-sectional view showing a configuration of a multilayer circuit board with a single-plate barrier layer.
【図２】図１の上面図である。FIG. 2 is a top view of FIG.
【図３】アルミナでなるバリア小片付き多層回路基板の
構成を示す断面図である。FIG. 3 is a cross-sectional view showing the configuration of a multilayer circuit board with barrier pieces made of alumina.
【図４】図４の上面図である。FIG. 4 is a top view of FIG.
【図５】アルミナ板の複数バリア層を設けた多層回路基
板を示す上面図である。FIG. 5 is a top view showing a multilayer circuit board provided with a plurality of barrier layers of an alumina plate.
【図６】基板の厚さ方向中心にアルミナ板でなるバリア
層を設けたコア型多層回路基板の断面図である。FIG. 6 is a cross-sectional view of a core type multilayer circuit board in which a barrier layer made of an alumina plate is provided at the center of the board in the thickness direction.
【図７】基板の上下両面に高融点のアルミナ板を設けた
対称型多層回路基板の断面図である。FIG. 7 is a cross-sectional view of a symmetrical multilayer circuit board in which high melting point alumina plates are provided on both upper and lower surfaces of the board.
【図８】基板の上面と厚さ方向の中間位置に高融点のア
ルミナ板を設けた挿入型多層回路基板の断面図である。FIG. 8 is a cross-sectional view of an insertion-type multilayer circuit board in which a high melting point alumina plate is provided at an intermediate position in the thickness direction with respect to the upper surface of the board.
【図９】多層回路基板作製のプロセスの一例を示す図で
ある。FIG. 9 is a diagram illustrating an example of a process of manufacturing a multilayer circuit board.
１ アルミナ板 ２ 絶縁層 ３ Ａｕパッド ４ ビア導体 ５ Ａｇ厚膜配線 ６ チップ ７ Ａｕ線 ８ アルミナ小片 ９ Ａｇ厚膜導体 １１ アルミナ板 DESCRIPTION OF SYMBOLS 1 Alumina plate 2 Insulating layer 3 Au pad 4 Via conductor 5 Ag thick film wiring 6 Chip 7 Au wire 8 Alumina small piece 9 Ag thick film conductor 11 Alumina plate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 長谷川 満 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuru Hasegawa 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory
Claims (9)
状に形成され、基板上面には該基板に搭載されるチップ
と結線されるＡｕ，Ｐｔ，ＣｕもしくはＡｌからなるパ
ッドが形成されたセラミック多層回路基板において、前
記回路が形成された基板部分は、融点もしくは軟化点が
５２５〜８００℃であるガラス層からなり、前記パッド
が形成された基板部分は、融点もしくは軟化点が１２０
０℃以上である高融点セラミック絶縁層からなることを
特徴とするセラミック多層回路基板。1. A circuit made of an Ag-based conductor is formed in a multi-layer structure in a substrate, and a pad made of Au, Pt, Cu or Al connected to a chip mounted on the substrate is formed on an upper surface of the substrate. In the ceramic multilayer circuit board, the circuit board-formed substrate portion is formed of a glass layer having a melting point or softening point of 525 to 800 ° C., and the board portion-formed board portion has a melting point or softening point of 120.
A ceramic multilayer circuit board comprising a high melting point ceramic insulating layer having a temperature of 0 ° C. or higher.
ス層上全面をおおう一枚板で構成されたことを特徴とす
る請求項１記載のセラミック多層回路基板。2. The ceramic multilayer circuit board according to claim 1, wherein the high-melting-point ceramic insulating layer is formed of a single plate covering the entire surface of the glass layer.
ス層上に２つ以上に分割され、該分割された高融点セラ
ミック絶縁層上に１つ以上の前記パッドを有することを
特徴とする請求項１記載のセラミック多層回路基板。3. The high melting point ceramic insulating layer is divided into two or more on the glass layer, and one or more pads are provided on the divided high melting point ceramic insulating layer. 1. The ceramic multilayer circuit board according to 1.
状に形成され、基板上面には該基板に搭載されるチップ
と結線されるＡｕ，Ｐｔ，ＣｕもしくはＡｌからなるパ
ッドが形成されたセラミック多層回路基板において、前
記回路が形成された基板部分は、融点もしくは軟化点が
１２００℃以上である高融点セラミック絶縁層を一層含
み他が融点もしくは軟化点が５２５〜８００℃であるガ
ラス層からなり、前記パッドが形成された基板部分は、
融点もしくは軟化点が１２００℃以上である高融点セラ
ミック絶縁層からなることを特徴とするセラミック多層
回路基板。4. A circuit made of an Ag-based conductor is formed in multiple layers in a substrate, and a pad made of Au, Pt, Cu or Al connected to a chip mounted on the substrate is formed on an upper surface of the substrate. In the ceramic multi-layer circuit board, the board portion on which the circuit is formed includes one high-melting-point ceramic insulating layer having a melting point or softening point of 1200 ° C. or higher, and the other from a glass layer having a melting point or softening point of 525 to 800 ° C. And the substrate portion on which the pad is formed is
A ceramic multilayer circuit board comprising a high melting point ceramic insulating layer having a melting point or a softening point of 1200 ° C. or higher.
縁層が、該ガラス層の最下部を占めることを特徴とする
請求項４記載のセラミック多層回路基板。5. The ceramic multilayer circuit board according to claim 4, wherein the high melting point ceramic insulating layer included in the glass layer occupies the lowermost portion of the glass layer.
縁層が、該ガラス層の厚さ方向の中央部を占めることを
特徴とする請求項４記載のセラミック多層回路基板。6. The ceramic multilayer circuit board according to claim 4, wherein the high-melting-point ceramic insulating layer included in the glass layer occupies a central portion in the thickness direction of the glass layer.
状に形成され、基板上面には該基板に搭載されるチップ
と結線されるＡｕ，Ｐｔ，ＣｕもしくはＡｌからなるパ
ッドが形成されたセラミック多層回路基板において、前
記パッドが表側に形成された基板部分は、融点もしくは
軟化点が１２００℃以上である高融点セラミック絶縁層
からなり、前記回路が形成された基板部分は、融点もし
くは軟化点が５２５〜８００℃であるガラス層からな
り、かつ回路が形成された基板部分の層の半分が前記高
融点セラミック絶縁層の裏側に、残りの半分が前記パッ
ドの位置に対応して該パッドを入れる穴を設けて高融点
セラミック絶縁層の表側に設けられていることを特徴と
するセラミック多層回路基板。7. A circuit made of an Ag-based conductor is formed in a multi-layered manner in a substrate, and a pad made of Au, Pt, Cu or Al connected to a chip mounted on the substrate is formed on an upper surface of the substrate. In the ceramic multilayer circuit board, the board portion on which the pad is formed is made of a high melting point ceramic insulating layer having a melting point or softening point of 1200 ° C. or higher, and the board portion on which the circuit is formed has a melting point or softening point. Of a glass layer having a temperature of 525 to 800 ° C., and half of the layer of the substrate portion on which the circuit is formed is on the back side of the high melting point ceramic insulating layer, and the other half corresponds to the position of the pad. A ceramic multi-layer circuit board, characterized in that a hole for insertion is provided on the front side of the high-melting-point ceramic insulating layer.
基板にチップを搭載し該チップと前記パッドとをワイヤ
ボンディングにより接続してなることを特徴とするチッ
プモジュール。8. A chip module comprising a ceramic multi-layer circuit board according to claim 1, wherein a chip is mounted, and the chip and the pad are connected by wire bonding.
状に形成され、基板上面には該基板に搭載されるチップ
と結線されるＡｕ，Ｐｔ，ＣｕもしくはＡｌからなるパ
ッドが形成されたセラミック多層回路基板の製法におい
て、焼結済みで１２００℃以上の融点もしくは軟化点を
有する高融点絶縁板にビアホールを形成し、このビアホ
ールにＡｇペーストを充填し、次いで高融点絶縁板の一
方の面にビアホール中のＡｇペーストと接続して、前記
パッドとなるべきＡｕ，Ｐｔ，ＣｕもしくはＡｌのペー
ストの膜を形成する一方、焼成することにより融点もし
くは軟化点が５２５〜８００℃であるガラス層となる複
数のグリーンシートそれぞれにビアホールを形成し、各
グリーンシートのビアホールにＡｇペーストを充填し、
各グリーンシート上にＡｇペーストにより配線回路パタ
ーンを印刷し、該印刷したグリーンシートを積層し、さ
らに該グリーンシートの積層体と、パッドとなるべきペ
ーストの膜を形成した高融点絶縁板とを組合せ、脱脂し
た後に前記ガラス層の融点で焼成することを特徴とする
セラミック多層回路基板の製法。9. A circuit made of an Ag-based conductor is formed in a multi-layered structure in a substrate, and a pad made of Au, Pt, Cu or Al connected to a chip mounted on the substrate is formed on an upper surface of the substrate. In the method for manufacturing a ceramic multilayer circuit board, a via hole is formed in a high melting point insulating plate that has been sintered and has a melting point or softening point of 1200 ° C. or higher, the via hole is filled with Ag paste, and then one surface of the high melting point insulating plate is formed. While being connected to the Ag paste in the via hole to form a film of a paste of Au, Pt, Cu or Al to serve as the pad, a glass layer having a melting point or softening point of 525 to 800 ° C. is formed by firing. Forming a via hole in each of the plurality of green sheets, and filling the via hole of each green sheet with Ag paste,
A wiring circuit pattern is printed on each green sheet with Ag paste, the printed green sheets are laminated, and a laminate of the green sheets and a high-melting point insulating plate on which a paste film to be a pad is formed are combined. A method for manufacturing a ceramic multilayer circuit board, comprising degreasing and firing at the melting point of the glass layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6210974A JPH0878849A (en) | 1994-09-05 | 1994-09-05 | Ceramic multilayered circuit board and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6210974A JPH0878849A (en) | 1994-09-05 | 1994-09-05 | Ceramic multilayered circuit board and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0878849A true JPH0878849A (en) | 1996-03-22 |
Family
ID=16598218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6210974A Pending JPH0878849A (en) | 1994-09-05 | 1994-09-05 | Ceramic multilayered circuit board and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0878849A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008270756A (en) * | 2007-03-26 | 2008-11-06 | Ngk Spark Plug Co Ltd | Multilayer ceramic substrate and method of manufacturing the same |
| JP2009152352A (en) * | 2007-12-20 | 2009-07-09 | Ngk Spark Plug Co Ltd | Manufacturing method of multilayer ceramic substrate for electronic component inspection fixture |
| JP2009158576A (en) * | 2007-12-25 | 2009-07-16 | Ngk Spark Plug Co Ltd | Multilayer ceramic substrate for electronic component inspecting tool |
| US8125060B2 (en) | 2006-12-08 | 2012-02-28 | Infineon Technologies Ag | Electronic component with layered frame |
-
1994
- 1994-09-05 JP JP6210974A patent/JPH0878849A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8125060B2 (en) | 2006-12-08 | 2012-02-28 | Infineon Technologies Ag | Electronic component with layered frame |
| US8703544B2 (en) | 2006-12-08 | 2014-04-22 | Infineon Technologies Ag | Electronic component employing a layered frame |
| JP2008270756A (en) * | 2007-03-26 | 2008-11-06 | Ngk Spark Plug Co Ltd | Multilayer ceramic substrate and method of manufacturing the same |
| JP2009152352A (en) * | 2007-12-20 | 2009-07-09 | Ngk Spark Plug Co Ltd | Manufacturing method of multilayer ceramic substrate for electronic component inspection fixture |
| JP2009158576A (en) * | 2007-12-25 | 2009-07-16 | Ngk Spark Plug Co Ltd | Multilayer ceramic substrate for electronic component inspecting tool |
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