JPH087770A - Surface discharge ac plasma display panel and display device using this - Google Patents

Abstract

PURPOSE:To lessen the size of picture element and achieve a highly fine displaying by installing a plurality of linearly maintaining electrodes on a glass board in such a way as separately and at a different level from a plane-form maintaining electrode. CONSTITUTION:On the first board 11 a plurality of linear. second electrodes Y1-Yn are installed in such a way as separately and at a different level from the first electrode XA. and the first electrode XA and second electrodes Y1-Yn are covered with dielectric substance layers 12, 13. Separately from the first board 11 the second board 14 is installed opposingly, and a plurality of third electrodes A1-An are installed on the second board 14 in such a way as separately from and in intersection with the second electrodes Y1-Yn. A phosphor 15 is attached to the second board 14 side, and a gas for discharging is encapsulated in the space 17 bounded by the first board 11 and second board 14. Thereby the size of picture element is made smaller than in a conventional arrangement in which the first electrode and the second electrodes are located on a level, and the displaying can be made with a high fineness.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat discharge AC type plasma display panel and a display device using the same.

2. Description of the Related Art FIG. 7 shows a cross section of a cell 10 which constitutes a pixel in an i-th row and a j-th column of a conventional flat discharge AC type plasma display panel (hereinafter referred to as PDP) having three electrodes. A pair of sustain electrodes X and Y extending in the direction perpendicular to the paper surface
i is formed on a glass substrate 11, a dielectric layer 12 for retaining wall charges is deposited thereon, and MgO is further deposited thereon.
A protective film 13 is applied. On the other hand, the address electrodes Aj extending in the left-right direction on the paper surface are formed on the glass substrate 14 which is arranged so as to face the glass substrate 11, and the fluorescent substance 15 which is also a dielectric substance is deposited thereon. Further, on the glass substrate 14, partition walls 16 are formed at pixel boundaries. M
The discharge space 17 between the gO protective film 13 and the phosphor 15 is filled with, for example, a Ne + Xe Penning mixed gas. Since the PDP is a self-luminous type as compared with a liquid crystal display panel, it has a good display quality, a high response speed, and a large screen is easy.

However, the pair of sustain electrodes X and Yi must be spaced apart in the same plane, and the wall charge is applied to the dielectric layer 12 on the sustain electrodes X and Yi. Since it has to be held in a plane, it is limited to reduce the pixel size to achieve high definition display. Particularly in the case of color display, this problem is magnified because a cell must be formed for each of the three primary colors of light.
In view of the above problems, an object of the present invention is to provide a flat discharge AC type plasma display panel capable of reducing the pixel size to achieve high definition display, and a display device using the same.

Means for Solving the Problem and Its Action
Description will be given by citing the corresponding reference numerals in the embodiment drawings. In the flat discharge AC type plasma display panel of the first invention,
For example, as shown in FIG. 1 and FIG.
A plurality of linear second electrodes Y1 to Yn are arranged at different heights and spaced apart from the electrode XA, the first electrode XA and the second electrodes Y1 to Yn are covered with the dielectric layers 12 and 13, and The second substrate 14 is disposed so as to face the first substrate 11 so as to be spaced apart from it, and the plurality of third electrodes A1 to Am are disposed on the second substrate 14 so as to intersect with the second electrodes Y1 to Yn while being spaced apart from each other. The phosphor 15 is attached to the substrate 14 side, and the first substrate 11 and the second substrate 14 are attached.
A discharge gas is sealed in a space 17 between According to the first aspect of the invention, the plurality of linear second electrodes Y1 to Y1 on the first substrate 11 are arranged at different heights and spaced apart from the first electrode XA.
Since Yn is arranged, the pixel size can be made smaller and the display can be made finer than in the case of FIG. 7 in which the first electrode and the second electrode are arranged at the same height. Also, the second
Since the electrodes Y1 to Yn are formed in a layer different from that of the first electrode XA, lead wires can be easily drawn from both ends of the first electrodes Y1 to Yn.
The second aspect can be easily configured. In the first aspect of the first aspect of the invention, for example, as shown in FIGS. 1 and 2, the first electrode XA
Is a surface electrode and is arranged closer to the first substrate 11 than the second electrode Yi. According to the first aspect, the potential of the first electrode XA can be made more constant than in the case of the line electrode, and the display quality is improved. Second of the first invention
In the aspect, for example, as shown in FIG. 6, the first electrode XC is a plurality of line electrodes arranged in parallel with and not overlapping with the second electrode Yi, and the ends of the plurality of line electrodes are connected. . According to the second aspect, the electric field strength due to the wall charges is stronger than that in the first aspect. In the flat discharge AC type plasma display device of the second invention, as shown in FIG. 2, for example, a scan pulse is applied line-sequentially to any one of the above flat discharge AC type plasma display panels and a plurality of second electrodes Y1 to Yn. The dielectric layer 1 on the second electrodes Yi to which the scan pulse is applied for each scan pulse to the scan drivers 25A and 25B and the third electrodes A1 to Am.
An address driver 23 for applying an address pulse to accumulate wall charges corresponding to display data in 2 and 13;
Between the first electrode XA and the second electrode Yi, the dielectric layer 12,
Common driver 24A that applies an AC sustain pulse to cause sustain discharge in addition to the voltage due to the wall charges on 13
24B and 26. In the first aspect of the second invention,
For example, as shown in FIG. 1, scan drivers 25A and 25B
Are connected to the second electrodes Y1 to Yn so as to apply the scan pulse from both ends of each of the second electrodes Y1 to Yn. According to the first aspect, the potential gradient on each of the second electrodes Y1 to Yn is reduced, and the display quality is improved. In the second aspect of the second invention, for example, as shown in FIG. 4, the scan drivers 25C and 25D include the odd-numbered second electrodes Y1 and Y3,
... so that the scan pulse is applied from one end side of the second electrodes Y2, Y4 (not shown) and the other end side of the ...
It is connected to Yn. According to the second aspect, even if the pixel size is small and the pitch of the second electrodes Y1 to Yn is small, the second electrodes Y1 to Yn and the scan drivers 25A and 25 are also provided.
Connection with B becomes easy.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components are designated by the same or similar reference numerals. [First Embodiment] FIG. 1 shows a sectional structure of a cell of a flat discharge AC type plasma display panel of the first embodiment. A planar sustain electrode XA is deposited on the glass substrate 11,
The dielectric layer 12 is deposited on the sustain electrode XA, and the dielectric layer 1
After the linear sustain electrode Yi is formed on the second electrode 2, the sustain electrode Yi is covered with the dielectric layer 12. A MgO protective film 13, which is also a dielectric, is deposited on the dielectric layer 12. In the first embodiment, since the sustain electrodes Yi and the sustain electrodes XA are formed in different layers, the cell size can be made smaller than that in the case of FIG. The glass substrate 14 side is the same as the glass substrate 14 side of FIG. 7 except that the size of one side of the rectangular partition wall 16 surrounding the separated intersection of the sustain electrode Yi and the address electrode Aj is shorter than that in the case of FIG. 7. It has the same configuration.
FIG. 2 shows a schematic configuration of a plasma display device 20 having the cell 10 of FIG. The display panel 21 is n × m
The pixels are subscripts i and j of the sustain electrode Yi and the address electrode Aj, i = 1 to n and j = 1 to m. The voltage applied to the sustain electrodes XA and Yi and the address electrode Aj is
It is generated by the power supply circuit 22, and supplied via the address driver 23, Y common drivers 24A and 24B, scan drivers 25A and 25B, and X common driver 26.
Since sustain electrodes Y1 to Yn are formed in a layer different from that of sustain electrode XA, lead wires can be easily drawn from both ends of sustain electrodes Y1 to Yn, and one end and the other end of sustain electrodes Y1 to Yn are symmetrical to each other. Scan drivers 25A and 25B
The output end of is connected. Accordingly, each sustain electrode Y
The potential gradient on 1 to Yn is reduced, and the display quality is improved. The output end of the X common driver 26 is connected to both ends of the sustain electrode XA in order to make the potential on the sustain electrode XA more uniform. Driver 23, 24A, 24
B, 25A, 25B and 26 are controlled by signals from the control circuit 27. The control circuit 27 outputs this control signal
Display data DATA and display data D supplied from the outside
It is generated based on the dot clock CLK synchronized with ATA, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC. The address driver 23 includes a shift register 2 to which serial display data and shift pulses are supplied from the control circuit 27 to a serial data input terminal and a clock input terminal, respectively.
31, a latch circuit 232 that holds the parallel display data of the shift register 231 when the display data of one row is secured in the shift register 231, and a latch circuit 232.
ON / OFF is determined based on the output of the address electrode drive circuit 233 and the timing of the drive voltage output is controlled by the control signal from the control circuit 27. The m output terminals of the address electrode drive circuit 233 are connected to the address electrodes A1 to Am, respectively. Scan driver 25A
Is a shift register 25A1 in which "1" is supplied to the serial data input terminal in synchronization with the start of the address period in the subfield and a shift pulse synchronized with the address cycle is supplied to the clock input terminal, and the shift register 25A1.
ON / OFF is determined by the output of each bit of the Y drive circuit 25A2, and the timing of the drive voltage output is controlled by the control signal from the control circuit 27. Y drive circuit 2
The output end of 5A2 is connected to one end of sustain electrodes Y1 to Yn. The Y common driver 24A is a Y drive circuit 25A.
2 to supply a common drive voltage to the sustain electrodes Y1 to Yn. The Y common driver 24B and the scan driver 25B have the same configurations as the Y common driver 24A and the scan driver 25A, respectively. FIG. 3 is a waveform diagram of an electrode applied voltage showing an example of the operation of the apparatus of FIG.
It shows subfields. This driving method is an address / sustain discharge separated type self-erasing address method,
One sub-field includes a reset period for keeping the wall charges of all the cells slightly left, and an address period for accumulating the wall charges by the address discharge to the extent that a sustain discharge can be performed later on the pixels to be lit. , The sustain pulse is added to the wall charges to generate the sustain discharge only in the cells in which the address discharge is generated. Hereinafter, the operation after time points a to g in FIG. 3 will be described. (A) In the reset period, in order to make the wall charges of all pixels substantially the same, first, with the sustain electrodes Y1 to Yn set to 0 V, the write pulse of the potential VS + VW is applied to the sustain electrode XA. The potential VW is equal to the sustain electrode XA and the sustain electrode Y.
When the discharge starting voltage between the sustain electrode i and the sustain electrode is Vfxy, it is determined that VS + VW>Vfxy> VW (1) is satisfied, and the full write discharge W between the sustain electrodes XA and the sustain electrodes Y1 to Yn. Occurs. At this time, as the discharge progresses, as shown in FIG. 1, electron wall charges are accumulated on the surface of the MgO protective film 13 above the sustain electrode XA and on the side of the sustain electrodes Y1 to Yn, while the sustain electrode Y1 is stored. Wall charges of positive ions are accumulated on the surface of the MgO protective film 13 above Yn. These wall charges reduce the electric field strength in the discharge space, so that the discharge immediately converges and ends in 1 to several μs. The voltage due to the wall charge at the time of termination is represented by Vwall1. (B) In order to make the wall charges of all pixels more uniform, the sustain electrodes X
With A at 0 V, the potential VS is applied to the sustain electrodes Y1 to Yn.
Sustain pulse is applied. The potential VS is determined so as to satisfy VS + Vwall1>Vf> VS (2), and the entire surface sustain discharge S is generated between the sustain electrode XA and the sustain electrodes Y1 to Yn. As a result, the polarity of the wall charges is opposite to that in the case (a). (C) With the sustain electrodes Y1 to Yn set to 0 V, the potential V
An erase pulse having a potential lower than S is applied to the sustain electrode XA. As a result, a part of the wall charges is neutralized, and the wall charges are reduced. At this time, the negative wall charges remaining above the sustain electrodes Y1 to Yn serve to generate the next address discharge at the low potential VA. The amount of this wall charge needs to be such that no sustain discharge is generated by the sustain pulse during the sustain discharge period for the cells that have not been subjected to the address discharge during the address period. Next, the address period starts. (D) The sustain electrodes XA and Y1 to Yn are set to the potential VS. (E) The sustain electrodes Y1 are selected, that is, the sustain electrodes Y1 to
The scan pulse is applied only to Y1 of Yn, and at the same time, the address pulse of the potential VA is applied to the address electrode Aj only for the cells to be lit in the selected line, thereby causing the write discharge. Hereinafter, sustain electrodes Y2 to Yn are sequentially selected to generate a write discharge. Next, the sustain discharge period starts. (F) The sustain electrodes Y1 to Yn have the same voltage waveform, and sustain pulses are alternately applied to the sustain electrodes XA and Y to turn on the cells to which writing has been performed in the address period. In the first embodiment, since the sustain electrodes Y1 to Yn are closer to the address electrodes A1 to Am than the sustain electrode XA, the voltage of the address pulse can be reduced as compared with the conventional case.
Further, since the sustain electrodes XA are planar, the potential thereof can be made more constant than before, and the display quality is improved. [Second Embodiment] In FIG. 2, as the pixel size becomes smaller, the pitch of sustain electrodes Y1 to Yn becomes smaller, which makes it difficult to connect sustain electrodes Y1 to Yn to scan drivers 25A and 25B. Therefore, in the plasma display device 20A of the second embodiment, as shown in FIG.
Scan drivers 25C and 25 are provided on one end side and the other end side of Yn.
The sustain electrodes Y1 to Yn have odd-numbered one ends connected to the output end of the scan driver 25C, and even-numbered other ends connected to the output end of the scan driver 25D. The other points are the same as in the case of FIG. [Third Embodiment] In the cell of FIG. 1, since wall charges of the same polarity are divided on both sides of the sustain electrode Yi, the electric field strength becomes weaker and the amount of wall charges required for sustain discharge is smaller than that in the case of FIG. I need to do a lot. Therefore, in the cell 10B of the third embodiment, as shown in FIG. 5, in order to perform the surface discharge only between the sustain electrode Yi and the sustain electrode XB on one side of the sustain electrode Yi, the sustain electrode Yi and the sustain electrode Yi are formed. The distance between the sustain electrode XB on the lower side and the non-surface discharge side is made larger than the distance between the sustain electrode Yi and the sustain electrode XB on the surface discharge side. In addition, the sustain electrode Y
By arranging i close to one side of the partition wall 16,
A sufficient surface discharge area is secured on the sustain electrodes XB, and discharge is less likely to occur on the non-surface discharge side. According to the third embodiment, since the wall charges are not divided as described above, the voltage of the address pulse can be made lower than that in the case of FIG. [Fourth Embodiment] In the stepped surface sustain electrode XB of FIG. 5, a portion that does not contribute to discharge between the linear sustain electrode Yi is not necessary. Therefore, in the cell 10C of the fourth embodiment,
As shown in FIG. 6, linear sustain electrodes XC are formed on the glass substrate 11 so as to approach the sustain electrodes Yi so as not to overlap the sustain electrodes Yi and to be parallel to the sustain electrodes Yi. The ends of the sustain electrodes XC have different sustain electrodes XC as indicated by the dotted line.
It is continuous between. That is, the sustain electrode XC has a shape obtained by cutting out a rectangular unnecessary portion from the sustain electrode XA in FIG. The other points are the same as in the case of FIG. In addition,
The present invention is characterized by the configuration of the PDP, and the present invention includes a display device in which the PDP and a driver of various driving methods are combined.

As described above, according to the flat discharge AC type plasma display panel of the present invention, a plurality of linear second electrodes are formed on the first substrate at different heights and spaced from each other. Is provided, the pixel size can be made smaller than that in the conventional configuration in which the first electrode and the second electrode are arranged at the same height, and the display can be made finer. Moreover, since the second electrode is formed in a layer different from that of the first electrode, lead wires can be easily drawn from both ends of the second electrode, and the first and second aspects of the second invention can be easily configured. Has the effect. 1st of 1st invention
According to the aspect, the electric potential of the first electrode can be made more constant than in the case of the line electrode, and the display quality is improved. According to the second aspect of the first invention, there is an effect that the electric field strength due to the wall charges becomes stronger than that of the first aspect. According to the first aspect of the second invention, there is an effect that the potential gradient on the second electrode is reduced and the display quality is improved. According to the second aspect of the second invention, even if the pixel size is small and the pitch of the second electrodes is small, it is possible to easily connect the second electrodes to the scan driver.

[Brief description of drawings]

FIG. 1 is a cell cross-sectional configuration diagram of a flat discharge AC type plasma display panel according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a planar discharge AC type plasma display device according to a first embodiment of the present invention.

FIG. 3 is an electrode applied voltage waveform diagram showing an example of the operation of the apparatus of FIG.

FIG. 4 is a block diagram showing a schematic configuration of a planar discharge AC type plasma display device according to a second embodiment of the present invention.

FIG. 5 is a cell cross-sectional configuration diagram of a flat discharge AC type plasma display panel according to a third embodiment of the present invention.

FIG. 6 is a cell cross-sectional configuration diagram of a flat discharge AC type plasma display panel according to a fourth embodiment of the present invention.

FIG. 7 is a cell cross-sectional configuration diagram of a conventional flat discharge AC type plasma display panel.

[Explanation of symbols]

 10, 10A to 10C cells 11, 14 glass substrate 12 dielectric layer 13 MgO protective film 15 phosphor 16 partition 17 discharge space A1 to Am, Aj address electrodes XA to XC, Y1 to Yn, Yi sustain electrode 20, 20A plasma display apparatus

Claims (6)

[Claims] 1. A plurality of linear second electrodes are arranged on the first substrate at different heights and at a distance from the first electrode, and the linear second electrodes are arranged.
An electrode and the second electrode are covered with a dielectric layer, a second substrate is arranged so as to be spaced apart from the first substrate, and a plurality of electrodes are arranged on the second substrate so as to be spaced apart from and intersect with the second electrode. A third electrode is disposed, a phosphor is adhered to the second substrate side, and a discharge gas is sealed in a space between the first substrate and the second substrate. Discharge AC type plasma display panel. 2. The first electrode is a surface electrode, and
2. The flat discharge AC type plasma display panel according to claim 1, wherein the flat discharge AC type plasma display panel is arranged closer to the first substrate than the second electrode. 3. The first electrode is a plurality of line electrodes arranged parallel to and not overlapping with the second electrode, and end portions of the plurality of line electrodes are connected to each other. The flat discharge AC type plasma display panel according to claim 1. 4. The flat discharge AC type plasma display panel according to claim 1, a scan driver for applying a scan pulse in a line-sequential manner to the plurality of second electrodes, and the third. An address driver that applies an address pulse to the electrode for each scan pulse to accumulate wall charges corresponding to display data in the dielectric layer on the second electrode to which the scan pulse is applied; A planar discharge comprising: a common driver for applying an AC sustain pulse in order to perform a sustain discharge in addition to a voltage due to wall charges on the dielectric layer, between the electrode and the second electrode. AC type plasma display device. 5. The flat discharge AC type plasma display according to claim 4, wherein the scan driver is connected to the second electrodes so as to apply the scan pulse from both ends of each second electrode. apparatus. 6. The scan driver applies the scan pulse from one end side of the odd-numbered second electrodes and applies the scan pulse from the other end side of the even-numbered second electrodes. The flat discharge AC type plasma display device according to claim 4, wherein the flat discharge AC type plasma display device is connected to two electrodes.