JPH0870067A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0870067A JPH0870067A JP6225686A JP22568694A JPH0870067A JP H0870067 A JPH0870067 A JP H0870067A JP 6225686 A JP6225686 A JP 6225686A JP 22568694 A JP22568694 A JP 22568694A JP H0870067 A JPH0870067 A JP H0870067A
- Authority
- JP
- Japan
- Prior art keywords
- film
- passivation film
- semiconductor device
- passivation
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、熱応力による耐湿性の低下を防止する構造の半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure that prevents deterioration of moisture resistance due to thermal stress.
【０００２】[0002]
【従来の技術】従来の半導体装置のパッケージング後の
構造を図２に示す。図２において、半導体基板１６上に
は配線１３やボンディングパット１４が形成され、ボン
ディングパット１４以外の部分は半導体装置を保護する
ためのパッシベーション膜１２によって覆われている。
このパッシベーション膜１２として、通常、シリコン窒
化膜やポリイミド膜などが使用され、シリコン窒化膜の
場合はプラズマＣＶＤ法により形成され、ポリイミド膜
の場合は回転塗布法により形成される。2. Description of the Related Art FIG. 2 shows a structure of a conventional semiconductor device after packaging. In FIG. 2, the wiring 13 and the bonding pad 14 are formed on the semiconductor substrate 16, and the portion other than the bonding pad 14 is covered with the passivation film 12 for protecting the semiconductor device.
As the passivation film 12, a silicon nitride film or a polyimide film is usually used. In the case of a silicon nitride film, it is formed by a plasma CVD method, and in the case of a polyimide film, it is formed by a spin coating method.
【０００３】その後、ダイシング工程に送り、ウェーハ
状の半導体装置をチップ状に分割した後、ダイボンディ
ング工程に送って、リードフレーム１８のダイパット上
にＡｇペースト１７により固着される。そして、ワイヤ
ボンディング工程で、ボンディングパット１４とリード
フレーム１８のリードとをＡｕワイヤ１５で接続した
後、モールド工程に送って、半導体装置全体をエポキシ
樹脂などの封止樹脂１１で封止する。After that, the wafer is sent to a dicing process, the wafer-shaped semiconductor device is divided into chips, and then sent to a die bonding process to be fixed on a die pad of a lead frame 18 with an Ag paste 17. Then, in the wire bonding step, the bonding pad 14 and the lead of the lead frame 18 are connected by the Au wire 15, and then sent to the molding step to seal the entire semiconductor device with the sealing resin 11 such as epoxy resin.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体装置で
は、最上層の配線１３の形成を行った後、ＣＶＤ法や回
転塗布法などでパッシベーション膜１２が形成されるた
め、パッシベーション膜１２の表面は平坦或いは最上層
の配線に沿った形状となる。In the conventional semiconductor device, since the passivation film 12 is formed by the CVD method or the spin coating method after forming the uppermost wiring 13, the surface of the passivation film 12 is The shape is flat or follows the wiring of the uppermost layer.
【０００５】そのため、モールド封止した半導体チップ
をプリント配線基板上に実装する場合、はんだリフロー
工程時に半導体チップ全体が高温にさらされ、封止樹脂
１１とパッシベーション膜１２との熱膨張係数の違いな
どに起因する熱応力により封止樹脂１１とチップとが剥
離し、パッケージクラックが発生してＡｕワイヤ１５が
断線したり、外部からの水分の侵入により配線１３やボ
ンディングパット１４が腐食したりして、半導体装置の
信頼性が低下するという問題があった。Therefore, when mounting a mold-sealed semiconductor chip on a printed wiring board, the entire semiconductor chip is exposed to high temperatures during the solder reflow process, and the difference in the thermal expansion coefficient between the sealing resin 11 and the passivation film 12 is caused. The sealing resin 11 and the chip are separated from each other due to the thermal stress caused by the, and the Au wire 15 is broken due to a package crack, or the wiring 13 and the bonding pad 14 are corroded by the intrusion of moisture from the outside. However, there is a problem that the reliability of the semiconductor device is reduced.
【０００６】そこで、本発明の目的は、半導体チップと
封止樹脂との密着性を向上させた半導体装置を提供する
ことである。Therefore, an object of the present invention is to provide a semiconductor device in which the adhesion between the semiconductor chip and the sealing resin is improved.
【０００７】[0007]
【課題を解決するための手段】上述した課題を解決する
ために、本発明の半導体装置では、半導体装置に形成さ
れたパッシベーション膜に凹凸が付されている。In order to solve the above-mentioned problems, in the semiconductor device of the present invention, the passivation film formed on the semiconductor device is provided with irregularities.
【０００８】[0008]
【作用】半導体装置に形成されたパッシベーション膜に
凹凸が付されているので、半導体チップと封止樹脂との
密着性が向上し、半導体チップと封止樹脂とが剥離する
のを防止できる。Since the passivation film formed on the semiconductor device is provided with irregularities, the adhesion between the semiconductor chip and the sealing resin is improved, and the semiconductor chip and the sealing resin can be prevented from peeling off.
【０００９】[0009]
【実施例】以下、本発明の実施例について図面を参照し
ながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１０】図１は、本発明の一実施例による半導体装
置のパッケージング後の構造を示す概略断面図である。FIG. 1 is a schematic sectional view showing a structure of a semiconductor device according to an embodiment of the present invention after packaging.
【００１１】図１において、半導体基板６上にはＡｌ−
Ｓｉ−Ｃｕなどの配線３やボンディングパット４が形成
され、ボンディングパット４以外の部分は表面に凹凸部
９を有するパッシベーション膜２によって覆われてい
る。このパッシベーション膜２の凹凸部９は、シリコン
窒化膜やポリイミド膜などのパッシベーション材料に応
じたエッチング、例えばウエットエッチングやドライエ
ッチングなどにより形成される。なお、このパッシベー
ション膜２として、シリコン窒化膜やポリイミド膜など
の他、ＰＳＧ膜、Ｐ−ＳｉＯＮ膜、Ｐ−ＳｉＯ膜などを
使用してもよい。In FIG. 1, Al- is formed on the semiconductor substrate 6.
Wiring 3 such as Si—Cu and a bonding pad 4 are formed, and a portion other than the bonding pad 4 is covered with a passivation film 2 having an uneven portion 9 on the surface. The uneven portion 9 of the passivation film 2 is formed by etching according to the passivation material such as a silicon nitride film or a polyimide film, for example, wet etching or dry etching. As the passivation film 2, a PSG film, a P-SiON film, a P-SiO film or the like may be used in addition to a silicon nitride film or a polyimide film.
【００１２】また、パッシベーション膜２上に凹凸部９
を形成する方法として、例えば、パッシベーション膜２
を通常より厚く形成した後、無数の斑点を有するマスク
を用いたフォトリソグラフィー工程によって、パッシベ
ーション膜２上にまだら状のパターンを有するフォトレ
ジストを形成し、そのフォトレジストをマスクとしてパ
ッシベーション膜２の途中まで異方性エッチングを行う
方法によってもよい。Further, an uneven portion 9 is formed on the passivation film 2.
As a method of forming the film, for example, the passivation film 2
Is formed thicker than usual, and then a photoresist having a mottled pattern is formed on the passivation film 2 by a photolithography process using a mask having innumerable spots, and the photoresist is used as a mask in the middle of the passivation film 2. The method may be anisotropic etching.
【００１３】その後、ダイシング工程に送り、ウェーハ
状の半導体装置をチップ状に分割した後、ダイボンディ
ング工程に送って、リードフレーム８のダイパット上に
Ａｇペースト７により固着される。そして、ワイヤボン
ディング工程で、ボンディングパット４とリードフレー
ム８のリードとをＡｕワイヤ１５で接続した後、モール
ド工程に送って、半導体装置全体をエポキシ樹脂やシリ
コン樹脂などの封止樹脂１で封止する。After that, the wafer is sent to a dicing step, the wafer-shaped semiconductor device is divided into chips, and then sent to a die bonding step, and fixed on the die pad of the lead frame 8 with the Ag paste 7. Then, in the wire bonding process, the bonding pad 4 and the lead of the lead frame 8 are connected by the Au wire 15, and then sent to the molding process to seal the entire semiconductor device with the sealing resin 1 such as epoxy resin or silicon resin. To do.
【００１４】この樹脂封止された半導体チップは、その
後のプリント配線基板への実装工程において、はんだリ
フロー時に高温にさらされても、半導体チップと封止樹
脂１との密着性が向上しているので、高温時の熱応力に
より半導体チップと封止樹脂１とが剥離するのを防止で
き、配線３やボンディングパット４が腐食したり、パケ
ージクラックが発生したりすることを抑制できる。な
お、パッシベーション膜２の凹凸部９は半導体チップの
周辺部に形成すると効果的である。This resin-sealed semiconductor chip has improved adhesion between the semiconductor chip and the sealing resin 1 even when exposed to high temperature during solder reflow in the subsequent mounting process on a printed wiring board. Therefore, it is possible to prevent the semiconductor chip and the sealing resin 1 from peeling off due to the thermal stress at high temperature, and it is possible to prevent the wiring 3 and the bonding pad 4 from being corroded and the package crack from being generated. It should be noted that it is effective to form the uneven portion 9 of the passivation film 2 in the peripheral portion of the semiconductor chip.
【００１５】[0015]
【発明の効果】本発明によれば、半導体チップと封止樹
脂との密着性が向上し、半導体チップと封止樹脂とが剥
離するのを防止できるので、外部から水分が侵入するこ
とを防止でき、半導体装置の信頼性が向上する。According to the present invention, the adhesion between the semiconductor chip and the encapsulating resin is improved, and it is possible to prevent the semiconductor chip and the encapsulating resin from peeling off. Therefore, it is possible to prevent moisture from entering from the outside. Therefore, the reliability of the semiconductor device is improved.
【図１】本発明の一実施例による半導体装置のパッケー
ジング後の構造を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention after packaging.
【図２】従来の半導体装置のパッケージング後の構造を
示す概略断面図である。FIG. 2 is a schematic cross-sectional view showing a structure of a conventional semiconductor device after packaging.
１ 封止樹脂 ２ 保護膜 ３ 配線 ４ ボンディングパット ５ Ａｕワイヤ ６ 半導体基板 ７ Ａｇペースト ８ リードフレーム ９ 凹凸部 1 Sealing Resin 2 Protective Film 3 Wiring 4 Bonding Pad 5 Au Wire 6 Semiconductor Substrate 7 Ag Paste 8 Lead Frame 9 Concavo-convex Part
Claims (1)
ン膜に凹凸が付されていることを特徴とする半導体装
置。1. A semiconductor device, wherein a passivation film formed on the semiconductor device is provided with irregularities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6225686A JPH0870067A (en) | 1994-08-26 | 1994-08-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6225686A JPH0870067A (en) | 1994-08-26 | 1994-08-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0870067A true JPH0870067A (en) | 1996-03-12 |
Family
ID=16833208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6225686A Withdrawn JPH0870067A (en) | 1994-08-26 | 1994-08-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0870067A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012199A1 (en) * | 1997-09-03 | 1999-03-11 | Siemens Aktiengesellschaft | Packaged integrated circuit |
| JP2013519235A (en) * | 2010-02-05 | 2013-05-23 | クアルコム，インコーポレイテッド | Die surface treatment to improve bond strength |
| CN109494203A (en) * | 2017-09-12 | 2019-03-19 | 松下知识产权经营株式会社 | Semiconductor device and its manufacturing method |
| CN112447610A (en) * | 2019-09-04 | 2021-03-05 | 三菱电机株式会社 | Semiconductor device and semiconductor element |
| WO2022259289A1 (en) * | 2021-06-07 | 2022-12-15 | 三菱電機株式会社 | Power semiconductor device and method for producing same |
-
1994
- 1994-08-26 JP JP6225686A patent/JPH0870067A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012199A1 (en) * | 1997-09-03 | 1999-03-11 | Siemens Aktiengesellschaft | Packaged integrated circuit |
| JP2013519235A (en) * | 2010-02-05 | 2013-05-23 | クアルコム，インコーポレイテッド | Die surface treatment to improve bond strength |
| CN109494203A (en) * | 2017-09-12 | 2019-03-19 | 松下知识产权经营株式会社 | Semiconductor device and its manufacturing method |
| CN112447610A (en) * | 2019-09-04 | 2021-03-05 | 三菱电机株式会社 | Semiconductor device and semiconductor element |
| JP2021040058A (en) * | 2019-09-04 | 2021-03-11 | 三菱電機株式会社 | Semiconductor device and semiconductor element |
| WO2022259289A1 (en) * | 2021-06-07 | 2022-12-15 | 三菱電機株式会社 | Power semiconductor device and method for producing same |
| JP7224545B1 (en) * | 2021-06-07 | 2023-02-17 | 三菱電機株式会社 | Power semiconductor device and its manufacturing method |
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