JPH0864760A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0864760A JPH0864760A JP19924394A JP19924394A JPH0864760A JP H0864760 A JPH0864760 A JP H0864760A JP 19924394 A JP19924394 A JP 19924394A JP 19924394 A JP19924394 A JP 19924394A JP H0864760 A JPH0864760 A JP H0864760A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- semiconductor device
- frame body
- gel
- wall portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、パワーモジュール型の
半導体装置の信頼性向上に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the reliability of a power module type semiconductor device.
【0002】[0002]
【従来の技術】図12に従来のパワーモジュール半導体
装置の平面図を示し、図13に正面図を示す。図14は
図12のA−A矢視断面図であり、図中の1は冷却フィ
ン、2は絶縁基板、3は半導体素子、4は配線端子、5
は枠体、6はゲル状封止体、7は封止樹脂、8はアルミ
ワイヤーであり、冷却フィン1の上面に絶縁基板2を半
田等でろう付けしている。この絶縁基板2の上には半導
体素子3および配線端子4が設けられ半田等によりろう
付けされている。枠体5は、上記冷却フィン1の周辺部
において冷却フィン1に接着剤等により固着され、この
枠体5内に半導体素子3を外気から遮断するためにゲル
状封止体6を入れ、その上に封止樹脂7を封入して密閉
している。2. Description of the Related Art FIG. 12 shows a plan view of a conventional power module semiconductor device, and FIG. 13 shows a front view thereof. FIG. 14 is a sectional view taken along the line AA of FIG. 12, in which 1 is a cooling fin, 2 is an insulating substrate, 3 is a semiconductor element, 4 is a wiring terminal, and 5 is a wiring terminal.
Is a frame body, 6 is a gel-like sealing body, 7 is a sealing resin, and 8 is an aluminum wire, and the insulating substrate 2 is brazed to the upper surface of the cooling fin 1 with solder or the like. A semiconductor element 3 and a wiring terminal 4 are provided on the insulating substrate 2 and brazed by soldering or the like. The frame body 5 is fixed to the cooling fin 1 at the peripheral portion of the cooling fin 1 with an adhesive or the like, and the gel-like sealing body 6 is placed in the frame body 5 to shield the semiconductor element 3 from the outside air. The sealing resin 7 is sealed on the top.
【0003】[0003]
【発明が解決しようとする課題】上記従来技術の半導体
装置では、封止樹脂硬化時に半導体装置の温度が上昇す
ると、下層のゲル状封止体が膨張し、上層の封止樹脂を
上方向に押し上げる力、及び枠体を横方向に押し広げる
力が作用する。これは、ゲル状封止体の線膨張係数(例
えば3×10-4/℃)が、封止樹脂及び枠体の線膨張係
数(例えば2.4×10-5/℃)に比べてかなり大きいた
めである。このゲル状封止体の膨張により、ゲル状封止
体が枠体内面(封止樹脂との界面)をはい上がる。ゲル
状封止体は、枠体と封止樹脂との接着を阻害するため、
結果として枠体と封止樹脂間の接着面積が低下すること
になる。その後、温度が降下すると封止樹脂が収縮し、
枠体と封止樹脂間が開口し、耐湿性が低下するという問
題が生じる。特にゲル状封止体の量が多い大型のパッケ
ージにおいて顕著となる。In the above-mentioned semiconductor device of the prior art, when the temperature of the semiconductor device rises during the curing of the sealing resin, the lower layer gel-like encapsulant expands and the upper layer encapsulating resin moves upward. A force to push up and a force to push the frame body laterally act. This is because the linear expansion coefficient of the gel encapsulant (eg, 3 × 10 −4 / ° C.) is considerably higher than that of the encapsulating resin and the frame (eg, 2.4 × 10 −5 / ° C.). Because it is big. Due to the expansion of the gel-like sealing body, the gel-like sealing body rises above the inner surface of the frame (interface with the sealing resin). The gel-like encapsulant inhibits the adhesion between the frame and the encapsulating resin,
As a result, the adhesion area between the frame and the sealing resin is reduced. After that, when the temperature drops, the sealing resin shrinks,
There is a problem that the frame is opened between the sealing resin and the moisture resistance is lowered. This is particularly noticeable in a large package having a large amount of gel-like sealing body.
【0004】本発明の目的は、上記の問題を考慮してな
されたものであり、上記のような温度の上昇・降下に伴
う信頼性の低下を防止できる半導体装置を提供すること
にある。An object of the present invention has been made in consideration of the above problems, and it is an object of the present invention to provide a semiconductor device capable of preventing the decrease in reliability due to the rise and fall of temperature as described above.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置で
は、金属基板に枠体を固着し、この枠体内の金属基板上
に、枠体に対向するように壁部を設ける。そして、壁部
内の金属基板上に、表面に導体層を有する絶縁基板を固
着し、この絶縁基板の導体層上に半導体素子、及びSベ
ンドを有する配線端子を設ける。ここで、Sベンドの湾
曲部の高さは壁部の高さよりも低くする。さらに、壁部
内にゲル状封止体を充填するとともに、枠体と壁部の間
に封止樹脂を充填する。In a semiconductor device of the present invention, a frame is fixed to a metal substrate, and a wall is provided on the metal substrate in the frame so as to face the frame. Then, an insulating substrate having a conductor layer on its surface is fixed on the metal substrate in the wall portion, and a semiconductor element and a wiring terminal having an S bend are provided on the conductor layer of this insulating substrate. Here, the height of the curved portion of the S bend is made lower than the height of the wall portion. Further, the gel-like sealing body is filled in the wall portion, and the sealing resin is filled between the frame body and the wall portion.
【0006】[0006]
【作用】本発明によれば、ゲル状封止体は、壁部の内部
にあるので、半導体装置最外部の枠体内面とは、接触し
ない。従って、封止樹脂硬化時において半導体装置の温
度が上昇するときに、従来のようなはい上がりの問題が
無くなるので、封止樹脂と枠体壁面との接着面積が広く
なり接着強度が向上する。従って、温度が降下するとき
に枠体と封止樹脂間の開口しないので、耐湿性が向上す
る。さらに、Sベンドの湾曲部の高さは壁部の高さより
も低いので、壁部内にゲル状封止体を充填したときにS
ベンドの湾曲部はゲル状封止体にある。従って、ゲル状
封止体が膨張・収縮するときに、絶縁基板や半導体素子
及び配線端子に加わる応力を緩和できる。According to the present invention, since the gel-like sealing body is inside the wall portion, it does not come into contact with the innermost frame inner surface of the semiconductor device. Therefore, when the temperature of the semiconductor device rises during curing of the sealing resin, there is no problem of rising in the past, so that the bonding area between the sealing resin and the frame wall surface is widened and the bonding strength is improved. Therefore, when the temperature drops, there is no opening between the frame and the sealing resin, so the moisture resistance is improved. Furthermore, since the height of the curved portion of the S bend is lower than the height of the wall portion, when the gel-like sealing body is filled in the wall portion, S
The bend of the bend is in the gel encapsulant. Therefore, the stress applied to the insulating substrate, the semiconductor element, and the wiring terminal can be relieved when the gel-like sealant expands and contracts.
【0007】以上により、温度の上昇・降下に伴う半導
体装置の信頼性の低下を防止できる。As described above, it is possible to prevent the reliability of the semiconductor device from being lowered due to the temperature rise and fall.
【0008】[0008]
(実施例1)図1は本発明の第1の実施例の側面断面図
を示し、図2はその半導体装置の正面断面図を示す。
尚、枠体5以外の半導体装置の構造は、従来例と同一の
ものである。図3に枠体の平面図を示し、図4は図3の
B−B断面図である。(Embodiment 1) FIG. 1 shows a side sectional view of a first embodiment of the present invention, and FIG. 2 shows a front sectional view of the semiconductor device.
The structure of the semiconductor device other than the frame 5 is the same as that of the conventional example. FIG. 3 shows a plan view of the frame body, and FIG. 4 is a sectional view taken along line BB of FIG.
【0009】合成樹脂成形品など絶縁材料からなる枠体
5は、金属基板である冷却フィン1の上部に接着され、
内部の各部品を囲い上部を開口している。枠体5の内側
には、この枠体5より高さが低い壁部として仕切板9
を、枠体5の長手方向の壁部5−a,5−bにわたって
これとほぼ対向させ形成し、これにより仕切板9と枠体
5との間に所定の厚さの空間部10,11が形成され
る。仕切板9の内側には、絶縁基板2が冷却フィン上に
半田付けされる。図示されてはいないが、絶縁基板2の
表面には導体層が設けられ、その導体層に半導体素子3
及び配線端子4が半田付けされる。配線端子4が半田付
けする導体層と半導体素子は、アルミワイヤー8により
接続されている。ここで、配線端子4はSベンド20を
持っており、その湾曲部21は仕切板9の高さよりも低
くしてある。なお、図2では一つの配線端子のみについ
てSベンド部を記載し、他の配線端子については記載を
省略している。A frame 5 made of an insulating material such as a synthetic resin molded product is adhered to the upper portion of the cooling fin 1 which is a metal substrate,
It surrounds each internal part and has an open top. A partition plate 9 is provided inside the frame body 5 as a wall portion having a height lower than that of the frame body 5.
Are formed so as to substantially face the longitudinal wall portions 5-a and 5-b of the frame body 5, and thereby the space portions 10 and 11 having a predetermined thickness are provided between the partition plate 9 and the frame body 5. Is formed. The insulating substrate 2 is soldered on the cooling fins inside the partition plate 9. Although not shown, a conductor layer is provided on the surface of the insulating substrate 2, and the semiconductor element 3 is provided on the conductor layer.
And the wiring terminal 4 is soldered. The conductor layer to which the wiring terminal 4 is soldered and the semiconductor element are connected by an aluminum wire 8. Here, the wiring terminal 4 has an S bend 20, and the curved portion 21 thereof is lower than the height of the partition plate 9. In FIG. 2, the S bend portion is shown only for one wiring terminal, and the other wiring terminals are omitted.
【0010】このような半導体装置において、ゲル状封
止体6を仕切板9の内側に充填した後、上層に封止樹脂
7を充填し硬化する。この場合、封止樹脂7は空間部1
0,11へも自動的に充填される。本実施例において
は、注入されたゲル状封止体6の高さが仕切板9の高さ
より低いので、仕切板9の内壁、すなわちゲル状封止体
6と接触する側の壁面にも封止樹脂が接着する。これ
は、ケースと封止樹脂の密着性の向上に寄与している。In such a semiconductor device, after the gel-like sealing body 6 is filled inside the partition plate 9, the sealing resin 7 is filled in the upper layer and cured. In this case, the sealing resin 7 is the space 1
It is automatically filled to 0 and 11. In this embodiment, since the height of the injected gel-like sealing body 6 is lower than the height of the partition plate 9, the inner wall of the partition plate 9, that is, the wall surface on the side in contact with the gel-like sealing body 6 is also sealed. Stop resin adheres. This contributes to the improvement of the adhesion between the case and the sealing resin.
【0011】本実施例の半導体装置において、枠体5内
に封入された下層のゲル状封止体6が温度上昇により熱
膨張しても、仕切板9を設けることにより、枠体内壁で
のゲル状封止体6のはい上がりは防止される。また、こ
のケースの構造では、前述したように枠体5と仕切板9
との空間部10,11に封止樹脂7が封入され、ゲル状
封止体6を封止樹脂7により密閉するような形となり、
枠体5と封止樹脂7の接着面積が従来の二倍以上広くな
る。さらに本構造にすることで、従来構造と比べゲル状
封止体6の量を低減でき、温度変化に伴うゲル状封止体
6の熱膨張により発生する内圧低減が実現できる。以上
により、枠体5と封止樹脂7間の開口が無くなる。ま
た、この二重構造ケースの半導体装置により、水分の侵
入経路が長くなるため、さらに耐湿性向上の面において
有効である。さらに、配線端子4のSベンド20の湾曲
部がゲル状封止体6内に入っているので、ゲル状封止体
6が膨張・収縮するときに、絶縁基板2,半導体素子
3,配線端子4に加わる応力を緩和できる。以上のよう
に、本実施例によれば信頼性の高い半導体装置が得られ
る。In the semiconductor device of this embodiment, even if the lower layer gel-like encapsulating body 6 enclosed in the frame body 5 is thermally expanded due to a temperature rise, the partition plate 9 is provided so that the inner wall of the frame body is protected. The rising of the gel-like sealing body 6 is prevented. Further, in the structure of this case, as described above, the frame body 5 and the partition plate 9 are
The sealing resin 7 is sealed in the space portions 10 and 11 of and, and the gel-like sealing body 6 is sealed by the sealing resin 7.
The bonding area between the frame body 5 and the sealing resin 7 is more than twice as wide as the conventional one. Further, with this structure, the amount of the gel-like sealing body 6 can be reduced compared to the conventional structure, and the internal pressure generated by the thermal expansion of the gel-like sealing body 6 due to the temperature change can be reduced. As described above, the opening between the frame body 5 and the sealing resin 7 is eliminated. In addition, the semiconductor device having the double-structured case has a longer moisture intrusion path, which is further effective in improving the moisture resistance. Furthermore, since the curved portion of the S bend 20 of the wiring terminal 4 is inside the gel-like sealing body 6, when the gel-like sealing body 6 expands and contracts, the insulating substrate 2, the semiconductor element 3, the wiring terminal The stress applied to 4 can be relaxed. As described above, according to this embodiment, a highly reliable semiconductor device can be obtained.
【0012】図5及び図6は実施例1の変形例である。
本実施例では、仕切板9は別ピースで枠体5と嵌合させ
ている。この場合は枠体5の内壁に凸部5−c,凹部5
−d等を設けることで作業性,設置位置精度等が向上す
る。また、この場合の仕切板9は金属性のものにし、薄
肉化をすることで半導体装置の小形化を図ることも考え
られる。5 and 6 are modifications of the first embodiment.
In this embodiment, the partition plate 9 is fitted to the frame body 5 as a separate piece. In this case, the convex portion 5-c and the concave portion 5 are formed on the inner wall of the frame body 5.
By providing -d etc., workability, installation position accuracy, etc. are improved. Further, in this case, it is considered that the partition plate 9 is made of metal and is made thin so that the semiconductor device can be miniaturized.
【0013】(実施例2)図7は本発明の第2の実施例
の側面断面図である。図8は本実施例の枠体の断面図で
あり、平面図は図3と同等である。本実施例では、実施
例1の効果のほかに、枠体5と仕切板9を冷却フィン1
側でつなげることにより枠体及び仕切板の強度が向上す
るという効果がある。(Second Embodiment) FIG. 7 is a side sectional view of a second embodiment of the present invention. FIG. 8 is a cross-sectional view of the frame body of this embodiment, and its plan view is the same as FIG. In this embodiment, in addition to the effect of the first embodiment, the frame 5 and the partition plate 9 are connected to the cooling fin 1.
By connecting them on the side, there is an effect that the strength of the frame body and the partition plate is improved.
【0014】(実施例3)図9は本発明の第3の実施例
である。図10は図9のC−C断面図である。枠体5の
内側に枠状壁面12を設ける二重枠体方式にすることに
より、全周に空間部が形成され、実施例1よりさらに耐
湿性が向上する。(Embodiment 3) FIG. 9 shows a third embodiment of the present invention. FIG. 10 is a sectional view taken along line CC of FIG. By adopting the double frame system in which the frame-shaped wall surface 12 is provided inside the frame 5, a space portion is formed on the entire circumference, and the moisture resistance is further improved as compared with the first embodiment.
【0015】(実施例4)図11は本発明の第4の実施
例であり、枠体の断面図を示す。平面図は実施例3の図
9と同等である。本実施例では、実施例3と同等の耐湿
性を持っているほかに、実施例3と同様に枠体及び壁部
の強度が向上するという効果がある。(Embodiment 4) FIG. 11 shows a fourth embodiment of the present invention and is a sectional view of a frame body. The plan view is the same as FIG. 9 of the third embodiment. In addition to having moisture resistance equivalent to that of the third embodiment, the present embodiment has the effect of improving the strength of the frame body and the wall portion similarly to the third embodiment.
【0016】[0016]
【発明の効果】本発明によれば、半導体装置において、
温度の上昇・降下に伴う信頼性の低下を防止できる。According to the present invention, in a semiconductor device,
It is possible to prevent a decrease in reliability due to temperature rise / fall.
【図1】本発明の第1の実施例の側面断面図。FIG. 1 is a side sectional view of a first embodiment of the present invention.
【図2】第1の実施例の半導体装置の正面断面図。FIG. 2 is a front cross-sectional view of the semiconductor device according to the first embodiment.
【図3】枠体の平面図。FIG. 3 is a plan view of a frame body.
【図4】図3のB−B断面図。4 is a sectional view taken along line BB of FIG.
【図5】実施例1の変形例。FIG. 5 is a modification of the first embodiment.
【図6】実施例1の変形例。FIG. 6 is a modification of the first embodiment.
【図7】本発明の第2の実施例の側面断面図。FIG. 7 is a side sectional view of the second embodiment of the present invention.
【図8】実施例2の枠体の断面図。FIG. 8 is a cross-sectional view of the frame body according to the second embodiment.
【図9】本発明の第3の実施例。FIG. 9 is a third embodiment of the present invention.
【図10】図9のC−C断面図。10 is a sectional view taken along line CC of FIG.
【図11】本発明の第4の実施例。FIG. 11 is a fourth embodiment of the present invention.
【図12】従来のパワーモジュール半導体装置の平面
図。FIG. 12 is a plan view of a conventional power module semiconductor device.
【図13】従来のパワーモジュール半導体装置の正面
図。FIG. 13 is a front view of a conventional power module semiconductor device.
【図14】図12のA−A矢視断面図。14 is a cross-sectional view taken along the line AA of FIG.
1…冷却フィン、2…絶縁基板、3…半導体素子、4…
配線端子、5…枠体、6…ゲル状封止体、7…封止樹
脂、8…アルミワイヤー、9…仕切板、10,11…空
間部、12…枠状壁面、20…Sベンド。1 ... Cooling fin, 2 ... Insulating substrate, 3 ... Semiconductor element, 4 ...
Wiring terminals, 5 ... Frame body, 6 ... Gel-like sealing body, 7 ... Sealing resin, 8 ... Aluminum wire, 9 ... Partition plate, 10, 11 ... Space part, 12 ... Frame wall surface, 20 ... S bend.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 紙田 行雄 茨城県日立市幸町三丁目1番1号 株式会 社日立製作所日立工場内 (72)発明者 茂村 達也 茨城県日立市幸町三丁目1番1号 株式会 社日立製作所日立工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Kamada 3-1-1, Saiwaicho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi factory (72) Inventor Tatsuya Shigemura 3-chome, Hitachi-shi, Ibaraki No. 1 No. 1 Stock Company Hitachi Ltd. Hitachi factory
Claims (5)
ける壁部と、 壁部内において金属基板上に固着され、表面に導体層を
有する絶縁基板と、 導体層上にはんだ付けされる、半導体素子、及びSベン
ドを有する配線端子と、を備え、 Sベンドの湾曲部の高さを壁部の高さよりも低くし、 壁部内にゲル状封止体を充填し、 枠体と壁部の間に封止樹脂を充填することを特徴とする
半導体装置。1. A metal substrate to which a frame body is fixed, a wall portion provided on the metal substrate so as to face the frame body in the frame body, and a conductor layer fixed to the metal substrate in the wall portion and having a conductor layer on the surface. An insulating substrate having a semiconductor element and a wiring terminal having an S bend, which is soldered on the conductor layer, are provided, and the height of the curved portion of the S bend is made lower than the height of the wall portion, A semiconductor device characterized in that a gel-like sealing body is filled, and a sealing resin is filled between the frame body and the wall portion.
部を位置決め嵌合するための凹部又は凸部を前記枠体内
壁に有することを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a concave portion or a convex portion for positioning and fitting the wall portion is provided on the inner wall of the frame.
と枠体とを一体形成したことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the wall portion and the frame body are integrally formed.
の高さが枠体の高さより低いことを特徴とする半導体装
置。4. The semiconductor device according to claim 1, wherein the height of the wall portion is lower than the height of the frame body.
が枠状であること特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein the wall portion has a frame shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19924394A JPH0864760A (en) | 1994-08-24 | 1994-08-24 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19924394A JPH0864760A (en) | 1994-08-24 | 1994-08-24 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0864760A true JPH0864760A (en) | 1996-03-08 |
Family
ID=16404554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19924394A Pending JPH0864760A (en) | 1994-08-24 | 1994-08-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0864760A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015156466A (en) * | 2014-01-17 | 2015-08-27 | ローム株式会社 | Power module and manufacturing method of the same |
JP2017174869A (en) * | 2016-03-18 | 2017-09-28 | 富士電機株式会社 | Semiconductor device and method of manufacturing the same |
-
1994
- 1994-08-24 JP JP19924394A patent/JPH0864760A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015156466A (en) * | 2014-01-17 | 2015-08-27 | ローム株式会社 | Power module and manufacturing method of the same |
JP2017174869A (en) * | 2016-03-18 | 2017-09-28 | 富士電機株式会社 | Semiconductor device and method of manufacturing the same |
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