JPH0864686A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a semiconductor device and its manufacturing method wherein breakdown strength is assured and ON resistance is reduced at the same time. CONSTITUTION: An N-type semiconductor substrate 11 (the first semiconductor substrate), element formation side, and a P-type semiconductor substrate 12 (the second semiconductor substrate), a supporting substrate, are Joined together directly, and further, at a joint interface 216 of the direct joint area, a doping layer 202 (a doping layer), a P-type high concentration layer, is formed. A horizontal DMOS 201 is formed on a direct joint area 200 of a part SOI substrate formed with the N-type semiconductor substrate 11 and the P-type semiconductor substrate 12, and farther, a source diffusion layer 204 (well area) is so formed that it reaches a PN joint interface 203 formed betweerj the doping layer 202 and the N-type semiconductor substrate 11, the element formation substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a predetermined place in a semiconductor substrate is separated by an insulator and a method of manufacturing the same, and its application is, for example, a plurality of power elements and their control circuits. It is suitable for use in a semiconductor device for an intelligent power IC integrated on one chip.

[0002]

2. Description of the Related Art Conventionally, the purpose has been to prevent noise and reduce size.
As an IC (semiconductor device), using an SOI substrate
There is an IC in which a dielectric is separated by insulation. In recent years, this
Power element with current performance of 1 to 3 A class in structured IC
Lateral MOSFET (Metal-Oxide-Semiconduct)
or Feild-Effect-Transistor) power devices (LDMOS, L
(IGBT etc.) are being integrated. Figure 9 is a dielectric
Form a lateral MOSFET (LDMOS) 201 on a separate substrate
It is an example of the formed IC. This is a dielectric separated N^-
Region 207 has a low resistance N⁺Forming a region 210,
N^-P-type impurities are implanted into the region 207 twice.
P well layer 209 (deep P well layer 2091, shallow P well
Well layer 2092) is formed in the P well layer 209.
Low resistance P ⁺Region 212, low resistance N⁺Forming region 213
To do. And the low resistance N⁺Region 210 and the P well
Low resistance N in layer 209⁺LOCOS between area 213
An oxide film 214 and a gate oxide film 215 are formed, and
The gate to create a channel in the channel region 208
Gate on oxide film 215 and LOCOS oxide film 214
It is a lateral MOSFET in which an electrode 205 is formed.

Here, a lateral MOSFET as shown in FIG.
When a reverse bias is applied to the P well layer 209, that is, when a positive bias is applied to the low resistance N ⁺ region 210 with respect to the P well layer 209, a potential distribution is generated around the P well layer 209. FIG. 10 is a diagram showing a potential distribution when a reverse bias is applied to the MOSFET of FIG. The same potential difference is applied between the equipotential lines. As shown in FIG. 10, the equipotential lines are closer to each other as they approach the P well layer 209, and the potential distribution becomes closer even near the corners of the shallow P well layer 2092 where the channel region 208 is formed. I know that

[0004]

That is, in the lateral MOSFET as shown in FIG. 9 or FIG. 10, a very high electric field (= potential difference ÷ distance) near the corner of the shallow P well layer 2092 where the channel region 18 is formed. Is hanging. By the way, the distance of the channel region 18, that is, the channel length Lg, is proportional to the diffusion depth of the shallow P well layer 2092. Therefore, if the distance of the channel region 18, that is, the channel length Lg is small, the shallow P well layer 2092 is formed.
The diffusion depth of is deeper, which causes the corner radius of curvature to be smaller and higher voltage is applied. As a result, breakdown (dielectric breakdown) easily occurs even at a low voltage. Therefore, in the IC having the structure as shown in FIG. 9, the PN junction depth of the P well layer 209, which is the source diffusion layer, is made sufficiently deep and the buried N ⁺ layer 220 is formed in order to secure the necessary breakdown voltage. There must be sufficient distance between them. That is, in order to secure the necessary breakdown voltage, Lg must be increased.

However, in the power element for electric power,
It is necessary to reduce the on-resistance to control a large current,
For that purpose, the channel length Lg needs to be shortened, but in the IC as shown in FIG. 9, the channel length Lg cannot be shortened and the on-resistance cannot be reduced for the above reason. That is, when an attempt is made to form a power element on the dielectric isolation substrate as shown in FIG. 9, there is a problem that it is not possible to simultaneously secure the breakdown voltage and reduce the ON resistance. Furthermore, SiO that is usually used as a dielectric
_Since the thermal conductivity of ₂ is smaller than that of Si, the heat generated by the power element or the like cannot escape to the substrate, and the heat is trapped. As a result, the performance of the power element deteriorates,
Further, there is a problem that the upper limit of the operating temperature range is lowered.

An object of the present invention is to obtain a semiconductor device which can simultaneously achieve a high breakdown voltage and a low on-resistance and which does not deteriorate the heat dissipation of a power element, and a manufacturing method thereof.

[0007]

A semiconductor device according to claim 1, which is configured to achieve the above object, has a first conductivity type ground to a predetermined thickness from a bonding interface to a main surface for element formation. Of the first semiconductor substrate and the first semiconductor substrate are bonded together so as to form a PN junction at the bonding interface, and the second conductivity type second semiconductor substrate is bonded to the first semiconductor substrate at the bonding interface. A doping layer of a second conductivity type having a higher impurity concentration than that of the second semiconductor substrate, formed on both sides of the bonding interface, and the doping from the element formation main surface side of the first semiconductor substrate. A second conductivity type well region formed to reach the layer, a first conductivity type source region formed in the well region, and a source electrode connected to the well region and the source region, The first semiconductor A drain electrode connected to the substrate,
A gate electrode formed on an element-forming main surface of the first semiconductor substrate via an insulating film so as to form a channel between the source region and the drain electrode in the well region. It is characterized by that.

A semiconductor device according to claim 2 configured to achieve the above object is the semiconductor device according to claim 1, wherein the semiconductor device is formed on the first semiconductor substrate for forming the element. It is formed by separating the first semiconductor substrate by the insulating separation groove and a plurality of insulating separation grooves formed from a plurality of insulating layers from the main surface to the bonding interface, and is surrounded by the insulating separation groove and the bonding interface. And a PN isolation region separated by the PN junction, wherein the doping layer is
The well region is formed on both sides of the junction interface of the PN isolation region with the junction interface interposed therebetween.
It is characterized in that it is formed so as to reach the doping layer from the element forming main surface side in the PN isolation region.

The semiconductor device according to claim 3 configured to achieve the above object is the semiconductor device according to claim 1, wherein the impurity concentration in the doping layer is 1 × 10 ^17. It is characterized by being cm ^-3 or more. Claim 4 configured to achieve the above object.
The method of manufacturing a semiconductor device according to Item 4, the surface polishing step of mirror-polishing at least one surface of a first conductivity type first semiconductor substrate and mirror-polishing at least one surface of a second conductivity type second semiconductor substrate. An impurity adding step of adding a high-concentration impurity of the second conductivity type from one mirror-polished main surface side of the first semiconductor substrate or the second semiconductor substrate; and the mirror-polished first semiconductor substrate. Ta one main surface and the second
A substrate bonding step of directly bonding the mirror-polished one main surface of a semiconductor substrate, and the first and second directly bonded
A heat treatment step of heating the semiconductor substrate in an oxidizing atmosphere to diffuse the impurities into the first and second semiconductor substrates to form a doping layer, and leaving the first semiconductor substrate to have a predetermined thickness from a bonding interface. A grinding and polishing step of grinding and polishing; a well area forming step of adding a second conductivity type impurity to form a well area from the ground and polished surface side of the first semiconductor substrate to the doping layer; A first conductivity type source region is formed in the region, and a source electrode is formed from above the well region to the source region;
Forming a drain electrode on the first semiconductor substrate;
And a transistor forming step of forming a gate electrode on the element-forming main surface of the first semiconductor substrate with an insulating film interposed therebetween.

According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, which is configured to achieve the above object.
The method of manufacturing a semiconductor device according to claim 1, wherein the impurity addition step is performed by the mirror polishing of the second semiconductor substrate.
This is a step of adding an impurity from the main surface side, and the impurity concentration is such that the impurity concentration at the junction interface of the doping layer formed in the doping layer forming step is
The feature is that it is set to be 1 × 10 ¹⁷ cm ⁻³ or more.

[0011]

According to the semiconductor device of the present invention having the above structure, since the well region and the doping layer are electrically connected to each other, the boundary between the first semiconductor substrate and the well region and the first semiconductor substrate The boundary with the doping layer becomes substantially equipotential. As a result, the equipotential line spreads around the drain electrode, and the potential distribution near the channel region becomes rough. Since the breakdown voltage is ensured by the rough potential distribution, it is not necessary to take a long channel length. And
By reducing the channel length, the on-resistance can be reduced. That is, it is possible to simultaneously secure the breakdown voltage and reduce the on-resistance. Further, unlike the conventional case, there is no dielectric having a small thermal conductivity at the bonding interface, so that the heat dissipation of the power element is not deteriorated.

According to the semiconductor device of the second aspect, since the doping layer is formed on both sides of the junction interface of the PN isolation region with the junction interface interposed therebetween, the doping layer can be easily formed. be able to. According to the method of manufacturing a semiconductor device according to claim 4, before bonding the first and second semiconductor substrates, one of the main surfaces of the mirror-polished main surfaces of the first and second semiconductor substrates is bonded. A second conductivity type high-concentration impurity is added thereto, and then a heat treatment is performed to diffuse the impurity to form a doping layer. Therefore,
A doping layer can be easily formed at the junction interface of the PN isolation region.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device which is an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a semiconductor device according to this embodiment. In addition,
The same parts as those of the conventional structure are designated by the same numbers as in FIG. In this embodiment, the N type corresponds to the first conductive type and the P type corresponds to the second conductive type. In the partial SOI substrate 200 used in this embodiment, the N-type semiconductor substrate 11 (first semiconductor substrate) on the element formation side and the P-type semiconductor substrate 12 (second semiconductor substrate) on the support substrate are directly bonded, and The bonding interface 216 in the direct bonding region is provided on both sides of the bonding interface 216 with the bonding interface 216 interposed therebetween, and the doping layer 20 of the P-type high-concentration layer is formed.
2 (doping layer) is formed. And in this embodiment, the N-type semiconductor substrate 11 and the P-type semiconductor substrate 12 are
The lateral DMOS 201 is formed in the direct junction region 200 of the partial SOI substrate formed by and reaches the PN junction interface 203 formed between the doping layer 202 and the N-type semiconductor substrate 11 which is the element formation substrate. Thus, the source diffusion layer 204 (well region) is formed.

[0014] The lateral DMOS201 is, n ⁺ source region 213 formed in the source diffusion layer 204, p ⁺ region 212, a source electrode formed over the upper source region 213 to the p ⁺ region 212, a source diffusion layer 204 It comprises a gate electrode 205 in which a channel region 208 is formed, and a drain electrode formed on the N-type semiconductor substrate 11. In this structure, when a reverse high voltage is applied between the source and the drain when the film thickness of the element formation substrate is in an appropriate range, the depletion layer of the PN junction 203 and the gate electrode 205 on the surface produce a synergistic effect. The high electric field is alleviated, the interval between equipotential lines 206 is widened as shown in FIG. 8, and as a result, the breakdown voltage is improved.

In this structure, when a reverse high voltage is applied between the source and the drain when the film thickness of the element formation substrate is in an appropriate range, the depletion layer of the PN junction 203 and the gate electrode 205 on the surface are formed. Due to the synergistic effect, the high electric field is alleviated and the interval between the equipotential lines 206 is widened as shown in FIG. 8 and as a result the breakdown voltage is improved. That is, since the source diffusion layer 204 and the doping layer 202 are electrically connected,
The boundary between the N-type semiconductor substrate 11 and the source diffusion layer 204 and the boundary between the N-type semiconductor substrate 11 and the doping layer 202 are substantially equipotential. As a result, the equipotential line spreads around the drain electrode, and the potential distribution near the channel region becomes rough. Since the breakdown voltage is ensured by roughening the potential distribution, it is not necessary to make the diffusion depth of the shallow P well in which the channel is formed large, and therefore it is not necessary to make the channel length large. Then, the ON resistance can be reduced by reducing the channel length.
That is, it is possible to simultaneously secure the breakdown voltage and reduce the on-resistance.

The thickness of the N ⁻ region 207 depends on the guaranteed breakdown voltage, but is about 3 μm when it is around 60V. Therefore, the diffusion depth of the source diffusion layer 204 may be about 3 μm, and the diffusion depth of the shallow P well that determines the lateral spread of the channel region 208 may be about 1 μm. As a result, the channel length Lg, which is the length of the channel region 208, may be reduced. It becomes possible to shorten the resistance, and the resistance component of the channel region when the lateral DMOS transistor 201 is in the ON state is reduced. Further, since the interval between the equipotential lines 206 is widened and the electric field strength is relaxed,
The impurity concentration of the drift region 211, which is a carrier path, can be increased accordingly, and as a result, the resistance of the drift region can be reduced. From these results, horizontal D
It is possible to reduce the ON resistance of the MOS (the resistance in the ON state).

In addition, in this structure, since the lateral DMOS, which is a power element, is directly formed in the junction region, the heat generated in the power element has good thermal conductivity in the P-type semiconductor substrate 12.
Since the heat is transmitted without passing through the oxide film layer which hinders heat conduction on the way, the heat dissipation is good. Next, a method of manufacturing the partial SOI substrate 200 and the semiconductor device according to this embodiment will be described with reference to FIGS. First, a concave portion 224 is formed on the mirror-polished surface of the N-type semiconductor substrate 11 by the method disclosed in Japanese Patent Application Laid-Open No. 2-96350 at a place where the SOI isolation region 301 will be formed in the future by using a normal photo process and a dry etching technique of Si. Form. Next, trenches 225, which are deeper than the recesses 224 and open to the side surfaces of the N-type semiconductor substrate 11, are formed in both end portions of the recesses 224 of the N-type semiconductor substrate 11 and portions where the elements are separated (FIG. 2). Next, the same N-type impurity atom (for example, As ⁺ ) as the N-type semiconductor substrate 11 is implanted into the mirror-polished surface of the N-type semiconductor substrate 11 in which the recesses 224 are formed by using an ion implantation method or the like (FIG. 3). . Here, N-type impurity atoms such as As ⁺ are implanted at about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ . next,
The P-type semiconductor substrate 12 is formed on the mirror-polished surface of the P-type semiconductor substrate 12.
The same P-type impurity atom (for example, B ⁻ ) is implanted using the ion implantation method or the like (FIG. 4). Next, the N-type semiconductor substrate 11
The mirror-polished surfaces of the P-type semiconductor substrate 12 are directly bonded to each other to form a bonded substrate (FIG. 5). Next, this bonded substrate is heated in an oxidizing atmosphere to form an oxide film in the space surrounded by the recess 224 and the P-type semiconductor substrate 12, and the space is filled with the oxide film (FIG. 6). At this time, oxygen or the like enters from the groove 225 opened on the side surface of the N-type semiconductor substrate 11 to oxidize the inside. At this time, in the above (FIG. 3), the impurity atoms injected into the bonding surface of the N-type semiconductor substrate 11 are diffused vertically and horizontally by the high temperature heat treatment at the time of bonding and buried oxidation, and the doping layer 202, the shield layer of the SOI region, etc. Is formed. After the joint substrate is formed in this manner, the N-type semiconductor substrate 11 is ground from the side opposite to the joint surface so as to leave a predetermined thickness from the joint surface and expose the groove 225.
Polishing is performed to obtain a partial SOI substrate 200 (FIG. 7). After that, according to a normal device process, the SOI isolation region 3
A logic element such as a CMOS is connected to a PN isolation region (Si-S
A power element such as DMOS is formed in the i direct junction region (FIG. 7).

In the above embodiment, the ion implantation was performed corresponding to the region which will be the PN isolation region 302 in the future in FIG. 4, but instead of this, the ion implantation is performed over the entire mirror side of the P-type semiconductor substrate 12. You may. In this case, the doping region 202 is entirely formed in the P-type semiconductor substrate 12 along the bonding interface between the P-type semiconductor substrate 12 and the N-type semiconductor substrate 11.

The structure of FIG. 1 may also be created as follows. That is, first, the N-type semiconductor substrate 1
P-type impurities are implanted into the mirror-polished surface of No. 1 at a high concentration at a shallow position from the surface by an ion implantation method. The implantation depth at this time is, for example, Average Projection Ra
inge) Rp = approximately 200 nm, injection amount is 1 per unit area
It is 0 ¹⁵ to 10 ¹⁶ cm ^-2 . Next, according to the method shown in FIG. 2, a recess 224 is formed in the ion implantation surface by a dry etching method such as RIE using an insulating film such as an oxide film as a mask. At this time, the etching depth is about 300
nm, and as a result, the implanted impurity ions are completely removed in the region 224 where the concave portion is formed. Next, in this state, while leaving an insulating film such as an oxide film, which is a mask, by implanting N-type impurity ions this time, a shield layer of the first conductivity type can be selectively formed only in the recess 224. it can. Next, a groove 2 deeper than the recess 224 is formed in the same manner as in FIG.
25 is formed. After that, a partial SOI substrate is formed according to the method of FIGS. 4 to 7, and then the semiconductor device shown in FIG. 1 is obtained according to a normal device process.

The structure of FIG. 11 may also be created as follows. That is, P as the P-type semiconductor substrate 12
2 and FIGS. 4 to 6 described above using a high impurity concentration type substrate.
Method. Through this step, the high-concentration impurities in the P-type semiconductor substrate 12 are diffused upward in the direct junction and enter the N-type N-type semiconductor substrate 11 so that P
An N junction is formed. After that, the semiconductor device shown in FIG. 1 is obtained according to a normal device process.

According to the method of manufacturing a semiconductor device described above, before the N-type and P-type semiconductor substrates are bonded,
The doping layer 2 is formed by adding a high concentration P-type impurity from any one of the mirror-polished main surfaces of the P-type semiconductor substrate and then performing a heat treatment to diffuse the impurity.
02 is formed. Therefore, the doping layer 202 can be easily formed at the junction interface of the PN isolation region.

The numerical values in the embodiments are not limited to the described values and may be arbitrarily changed.

[0023]

According to the semiconductor device of the first aspect,
Since the breakdown voltage is secured by the coarse potential distribution, it is not necessary to take a long channel length, and the ON resistance can be reduced by reducing the channel length. Therefore, it is possible to simultaneously secure the breakdown voltage and reduce the ON resistance. In addition, since there is no dielectric having a small thermal conductivity at the bonding interface as in the conventional case, it is possible to prevent the heat dissipation of the power element from lowering.

According to the semiconductor device of the second aspect, this doping layer can be easily formed. According to the semiconductor device manufacturing method of the fourth aspect, the doping layer can be easily formed at the junction interface of the PN isolation region.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 4 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 5 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 6 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 7 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1;

8 is a diagram showing a potential distribution of the semiconductor device shown in FIG.

FIG. 9 is a diagram showing a semiconductor device using a conventional semiconductor device.

10 is a diagram showing a potential distribution of the semiconductor device shown in FIG.

[Explanation of symbols]

11 N-type semiconductor substrate (first semiconductor substrate) 12 P-type semiconductor substrate (second semiconductor substrate) 200 SOI substrate 201 lateral DMOS 202 doping layer (doping layer) 203 PN junction interface 204 source diffusion layer (well region) 205 gate electrode 206 equipotential line 207 N ⁻ region 208 channel region 209 P well layer 211 drift region 212 p ⁺ region 213 source region 216 junction interface 224 recess 225 deep groove

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/78 H01L 29/78 301 W

Claims (5)

[Claims] 1. A first semiconductor substrate of a first conductivity type polished to a predetermined thickness from a bonding interface to a main surface for element formation, and a PN junction is formed at the bonding interface with the first semiconductor substrate. And a second semiconductor substrate of a second conductivity type formed on both sides of the second semiconductor substrate of a second conductivity type and the bonding interface of the first semiconductor substrate with the bonding interface sandwiched therebetween. A doping layer having a higher impurity concentration, a second conductivity type well region formed so as to reach the doping layer from the element forming main surface side of the first semiconductor substrate, and formed in the well region. A source region of a first conductivity type; a source electrode connected to the well region and the source region; a drain electrode connected to the first semiconductor substrate; and a source region in the well region. The semiconductor device as to form a channel, characterized in that it comprises a gate electrode formed through an insulating film on the first semiconductor substrate of the element forming on the main surface between the drain electrode. 2. A plurality of insulating separation grooves formed on the first semiconductor substrate and formed of a plurality of insulating layers reaching from the main surface for element formation to the bonding interface, and the first semiconductor substrate with the insulating separation grooves. Formed by separating, surrounded by the insulating separation groove and the bonding interface,
A PN isolation region separated by the PN junction, the doping layer is formed on both sides of the junction interface of the PN isolation region with the junction interface in between, and the well region is 2. The semiconductor device according to claim 1, wherein the PN isolation region is formed so as to reach the doping layer from the element-forming main surface side. 3. The semiconductor device according to claim 1, wherein the impurity concentration in the doping layer is 1 × 10 ¹⁷ cm ⁻³ or more. 4. A surface polishing step of mirror-polishing at least one surface of a first-conductivity-type first semiconductor substrate and mirror-polishing at least one surface of a second-conductivity-type second semiconductor substrate; An impurity addition step of adding a high-concentration impurity of the second conductivity type from the mirror-polished one main surface side of the semiconductor substrate or the second semiconductor substrate; and the one mirror-polished main surface of the first semiconductor substrate. A substrate bonding step of directly bonding the mirror-polished one main surface of the second semiconductor substrate; heating the directly bonded first and second semiconductor substrates in an oxidizing atmosphere; A heat treatment step of diffusing the first semiconductor substrate into the first and second semiconductor substrates to form a doping layer, a grinding and polishing step of grinding and polishing the first semiconductor substrate with a predetermined thickness left from a bonding interface, and Grinded and polished table And the well region forming step of forming a well region by adding an impurity of a second conductivity type from the side to reach the doped layer, a source region of the first conductivity type formed in said well region,
A source electrode is formed from above the well region to the source region, a drain electrode is formed on the first semiconductor substrate, and further, an insulating film is formed on the element-forming main surface of the first semiconductor substrate. And a transistor forming step of forming a gate electrode. 5. The impurity adding step is a step of adding an impurity from the mirror-polished one main surface side of the second semiconductor substrate, and the concentration of the impurity is formed in the doping layer forming step. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the impurity concentration at the junction interface of the doping layer is set to 1 × 10 ¹⁷ cm ⁻³ or more.