JPH0864648A - Semiconductor wafer - Google Patents

Abstract

PURPOSE: To obtain a semiconductor wafer in which the time required for evaluating an LSI can be shortened by limiting the movement of a probe. CONSTITUTION: The constitution of an integrated circuit chip 2 to be formed on a semiconductor wafer is divided into a plurality of groups each formed with an evaluation circuit part 1. The evaluation circuit part is provided with pads 3, 5 for touching a probe, and a decode means 4 connected with the I/O pad of each chip in each group in order to decode a chip selection signal being inputted from the probe touching pad and to connect the probe touching pad with a selected chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer suitable for LSI test evaluation.

[0002]

2. Description of the Related Art In a conventional LSI manufacturing process, as shown in FIG. 5, only a product chip (chip to be evaluated) portion 2 is formed on a semiconductor wafer 12, and the electrical characteristics of each LSI are The evaluation is performed by a method in which a probe is brought into contact with each pad of each of the product chip portions 2 and the electrical characteristics of each chip are measured. Therefore, in this conventional method, it is necessary to create a dedicated probe card in which the probes are arranged according to the pad arrangement of each LSI.

On the other hand, in the evaluation of a memory such as a large capacity DRAM, which requires a long time to evaluate one chip, or a logic IC which is difficult to evaluate, a self-evaluation circuit is built in each chip in order to facilitate the evaluation. There is.

[0004]

In the above-mentioned conventional method, since the evaluation is performed by moving the wafer one chip at a time, the evaluation takes time, and the design rule around the pad may be restricted by the probe. . Moreover, since the probe card has specifications that match the pad arrangement of each product, it is not compatible with other products. On the other hand, in an LSI having a built-in self-evaluation circuit, a self-evaluation circuit, which is unnecessary for use as a product, is built in, and thus there is a disadvantage that the chip area increases.

The present invention has been devised in order to remedy such drawbacks of the prior art, and its main purpose is to
It is an object of the present invention to provide a semiconductor wafer configured so that the movement of the probe can be reduced during the evaluation of SI to shorten the evaluation time.

[0006]

According to the present invention, there is provided a semiconductor wafer having a plurality of chips on which integrated circuits are formed, the plurality of chips being divided into a plurality of groups. The circuit portion for evaluation is divided and formed for each group, and the circuit portion for evaluation is connected to a pad for probe contact and an input / output pad of each chip in each group, and And a decoding means for decoding a chip selection signal input from the probe contact pad to connect the probe contact pad to the selected chip.

[0007]

In the means according to the present invention, the evaluation is carried out by bringing the probe into contact with the pad of the evaluation circuit section instead of bringing the probe into contact with the pad of each chip and performing evaluation one by one. The number of movements of (1) is (conventional number of evaluation circuit parts) / (number of chips to be evaluated), and the evaluation time can be shortened. When this method is used, the probe is not brought into contact with the pad of the product chip, so that the design rule around the pad can be made unaffected by the probe. Furthermore, by standardizing the number of pads and the layout of pads in this evaluation circuit unit, one type of probe card can be shared by a plurality of products, so that the probe card production cost can be reduced. Further, by mounting the self-evaluation circuit in the evaluation circuit section, the chip area of the LSI that requires the self-evaluation circuit can be reduced. In addition, by arranging a large number of product chips for one evaluation circuit section, it becomes possible to increase the number of product chips that can be formed on one wafer as compared with the conventional case.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic view of a chip layout on a wafer for explaining one embodiment of the present invention. This wafer is provided with a plurality of product chip (chips to be evaluated) portions 2 to be cut into products in later steps, and an evaluation circuit portion 1 used for evaluation of the product chip portions 2.

The evaluation circuit section 1 includes a signal / power supply pad 3 necessary for measurement of the product chip section 2 and a product chip section that is electrically connected to the signal / power supply pad 3 and sends a signal / power supply. A decoder circuit 4 for selecting 2 and a chip address signal which is electrically connected to the decoder circuit 4 and issues a chip address (00, 01, 10, 11) signal necessary for selecting the evaluated chip portion 2 The pad 5 and the product chip portion 2 are formed by a known process technique.

Two product chips 2 are formed on the upper and lower sides of the evaluation circuit unit 1. Then, the AL wirings 7 and 8 are formed on the scribe line 6 to electrically connect the signal / power supply pad 9 of the product chip section 2 and the decoder circuit 4 of the evaluation circuit section 1. At this time, the lengths of the AL wirings 7 and 8 are set to be the same for any product chip portion 2.

Chips are arranged on the wafer 12 as shown in FIG. 2 with the combination of one evaluation circuit unit 1 and four product chip units 2 as described above as a minimum unit group. The product chip unit 2 in each group is 0 in FIG.
It is addressed as indicated by 0, 01, 10, 11.

In the present embodiment, a probe (not shown) is brought into contact with the pad of the evaluation circuit section 1 so that signals necessary for evaluation
By sequentially sending the chip address signals (00, 01, 10, 11) for selecting the chips to be evaluated simultaneously with the power supply, four chips can be measured with one contact of the probe. Moreover, since the probe is not brought into contact with the pad 9 in the product chip portion 2, the design rule around the pad is not restricted by the probe.

FIG. 3 is a schematic diagram for explaining an embodiment in which the number and arrangement of pads of the evaluation circuit portion 1 are standardized in the present invention. Each chip is formed in the same manner as in the first embodiment, but here, more pads 3, 5, 10 than necessary are formed on the evaluation circuit section 1. However, the unused pad 10 is not electrically connected to the decoder circuit 4. The probe card is created according to the number and arrangement of these pads 3, 5, 10.
For example, even when different LSIs are created, a common probe card can be used by making the number and arrangement of pads of the evaluation circuit unit 1 common.

FIG. 4 shows the self-evaluation circuit 1 in the evaluation circuit section 1.
FIG. 3 is a schematic diagram for explaining an example in which 1 is mounted. Each chip is formed in the same manner as in the first embodiment, but here, the self-evaluation circuit 11 is formed on the evaluation circuit unit 1. In this embodiment, since the self-evaluation circuit 11 is arranged outside the product chip section 2, the area of the product chip section 2 does not increase.

[0016]

As described above, according to the present invention, since a plurality of product chips (chips to be evaluated) can be evaluated by one probe contact with the pad, the number of wafer movements is reduced, The evaluation time can be shortened.

[Brief description of drawings]

FIG. 1 is a schematic view of a chip arrangement for explaining an embodiment of the present invention.

FIG. 2 is a plan view of a wafer for explaining an embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining an embodiment in which the number and arrangement of pads in the evaluation circuit section are standardized in the present invention.

FIG. 4 is a schematic diagram for explaining an embodiment in which a self-evaluation circuit is mounted on an evaluation circuit unit according to the present invention.

FIG. 5 is a plan view of a wafer for explaining a conventional example.

[Explanation of symbols]

 1 Evaluation Circuit Section 2 Product Chip Section 3 Signal / Power Pad 4 Decoder Circuit 5 Chip Address Signal Pad 6 Scribe Line 7 and 8 AL Wiring 9 Signal / Power Pad 10 Spare Pad 11 Self-Evaluation Circuit 12 Wafer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 H01L 27/04 T

Claims (1)

[Claims] 1. A semiconductor wafer having a plurality of chips on which integrated circuits are formed, wherein the plurality of chips are divided into a plurality of groups, and an evaluation circuit unit is formed for each group. The evaluation circuit unit is connected to a probe contact pad and an input / output pad of each chip in each group, and decodes a chip selection signal input from the probe contact pad to decode the chip selection signal. A semiconductor wafer, comprising: a decoding means for connecting a probe contact pad to a selected chip.