JPH0862297A - Digital-signal processing lsi test circuit - Google Patents

Abstract

PURPOSE: To test LSI using a low-speed tester by supplying a test pattern into an input part at the time of testing, supplying a single-phase clock to the input part and an output part, respectively, and outputting the result of the test. CONSTITUTION: At the time of testing, a data selector 6 selects test data 11 from an LSI tester 3 as the test data and inputs the data into a signal processing circuit 2 through a data flip-flop 4. The output data are inputted into the LSI tester 3 as the result of the test. At the time of the normal test, the operation is performed by a single-phase clock 12 supplied from the LSI tester 3. At the time of the high-speed test, a data selector 7 selects the output of an OR gate 9 based on a test signal 14. A clock C, which is obtained by synthesizing three-phase clocks C1, C2 and C3 at the OR gate, is supplied into the flip-flops 4 and 5 and a pattern generating circuit 8. Furthermore, the data selector 6 selects a test pattern as the test data. The test pattern is inputted to the signal processing circuit 2, and the test can be performed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to testing semiconductor integrated circuits, and more particularly to testing digital signal processing LSIs operating at high speed.

[0002]

2. Description of the Related Art A conventional method for testing a digital signal processing LSI is a device under test (Device Under Test).
A general method is to apply a test pattern from an LSI tester (also called "tester") to the input section of the digital signal processing LSI, and input the output data of the digital signal processing LSI to the LSI tester as a test result to perform the test. Target.

A conventional technique will be described with reference to FIG. As shown in FIG. 4, in the digital signal processing LSI 1, the test data 11 supplied from the LSI tester 3
Is input to the signal processing circuit 2 inside the LSI via the data flip-flop 4, the output data of the signal processing circuit 2 is output as the device output data 13 via the data flip-flop 5, and the LSI tester 3 outputs the test result.
Is input to

At this time, the data flip-flops 4 and 5
Operates with a single-phase clock signal supplied from the LSI tester 3.

Therefore, the test rate of the LSI tester 3 must be higher than or at least equal to the operating frequency of the LSI, which is the device under test.

By the way, with the recent increase in the speed of LSIs,
Although LSIs with operating frequencies of about 50 to 100 MHz have appeared, currently, general testers, especially testers for mass production tests, have test rates of about 20 to 30 MHz.
High-speed testers with a test rate of 50 MHz or more are still few and extremely expensive, and are mainly suitable for research and development (R & D).

[0007]

Conventionally, the above 20 to 30
There are many products that enable high-speed testing by generating and synthesizing n-phase clocks even in LSI testers with low test rates of MHz, but in this case, the device under test, L
Input / output ports that are n times the number of SI pins are required. That is, some LSI testers have, for example, a pin multiplex function that multiplexes 2-pin data and edges to realize a double test rate.
In this case, when the number of pins of the LSI tester is 256, basically only a half of the device with a scale of about 128 pins can be tested.

As a method for testing a high speed VLSI device using a low speed tester, for example, Japanese Patent Laid-Open No. 63-1315.
Japanese Unexamined Patent Publication No. 4 (1994) proposes a test method in which two staging latches connected in series are incorporated and a high-speed test is equivalently performed by utilizing the phase difference of clocks supplied to each latch.

FIG. 5 shows an example of the configuration of the test method disclosed in Japanese Patent Laid-Open No. 63-13154.

Referring to FIG. 5, combination circuit 100 receives input data DI as an input and outputs it as output data X _{1 to} X _N. The output data X _{1 to} X _N are latched by the system clock C _M in the master latch (M latch) 102 and then latched by the system clock C _{S in} the slave latch (S latch) 104 and output as outputs Y ₁ to Y _N. At the same time, it is input as a feedback input Y to the combination circuit 100.

At this time, by setting the phase relationship between the system clocks C _M and C _S as shown in FIG. 6, the test can be performed in the test cycle T _P shorter than the cycle time T _C of the tester.

However, in the test method of the above-mentioned Japanese Patent Laid-Open No. 63-13154, two clock wirings are required because the circuit design is performed using a two-phase clock, and the chip area is increased. In addition to the problem of increasing the number of clocks, a margin must be ensured so that the clocks do not overlap during actual operation, and therefore there is a drawback that the speed margin becomes more severe in the case of a high-speed circuit.

In a high-speed LSI, power consumption becomes a problem, but the ratio of clocked buffers to the power consumption of the entire LSI is large, and it is necessary to set a plurality of clock buffers in terms of power consumption. Is also a disadvantage.

As described above, in the operation test of the conventional high-speed digital signal processing circuit, a high-speed tester capable of operating at an operation speed equal to or higher than the operation speed of the LSI or a tester having a very large number of pins is required. The equipment cannot handle it.

Further, even if the number of high-speed testers is set, the number of the high-speed testers is small and the processing capacity is limited. Further, since a high-speed tester and a tester having a large number of pins are extremely expensive, a large amount of investment is required for new introduction, resulting in an increase in LSI manufacturing cost.

Further, it has been found that there is a problem in the speed margin and the power consumption in the actual operation even in the conventional example in which the same effect as the present invention is obtained by utilizing the phase difference between the two-phase clocks.

Therefore, the present invention solves the above problems,
An object of the present invention is to provide an LSI test circuit that enables a test of an LSI under test using a low-speed tester having a test cycle longer than the operation cycle time of the LSI under test.

[0018]

In order to achieve the above object, the present invention provides a signal processing for inputting / outputting data through flip-flops provided with an input section and an output section and operating with the same clock pulse. In a semiconductor integrated circuit having a circuit, a clock synthesizing unit for synthesizing n-phase (n is a positive integer) clock pulses that do not overlap with each other inputted from the outside and outputs as a single-phase clock,
A test pattern generation circuit driven by a single-phase clock output from the clock synthesis unit,
The test pattern output from the test pattern generating circuit is supplied to the input unit, and the single-phase clocks output from the clock synthesis unit are supplied to the flip-flops of the input unit and the output unit, respectively, and the output Provided is a test circuit for a semiconductor integrated circuit, which outputs output data from a unit as a test result.

Further, in the test circuit of the semiconductor integrated circuit according to the present invention, it is preferable that either the single-phase clock output from the clock synthesizer or the single-phase clock input from the outside is based on the test mode control signal. It is characterized by comprising a first selector for selecting and a second selector for selecting one of the output of the test pattern generating circuit and a test pattern input from the outside based on the test mode control signal. .

Further, in the test circuit of the semiconductor integrated circuit according to the present invention, after the data judging circuit is connected to the output section and the output of the output section is judged by the data judging circuit, only the judgment result is the test result. It is characterized by outputting as.

The semiconductor integrated circuit test circuit according to the present invention is characterized in that the semiconductor integrated circuit includes a circuit for digital signal processing as an internal circuit.

Further, according to the present invention, an LSI tester tests a semiconductor integrated circuit having a signal processing circuit for inputting / outputting data via flip-flops provided with an input section and an output section and operating with the same clock pulse. In the test circuit for performing the above, a clock synthesizing unit that synthesizes n-phase (n is a positive integer) clock pulses that do not temporally overlap with each other and is output as a single-phase clock from the LSI tester; A test pattern generation circuit driven by a single-phase clock output from the synthesis unit,
And an LS that operates at a lower speed than the semiconductor integrated circuit
During the test by the I tester, the test pattern output from the test pattern generating circuit is supplied to the input section of the semiconductor integrated circuit, and the clock synthesis section is provided for the flip-flops of the input section and the output section of the semiconductor integrated circuit. A single-phase clock output from each of the semiconductor integrated circuits is supplied to the tester, and output data from the output section of the semiconductor integrated circuit is input to the LSI tester as a test result.

[0023]

According to the present invention, in a digital signal processing LSI having a signal processing circuit for inputting / outputting data via flip-flops operating with the same clock pulse, a pattern generating circuit for generating a predetermined pattern and an external circuit are provided. A clock synthesizer that synthesizes more input n-phase clocks and supplies the clocks as a single-phase clock is used to perform a test using a tester having a cycle time longer than the operation cycle time of the digital signal processing LSI. Further, it has an advantage that it does not affect speed margin and power consumption during actual operation.

Further, in the present invention, when the data determination circuit is provided, the number of pins used in the LSI tester can be further reduced. Further, according to the present invention, either the clock synthesizing unit and the pattern generating circuit or the direct input of the test pattern from the LSI tester is selected in accordance with the selection signal at the time of the normal test and the high-speed test, and the test target is tested. Can be supplied to the circuit.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, in which elements having the same functions as those of the circuit shown in FIG. 4 are designated by the same reference numerals. FIG. 2 is a timing chart showing the phase relationship of clocks in this embodiment.

Referring to FIG. 1, digital signal processing LS
In I1, in the normal test, the data selector 6 is
The test data (also referred to as “test pattern”) 11 output from the I tester 3 is selected as test data and input to the signal processing circuit 2 via the data flip-flop 4. The output data of the signal processing circuit 2 is output via the data flip-flop 5 and input to the LSI tester 3 as a test result.

During the normal test, the data flip-flops 4 and 5 are operated by the single-phase clock 12 supplied from the LSI tester 3 via the data selector 7.

During the high speed test, the data selector 7
Is a test control signal 14 supplied from the LSI tester 3.
The output of the OR gate 9 is selected by the
The clock C obtained by combining the three-phase clocks C1, C2, C3 supplied from the OR gate 9 is supplied to the data flip-flops 4, 5 and the pattern generation circuit 8.

Further, the data selector 6 selects the test pattern generated by the pattern generating circuit 8 as the test data by the test control signal 14 supplied from the LSI tester 3, and the test pattern is the data flip-flop 4.
Is input to the signal processing circuit 2 via.

The signal processing circuit 2 includes clocks C1, C2,
Output data A ′, B ′, C ′ (see FIG. 2) synchronized with C3 are output as device output data 13 via the data flip-flop 5, and input to the LSI tester 3 as a test result.

Referring to FIG. 2, the LSI tester 3 outputs the output data A ', B', and C'to the tester strobe signal a,
Take in b and c, and compare with expected pattern and test. At that time, the output data A ′, B ′, C ′ are parallelized (that is, on separate pins) and the tester strobe signals a, b, c are output to each pin at corresponding timing positions (phases) during one test cycle. It may be output every time, or output data is input to the same pin and the same test is performed 3 times.
The timing position of the strobe signal may be sequentially changed for each test by repeating the test.

Thus, according to this embodiment, the LS
The test can be performed at a frequency three times the test rate of the I tester.

Since the number of critical paths that require high speed operation is very limited, the pattern generation circuit 8 may be small.
For example, since it can be constituted by a ROM (read only memory) of several tens to several hundreds of bits, an increase in circuit scale is suppressed.

Further, for example, MUSE (Multiple Sub-Nyq)
uist Sampling Encode) type image processing LSI,
The H-Sweep (horizontal sweep) circuit or the ramp waveform generating circuit can be used, and these circuits can be used as a counter.

Further, unlike the test method disclosed in Japanese Patent Laid-Open No. 63-13154, which has been described as the conventional example, the LSI according to the present embodiment operates with a single-phase clock, and therefore has a speed margin. There is a margin, which is also advantageous in terms of power consumption.

Note that, unlike the configuration shown in this embodiment,
There is also a method of generating three-phase clocks on the tester side, but as the number of clocks increases, the model of the tester is limited, and as mentioned above, the problem of processing capacity occurs, so that more versatility is provided. The clock synthesis circuit is preferably incorporated in the LSI.

As described above, in the present embodiment, the present invention has been described based on the example of generating the single-phase clock from the three-phase clocks whose phases do not overlap with each other. By generating a single-phase clock from an (integer) clock, it is possible to test high-speed devices with a low-speed tester.

In this embodiment, the LSI in which the test circuit is mounted on the semiconductor chip has been described as a preferable mode, but the digital signal processing LSI is as shown in FIG.
As a device composed of the data flip-flops 4 and 5 and the signal processing circuit 3, in order to test the digital signal processing LSI, a test jig of an LSI tester (a socket for a device under test and pins of the LSI tester, a power supply, a ground) is used. , Etc. on the test board)
The present invention also includes a configuration in which test circuits such as the clock synthesis circuit 9, the selectors 6 and 7, the pattern generation circuit 8 are provided.

[0040]

[Embodiment 2] FIG. 3 shows a configuration example of a second embodiment of this embodiment. In FIG. 3, elements having the same functions as those in FIG. 1 are designated by the same reference numerals.

Referring to FIG. 3, the present embodiment is different from the first embodiment in that the data decision circuit 5 is built in the digital signal processing LSI 1, and the other structures are the same. Only the differences will be described below.

Referring to FIG. 3, the output result of the signal processing circuit 2 is input to the data determination circuit 10 via the data flip-flop 5, and the data determination circuit 10 outputs a predetermined expected value and an output result provided in advance. Is compared and judged, and only the judgment result is output. As a result, the LS is different from that of the first embodiment.
The number of input pins of the I tester 3 can be significantly reduced. If the pattern generation circuit 8 is composed of a ROM having a relatively small capacity, a counter, or the like,
The expected value of the output of the signal processing circuit 2 corresponding to this test pattern is stored in advance in a ROM (not shown) or the like, and after comparing the output result with the expected value, the result is PASS or FAIL.
L) information is output, and the data determination circuit 10
It is possible to suppress an increase in the circuit scale of the test circuit due to the insertion of.

In the present invention, test circuits such as the clock synthesis circuit 9, the selectors 6 and 7, the pattern generation circuit 8 and the data determination circuit 10 shown in FIG. 3 are provided on the test jig of the LSI tester. It also includes the configuration.

In the above embodiments, the digital signal processing LSI is described as a suitable mode as the LSI to be tested, but it goes without saying that the principle of the present invention can be applied to LSIs for other purposes.

[0045]

As described above, according to the present invention, in the digital signal processing LSI having the signal processing circuit for inputting / outputting data via the flip-flops operating with the same clock pulse, the pattern generating circuit and the external circuit are provided. By having a clock synthesizing unit that synthesizes n-phase clocks that are more input and supplies as a single-phase clock, the LSI tester that operates at a lower speed than the digital signal processing LSI that is the device under test can be used to test the LSI. This has the effect of enabling testing and reducing the test cost.

Further, according to the present invention, there is an advantage that it is possible to perform a test by a low-speed tester without affecting the speed margin and power consumption during actual operation.

According to the present invention, the circuit scale of the pattern generating circuit can be small, and an increase in the circuit scale of the test circuit of the semiconductor integrated circuit can be suppressed.

Further, in the present invention, when the data judgment circuit is provided, the number of pins used in the LSI tester can be further reduced.

Further, according to the present invention, either the clock synthesizing unit and the pattern generating circuit or the direct input of the test pattern from the LSI tester can be switched according to the mode at the time of the normal test and the high-speed test. In addition to being able to test high-speed devices, it is also possible to directly input a test pattern from a high-speed tester and perform characteristic analysis tests for research and development.

Further, according to the test circuit of the present invention,
The LSI tester that operates at a lower speed than the LSI under test, which is the device under test, can be used to test the LSI, and the test cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing a phase relationship of clocks in the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional test method.

FIG. 5 is a block diagram showing a conventional technique.

FIG. 6 is a timing diagram showing a clock phase relationship in the related art.

[Explanation of symbols]

 1 Digital Signal Processing LSI 2 Signal Processing Circuit 3 LSI Tester 4, 5 Data Flip-Flop 6, 7 Data Selector 8 Pattern Generation Circuit 9 OR Gate 10 Data Judgment Circuit 11 Test Data (Test Pattern) 13 Clock 13 Device Output Data 14 Test Control Signal 100 combination circuit 102, 104 data latch C1, C2, C3, C clock A ', B', C ', output data a, b, c tester strobe signal

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 3, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

As a method of testing high-speed VLSI devices using low-speed tester, for example, Japanese Public Akira 63-1315
Japanese Unexamined Patent Publication No. 4 (1994) proposes a test method in which two staging latches connected in series are incorporated and a high-speed test is equivalently performed by utilizing the phase difference of clocks supplied to each latch.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

[0009] FIG. 5 shows a configuration example of the disclosed test method in JP said Akira Japanese public 63-13154.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012] However, said keep test methods Japanese public Sho 63-13154 discloses, to carry out circuit design using two-phase clock to have the basic clock wiring is required two chip area In addition to the problem of increasing the number of clocks, a margin must be ensured so that the clocks do not overlap during actual operation, and therefore there is a drawback that the speed margin becomes more severe in the case of a high-speed circuit.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

Further, LSI according to the present embodiment is different from the the test method disclosed in Japanese public Sho 63-13154 discloses described as a conventional example, since operating a single-phase clock, the speed margin There is a margin, which is also advantageous in terms of power consumption.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04 21/822 H01L 27/04 T

Claims (5)

[Claims] 1. In a semiconductor integrated circuit having a signal processing circuit for inputting / outputting data via flip-flops provided with an input section and an output section and operating with the same clock pulse, the time input from the outside with respect to each other. Clock synthesizing unit that synthesizes n-phase (n is a positive integer) clock pulses that do not overlap each other and outputs as a single-phase clock, and a test pattern generating circuit driven by the single-phase clock output by the clock synthesizing unit And a test pattern output from the test pattern generating circuit is supplied to the input unit during a test, and a single phase output from the clock synthesis unit is supplied to the flip-flops of the input unit and the output unit. A semiconductor integrated circuit characterized in that a clock is supplied to each and the output data from the output section is output as a test result. Test circuit. 2. A first selector for selecting one of a single-phase clock output from the clock synthesizer and a single-phase clock input from the outside based on a test mode control signal,
2. The semiconductor integrated circuit according to claim 1, further comprising: a second selector that selects one of an output of the test pattern generation circuit and a test pattern input from the outside based on the test mode control signal. Test circuit. 3. A data judgment circuit is connected to the output section, and after the output of the output section is judged by the data judgment circuit,
3. The test circuit for a semiconductor integrated circuit according to claim 1, wherein only the judgment result is output as the test result. 4. The test circuit for a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit includes a circuit for digital signal processing as an internal circuit. 5. A test for testing, by an LSI tester, a semiconductor integrated circuit having a signal processing circuit for inputting and outputting data via flip-flops provided with an input section and an output section and operating with the same clock pulse. In the circuit, a clock synthesizing unit that synthesizes n-phase (n is a positive integer) clock pulses that do not temporally overlap with each other and is output as a single-phase clock from the LSI tester, and the clock synthesizing unit outputs the clock pulses. And a test pattern generating circuit driven by a single-phase clock, which is output from the test pattern generating circuit to an input section of the semiconductor integrated circuit during a test by an LSI tester operating at a lower speed than the semiconductor integrated circuit. The test pattern is supplied to the flip-flops of the input section and the output section of the semiconductor integrated circuit. The single-phase clock output from the clock synthesis unit and each supply, the input to the LSI tester output data from the output portion of the semiconductor integrated circuit as a test result, the test circuit, characterized in that the.