JPH0856143A - Variable delay circuit for periodic clock - Google Patents

Abstract

PURPOSE:To obtain a variable delay circuit without occurrence of jitter attended with circuit integration and to realize the variable delay circuit ease of large scale circuit integration by constituting the variable delay circuit only a digital circuit. CONSTITUTION:An input periodic clock signal 70 is fed to an input terminal of a gate 12a of a 1st stage and plural gates 12a to 12n providing a propagation delay in excess of a multiple of several number of a prescribed period Tconst are provided in series connection. Then each output terminal of the plural gates 12a to 12n is connected to the input terminal of the selector 16, which selects any output signal of the plural gates 12a to 12n and outputs it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit which makes variable the output timing of a periodic clock.

[0002]

2. Description of the Related Art As a conventional example, there is a delay circuit that generates a ramp wave and uses a comparator to change the output timing. This will be described with reference to FIGS. 3 and 4. In the configuration of this apparatus, as shown in FIG. 3, the periodic clock signal 70, which is the input signal of the ramp wave generator 52, is a clock signal generated at a constant period Tconst. The ramp wave generator 52 is a generator that generates a triangular waveform for each trigger signal, and generates a rising voltage having a slope proportional to time. That is, the rising edge of the input periodic clock signal 70 is detected as a trigger signal, and as shown in FIG. 4, the ramp wave 80 is initialized and then a rising voltage signal of triangular waveform is started. The output signal 53 of the ramp wave 80 is supplied to one input terminal of the comparator 58. The DA converter 56 is a DA converter that receives the setting of digital data and outputs an analog comparison voltage 57. Upon receiving the delay amount setting data 55 from the outside, an analog comparison voltage 57 corresponding to this data is supplied to the other input terminal of the comparator 58 as a reference comparison voltage. Comparator 5
Reference numeral 8 is a comparison of both analog voltages, and when the rising voltage of the ramp wave 80 detects the comparison voltage 57 or more, the output signal 59 becomes high level. With this configuration, by changing the value set in the DA converter 56, it is possible to add an arbitrary delay time to the input periodic clock signal 70 and output it. Here, the resolution of the delay time is the resolution of the DA converter 56,
Since it is determined by the slope of the ramp wave 80, a desired delay resolution can be easily obtained by using the DA converter 56 having a desired resolution.

[0003]

As described above, since the ramp wave generating section 52, the DA converter 56, and the comparator 58 are composed of analog circuits, when they are integrated, signals of adjacent signals are not generated. There may be a problem that jitter is generated in the output signal 59 due to the influence of noise. Further, the cost of using an analog mixed circuit as an LSI is often high.

Therefore, the problem to be solved by the present invention is to construct a variable delay circuit by only a digital circuit to form a stable circuit without the occurrence of jitter due to integration, and
It is an object to realize a variable delay circuit which can be easily converted to I.

[0005]

FIG. 1 shows a solution according to the present invention. In order to solve the above-mentioned problem, in the configuration of the present invention, the periodic clock signal 70 that is an input is supplied to the input end of the gate 12a of the first stage, and the constant period Tconst
A plurality of gates 12a to 1 that give a propagation delay exceeding several times
2n are provided in series connection, and a selector 16 is provided that connects each output terminal of the plurality of gates 12a to 12n to an input terminal of the selector 16 and selects and outputs any output signal of the plurality of gates 12a to 12n. Make it a constituent means. Thereby, due to the resolution less than the propagation delay time Td of the gate,
It is used as a means for realizing a variable delay circuit. In addition, there is also a configuration means for implementing the above-described configuration of the plurality of gates and the selector in series in a plurality of stages.

[0006]

The overall propagation delay T due to the gates 12a to 12n
By providing total several times or more of the period Tconst and selecting it as the output signal 18 by the selector 16, there is an effect of obtaining resolution less than the propagation delay time Td of the gate.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is a circuit in which the propagation delay due to the gates of a plurality of ICs is used as a delay element, and this and a selector are used to make the output timing variable. This will be described with reference to FIG. The configuration of this device is
As shown in FIG. 1, the periodic clock signal 70, which is the input signal of the plurality of gates 12a to 12n, has a constant period Tconst.
Signal. The plurality of gates 12a to 12n are N gates, and each gate has substantially the same propagation delay T.
It is used as a delay element having d. These gates are connected in series, and are supplied from the output point of each gate 12n to the input terminal of the selector 16. Multiple gates 1
The total propagation delay Ttotal due to 2a to 12n is the period Tc.
Provide several times more than onst.

The selector 16 is an N-input 1-output selector circuit. One of the delayed signals from the N gates is selected by the selection signal 17 and becomes the output signal 18. As a result, the delay time of the output signal 18 can be output as a signal delayed by the resolution of the propagation delay Td of the gate. As a result, the obtained resolution is determined by the propagation delay of the gate. However, in the present invention in which the total propagation delay Ttotal is set to be several times or more of the period Tconst,
Focusing on the periodic clock signal 70 that is repeatedly generated, a resolution of less than one gate time can be obtained. This will be described below by showing numerical examples.

The gate propagation delay is, for example, Td = 90p
s, the number of used gates N = 900, and the period Tco
It is assumed that nst = 10 ns, and the gate selection stage value of the selector 16 = Sel. Here, the propagation delay of the selector 16 is assumed to be 0 ns for ease of explanation.
The delay time at the output point 18 can be expressed by Tx = Td × Sel.
Here, since Td = 90 ps, the resolution is 90 ps.
It is a step. Next, the delay time from the position exceeding Tx> 10 ns is Tx = Td × at the position Sel = 112.
Sel = 90 × 112 = 108080 ps. Here, when the period Tconst = 10 ns is subtracted, 80 ps is the difference from the immediately preceding input period clock signal 70, which can be regarded as the obtained delay time. That is, when one cycle Tconst time (10 ns) is delayed, the time added with the offset time of 80 ps becomes the delay time. Similarly, 2 periods Tconst
When the time (20 ns) is delayed, the offset time becomes 70 ps. Similarly, an offset time of 60 ps results when the delay is 3 cycles Tconst time (30 ns). In this way M
If the period Tconst time (M × 10 ns) is delayed, 90− (M
× 10) The offset time is ps. As shown in the above numerical example, the cyclic clock signal 70 is repeatedly generated.
It is understood that the output timing can be finely changed by setting the desired selection signal 17 even for a minute delay time less than the propagation delay of the gate by utilizing the above. Moreover, this realizing circuit can be realized only by a digital circuit and is suitable for an LSI. In the above, in reality, since the propagation delays of the individual gates have variations, the selection signal 17 for determining the delay setting value is set to a normal value by setting the value calibrated in advance. A minute delay time can be obtained.

(Application Example) In the above description of the embodiment, the case where one selector 16 is used has been described. However, as shown in FIG. 2, a configuration in which a plurality of gates and selectors are provided in a plurality of stages is provided. It is good and can be implemented in the same manner. Also,
In the description of the above embodiment, the power supply voltage supplied to the gates 12a to 12n was not mentioned, but by changing the supplied power supply voltage as a power supply independent of other circuits, the change of the propagation delay of the gate is changed. Is obtained. Utilizing this change, a means for reducing the number N of the gates 12a to 12n stages may be used in combination, and the same operation can be performed.

[0011]

Since the present invention is configured as described above, it has the following effects. The total propagation delay Ttotal due to the gates 12a to 12n is
By providing several times or more of the cycle Tconst and selecting this as the output signal 18 by the selector 16, it is possible to obtain the resolution less than the propagation delay time Td of the gate. As a result, it is possible to realize a delay circuit that can finely change the output timing. Further, since this circuit is realized only by a digital circuit, there is an advantage that it can be easily made into an LSI. Of course, since there is no analog circuit, it is possible to realize a stable variable delay circuit that does not generate jitter due to integration.

[0012]

[Brief description of drawings]

FIG. 1 is a delay circuit according to the present invention, which uses a propagation delay due to a plurality of gates as a delay element and uses this and a selector to vary output timing.

FIG. 2 is a delay circuit of the present invention in which a plurality of gates and a selector are provided in a plurality of stages to make output timing variable.

FIG. 3 is an example of a conventional delay circuit that changes output timing by using a ramp wave generation and a comparator.

FIG. 4 is a timing diagram for explaining a conventional output timing delay due to the inclination of the triangular waveform of the ramp wave generator.

[Explanation of symbols]

 12a, 12n Gate 16 Selector 17 Selection signal 18, 59 Output signal 52 Ramp wave generator 55 Delay amount setting data 56 DA converter 57 Analog comparison voltage 58 Comparator 70 Period clock signal 80 Ramp wave

Claims (1)

[Claims] 1. A delay circuit for receiving and outputting a periodic clock signal (70) generated at a constant period (Tconst), and providing a propagation delay that exceeds several times the constant period (Tconst). A plurality of gates (12a to 12n) are connected in series, each output terminal of the plurality of gates (12a to 12n) is connected to an input terminal of the selector (16), and one of the plurality of gates (12a to 12n) is connected. A variable delay circuit for a periodic clock, characterized by comprising a selector (16) for selecting and outputting the output signal.