JPH0851553A - Synchronization processing unit for television receiver - Google Patents

Abstract

PURPOSE:To obtain a reproduced image with high image quality with signal processing using a burst lock clock even in the case of reception of a standard signal and a non-standard signal. CONSTITUTION:A digital PLL 26 generates a burst lock clock. A horizontal synchronization phase detection circuit 31 detects phase fluctuation of a horizontal synchronizing signal based on the burst lock clock. A filter coefficient control circuit 32 changes a filter coefficient used for the processing of a signal processing circuit 18 in response to a phase fluctuation amt. of the horizontal synchronizing signal. The signal processing circuit 18 conducts the processing in response to the filter coefficient synchronously with the burst lock clock to process the video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous processing circuit for generating a synchronous clock synchronized with a television signal in a television receiver, and more particularly to a time axis fluctuation of a horizontal synchronous signal of the television signal in the synchronous processing circuit. The present invention relates to a technique for detecting with high accuracy.

[0002]

2. Description of the Related Art Conventionally, in a digital television receiver (hereinafter abbreviated as "digital television") that digitizes and processes a television signal, a synchronizing clock synchronized with the television signal is generated for television signal processing. A clock generation circuit that operates is generally disclosed in Japanese Patent Laid-Open No. 2-2.
It was constituted by an analog type PLL as described in Japanese Patent No. 53780.

FIG. 10 shows the configuration of such a PLL.

In the figure, 1 is a reference synchronizing signal input terminal, 2 is a phase comparator, 3 is a low-pass filter, 4 is a voltage controlled oscillator (VCO), 5 is a crystal oscillator, 6 is a frequency divider, and 7 is a clock output. It is a terminal.

The phase comparator 3 compares the phase of the input reference signal r with the comparison signal c from the frequency divider 6. The output of the phase comparator is applied to the voltage controlled oscillator 4 via the low pass filter 3. The crystal oscillator 5 supplies an oscillation signal to the oscillator 4. The voltage controlled oscillator 4 is controlled by the output of the low pass filter 3 and outputs a clock ck synchronized with the input reference signal r to the terminal 7 by using the oscillation signal from the oscillator 4.

In the digital television, as a synchronization clock for signal processing for high image quality reproduction, a burst lock clock locked to a color burst included in a television signal and a horizontal synchronization signal included in a television signal are locked. It is considered to use two types of system clocks, a line lock clock having the same frequency as the burst lock clock. That is, when processing a standard signal such as a broadcast wave according to the standard television broadcasting system, a burst lock clock is used, and a reproduction signal such as a VTR which does not strictly comply with the standard television broadcasting system is used. It has been considered to use a line lock clock when processing various nonstandard signals.

Further, the analog type PLL shown in FIG.
A configuration shown in FIG. 11 is conceivable as a configuration of a video signal processing device for performing such a video signal processing by using.

In the figure, 8 is a video signal input terminal and 9 is a clock generation circuit, which is constituted by the analog type PLL shown in FIG. Further, 10 is a synchronizing signal generating circuit, 11
Is a signal processing circuit, 12 is a synchronous reproduction signal output terminal, and 13 is a video signal output terminal.

In the clock generation circuit 9, when a standard signal is input from the video signal input terminal 8, a burst lock clock synchronized with the burst signal is input, and when a non-standard signal is input from the video signal input terminal 8, a horizontal lock clock is input. A line lock clock synchronized with the sync signal is generated.

Next, the sync signal generating circuit 10 generates a sync signal based on the burst lock clock or line lock clock from the circuit 9.

The signal processing circuit 11 inputs the burst lock clock or line lock clock output from the clock generation circuit 9 and performs video signal processing for high image quality.

[0012]

The video processing device shown in FIG. 11 has the following problems.

First, various circuits for switching the burst lock clock and the line lock clock, and a phase for matching the phase of the data obtained by digitizing the video portion of the television signal with the clock to be used according to the switching of the clock. A conversion circuit or the like is required.

When the burst lock clock is also used when a non-standard signal is input, the fluctuation of the horizontal synchronization phase is not reflected in the clock, so that the image quality is sufficiently improved depending on the signal processing using this clock. The effect of can not be expected.

On the other hand, since the line lock clock needs to keep the Q value of the oscillator used low so as to be able to synchronize with a non-standard signal, its accuracy and stability are low. Therefore, a sufficient image quality improvement effect cannot be expected by the signal processing using this clock.

Therefore, the present invention generates a highly stable burst lock clock when inputting both standard and non-standard signals, and accurately contributes to the phase fluctuation of horizontal synchronization in order to contribute to signal processing. An object of the present invention is to provide a synchronous processing circuit capable of detecting.

[0017]

[Means for Solving the Problems] To achieve the above object,
The present invention comprises an A / D converter for converting an input television signal into a digital signal, and means for separating and extracting a burst signal component contained in the digitally converted television signal,
Means for separating and extracting the horizontal synchronizing signal component contained in the digitally converted television signal, digital PLL circuit for digitally generating a burst lock clock locked to the burst signal indicated by the extracted burst signal component, and extracting There is provided a synchronization processing circuit for a television device, which comprises horizontal synchronization variation detecting means for determining a variation in the phase of the horizontal synchronization signal indicated by the horizontal synchronization signal component, with reference to the burst lock clock.

Further, the synchronization processing circuit, the line interpolation filter for performing the line interpolation processing on the digitally converted television signal using a predetermined filter coefficient, and the horizontal synchronization variation detecting means of the synchronization processing circuit are detected. Filter coefficient control means for changing the filter coefficient used by the line interpolation filter according to the amount of change in the phase of the horizontal synchronizing signal so that the influence of the change in the phase of the horizontal synchronizing signal is corrected by the line interpolation processing. Provided is a television signal processing circuit having.

[0019]

According to the synchronization processing circuit of the television device of the present invention, the digital PLL generates the burst lock clock based on the television signal digitally converted by the A / D converter. Further, the horizontal sync fluctuation detecting means obtains the fluctuation of the phase of the horizontal sync signal with reference to the burst lock clock.

The fluctuation of the phase of the horizontal synchronizing signal thus obtained is determined by, for example, using the filter coefficient used by the line interpolation filter in the above-mentioned television signal processing circuit of the present invention as the phase of the horizontal synchronizing signal. It can be used to change the effects of variations so that they are corrected by the line interpolation process.

[0021]

Embodiments of the present invention will be described below.

First, FIG. 1 shows the configuration of a video signal processing apparatus according to this embodiment.

In the figure, 14 is a video signal input terminal, and 15 is A.
/ D converter, 16 Y / C separation circuit, 17 color demodulation circuit, 18 signal processing circuit, 19 output processing circuit, 20 D / A converter, 21, 22 and 23 video signal output terminals,
24 is a burst signal extraction circuit, 25 is a sync signal separation circuit, 26 is a digital clock generation circuit, 31 is a horizontal sync phase fluctuation detection circuit, 32 is a filter coefficient control circuit, 3
Reference numeral 3 is a sync signal reproducing circuit, and 34 and 35 are sync signal output terminals.

Further, the digital clock generation circuit 26
Is composed of a phase comparator 27, a low-pass filter 28, a digital VCO (voltage controlled oscillator) 29, and a frequency divider 30.

Next, the operation of the digital video signal processing apparatus according to this embodiment will be described.

The video signal input from the video signal input terminal 14 is converted into a digital signal by the A / D converter 15, and the burst signal extraction circuit 24 and the sync signal separation circuit 2 are converted.
5 and Y / C separation circuit 16 respectively.

The Y / C separation circuit 16 performs three-dimensional filter processing using, for example, a frame comb filter, and separates the luminance (Y) signal and the color (C) signal for output. The color demodulation circuit 17 demodulates the C signal and separates and outputs the I signal and the Q signal. In the next signal processing circuit 18, a process for converting the number of scanning lines, such as a scanning line interpolation process performed when the image receiving device is a progressive scanning system or a wide variation process for converting a wide aspect, is performed by line interpolation. The line interpolation is realized by a line interpolation digital filter as described later. The filter coefficient of the line interpolation digital filter is controlled by the control signal ct output from the filter coefficient control circuit 32. Details of the signal processing circuit 18 will be described later.

The output processing circuit 19 performs level adjustment of the luminance signal and the color signal processed by the signal processing circuit 18, matrix conversion processing of the color signal, composite video signal creation processing and the like. The D / A converter 20 converts the output of the output processing circuit 19 into an analog signal, for example,
The signals are output from terminals 21, 22, and 23 as R, G, and B signals.

The A / D converter 15 and the D / A converter 2
A clock CK1 output from the digital clock generation circuit 26 is supplied as a sampling clock of 0 and a system clock of the Y / C separation circuit 16, the color demodulation circuit 17, the signal processing circuit 18, and the output processing circuit 19. The frequency of this clock is the subcarrier frequency f of the normal video signal.
4 or 8 times the frequency of sc (4fsc / 8fsc)
Is.

On the other hand, in the burst signal extraction circuit 24, 3.
Using a 58 MHz band pass filter or the like, the burst signal B digitally extracted from the video signal is extracted,
It is input to the clock generation circuit 26. The burst signal extraction circuit 24 can be realized by a digital FIR filter.

The sync signal separation circuit 25 digitally separates and extracts the horizontal sync signal component H and the vertical sync signal component V contained in the video signal, and the horizontal sync phase fluctuation detection circuit 3
1 and the synchronizing signal reproducing circuit 33. The sync signal separation circuit 25 can be realized by using a digital comparator that detects the signal levels of the horizontal sync signal and the vertical sync signal.

The digital clock generating circuit 26 generates a burst lock clock CK1 synchronized with the burst signal based on the input burst signal B. Detailed operation will be described later.

On the other hand, in the horizontal sync phase fluctuation detection circuit 31, based on the horizontal sync signal component H from the sync separation circuit 25 and the clock CK1 from the clock generation circuit 26, a data signal hi representing the fluctuation of the horizontal sync signal on the time axis. Is output. The signal hi is supplied to the filter coefficient control circuit 32 and generates a signal ct for adaptively controlling the coefficient of the line interpolation filter used in the signal processing circuit 18.

The sync signal reproducing circuit 33 includes a horizontal sync signal component H and a vertical sync signal component V from the sync separation circuit 25.
And horizontal drive pulse HD based on clock CK1
And vertical drive pulse VD are generated and output to terminals 34 and 45, respectively.

The clock CK1 output from the digital clock generation circuit 26 is also supplied as a system clock for the separation circuit 25, the burst extraction circuit 24, and the filter count control circuit 32.

Next, details of the operation of generating the burst lock clock CK1 in the digital clock generating circuit 26 will be described.

In the phase comparator 27, the burst signal B
And the phase of the signal from the frequency divider 30 described later are compared, and the phase error signal eb is output according to the phase difference. The phase comparator 27 can be realized by an exclusive OR circuit that takes an exclusive OR of the burst signal B and a signal from the frequency divider 30 described later.

The phase difference signal eb is filtered by the digital low-pass filter 28 and then input to the digital VCO 29 as the phase error signal ei. The low pass filter 28 can be realized by an IIR filter.

The digital VCO 29 outputs the system clock CK1 whose frequency / phase is controlled according to the magnitude of the signal ei. The frequency of the system clock CK1 is usually 8 times or 4 times the subcarrier frequency as described above. Details of the digital VCO 29 will be described later.

Next, the clock CK1 is input to the frequency divider 30, and the frequency divider 30 frequency-divides the clock CK1 into the same frequency (fsc) as the burst signal. This frequency-divided signal is input to the phase comparator 27 as one comparison signal.

The clock generating circuit 26 including the phase comparator 27, the low-pass filter 28, the digital VCO 29, and the frequency divider 30 constitutes a digital PLL.

Next, details of the digital VCO 29 in the digital clock generation circuit 26 will be described.

FIG. 2 shows the configuration of the digital VCO 29.

In FIG. 2, 36 is an input terminal of the phase error signal ei from the adder 29, 37 is a reference phase / frequency setting data E input terminal, 38 is an adder (or subtractor), 39 is a register, 40 Is a crystal oscillator, 41 is an adder, 42 is a latch circuit, 43 is a phase-amplitude data converter, 44 is a rectangular wave forming circuit, and 45 is a system clock C.
This is the output terminal of K1.

Next, the operation will be described. The adder 38 subtracts the reference frequency / phase signal E from the terminal 37 from the input phase error signal ei from the terminal 36 and inputs the output signal eo to the register 39. The reference frequency / phase signal E is
The digital data is provided so that the clock ck of the desired frequency can be obtained in the free run state, that is, in the state where the input phase error signal ei is not input.

The register 39 takes in the input phase data signal eo in synchronization with the master clock MK output from the crystal oscillator 40 and outputs it as a phase increment value signal pi. The signal pi is added by the adder 41 to the latch circuit 4
The output signal from 2 is added, and the added phase cumulative data pa is input to the latch circuit 42 again. This latch operation is performed in synchronization with the master clock MK.

Therefore, the adder 41 and the latch circuit 42 operate as a phase data accumulator, and successively add the phase increment value pi from the register 39 to the previously output value.

Phase accumulated data pa from the latch circuit 42
Is also input to the phase-amplitude data converter 43. In the data converter 43, based on the input phase accumulated data pa,
By sequentially outputting the amplitude corresponding to each phase,
A sine wave amplitude value signal pm having a predetermined frequency (8 times or 4 times the subcarrier frequency) is generated and output. The data converter 43 is composed of, for example, a ROM (Read Only Memory) in which the phase accumulated data pa is used as an input address and the amplitude value corresponding to the phase accumulated data pa is stored as data.

The amplitude output signal pm of the data converter 43 is shaped into a rectangular wave by the rectangular wave forming circuit 44, and is output to the terminal 45 as the above-mentioned system clock CK1.

FIG. 3 shows the digital VCO 2 shown in FIG.
It is a figure for demonstrating operation | movement of the clock generation process of FIG.

When the phase increment value output from the register 39 in FIG. 2 is Δφ, Δφm is the maximum possible phase increment value (360 degrees), and fm is the frequency of the master clock MK, the configuration shown in FIG. 2 is used. The frequency f0 is fo = Δφ / Δφm × fm.

The clock frequency to be generated here is eight times the subcarrier frequency fo = 3.58 MHz × 8 = 2
8.64MHz, master clock used fm = 1
Assuming 20 MHz, the relationship between both clocks at this time is shown in FIG.
As shown in, the master clock divides one cycle of the generated clock into 1 / 4.19.

Therefore, the unit phase angle corresponding to the above-mentioned phase increment value Δφ is 360 ° / 4.19 = 8.
It becomes 5.9 °. Therefore, if 85.9 ° is given as the reference frequency / phase signal E, when the input phase error signal ei has the value 0, the phase angle of 85.9 ° corresponding to the phase increment value output from the register 40 is set to the master clock. Add in cycles. That is, as shown in the figure, assuming that the initial state is 0 = 0 °, every time the master clock is input, = 85.9 ° → = 171.8 ° → = 25
It changes like 7.7 ° → = 343.6 ° → 0 = 69.5 °.

Therefore, although the phase shifts every cycle, a clock having a desired frequency fo can be obtained by outputting the amplitude value corresponding to the transition of each phase as shown in FIG.
When the input phase error signal ei is not 0, the added value changes according to the value, and as a result, a clock synchronized with the burst signal B is obtained.

Next, FIG. 4 shows the configuration of the horizontal sync phase fluctuation detection circuit 31 (see FIG. 1).

In the figure, 85 is an input terminal for the horizontal synchronizing signal H,
Reference numeral 86 is a phase comparator, 87 is a frequency divider, 88 is an input terminal of the clock CK1 from the clock generation circuit 26, 89 is a digital low-pass filter, and 90 is an output terminal of the horizontal phase fluctuation signal hi.

Next, the horizontal sync phase fluctuation detection circuit 31
The operation of will be described.

The frequency divider 87 divides the highly stable burst lock clock CK1 into a signal having the same frequency as the horizontal synchronizing signal. The phase comparator 86 compares the phases of the horizontal synchronizing signal H and the frequency-divided signal from the frequency divider 87, and outputs a phase difference signal indicating the phase difference. Then, after the phase difference signal is filtered by the low-pass filter 89, it is output to the terminal 90 as the horizontal phase fluctuation signal hi. From the horizontal phase fluctuation signal hi, the filter coefficient control circuit 32 can know the horizontal synchronization time axis fluctuation amount based on the stable burst lock clock ck. The low-pass filter 8
9 can be composed of an FIR filter.

Next, details of the signal processing circuit 18 and the filter coefficient control circuit 32 (see FIG. 1) will be described.

FIG. 5 shows the configuration of the signal processing circuit 18 when the signal processing circuit 18 is a progressive scan conversion circuit.

In the figure, 46, 47 and 48 are input terminals for the Y signal, I signal and Q signal respectively, 49 is an input terminal for the filter coefficient control signal ct from the control circuit 32, and a broken line portion 50.
Reference numerals 51 and 52 denote progressive scan conversion circuits having the same configuration. Reference numerals 62, 63, and 64 denote output terminals for the Y signal, I signal, and Q signal after the sequential scan conversion. Also, 5
3 is a line memory, 54 is a field memory, 55, 5
7, 60, 91, 93, 94 are coefficient multipliers, 5
6, 92 and 95 are adders, 58, 96 and 97 are 1/2 level converters, 59 is a mixing circuit, 61 is a double speed converter, and 91.
Is an input terminal of the system clock CK1.

The operation of the progressive scan conversion circuit 50 will be described below.

The progressive scan conversion circuit 50 is a motion adaptive interpolation filter, and switches between field interpolation and line interpolation depending on the amount of motion. Inter-line interpolation is a process of obtaining one line inserted between two continuous lines by interpolation. Such processing has already been performed by the ED.
Since it is adopted in TVs and is widely known, a description will be given here mainly of a part different from the conventional one. The difference between the progressive scan conversion circuit 50 according to the present embodiment and the conventional one is that the multipliers 55 (coefficients k1) and 57 (coefficients k2) that change the filter coefficient of the interline interpolation filter that performs interline interpolation,
60 (coefficient k0) and 94 (coefficient k3) are newly provided, and the coefficient value is adaptively changed every moment according to the horizontal synchronization phase variation, and correction is performed according to the horizontal synchronization phase variation of the interline interpolation calculation. In point.

Now, the Y signal input from the Y signal input terminal 46 is delayed by one line in the line memory 53, multiplied by the coefficient k2 in the multiplier 57, and before being delayed in the line memory 53 (1 The Y signal (before the line) is multiplied by the coefficient k1 by the multiplier 55 and added by the adder 56. Then, the added signal is 1/2 by the 1/2 level converter 58.
After being increased to 2, it is output to the mixer 59. This signal is the signal of the line generated by the line interpolation.

Similarly, the Y signal input from the Y signal input terminal 46 is delayed by one line in the line memory 53, multiplied by the coefficient k3 in the multiplier 94, and then delayed in the line memory 53. The signal obtained by multiplying the Y signal (1 line before) by the coefficient k0 in the multiplier 60 is added by the adder 95. Then, the added signal is converted into a 1/2 level converter 9
After being halved by 7, it is output to the double speed converter 61.

When interpolating between lines, the mixer 59
The signal given from the level 2 converter 58 is given to the double speed converter 61 as it is.

The double speed converter 97 is a 1/2 level converter 9
The signal given from 7 and the signal given from the 1 / level 2 converter 58 are doubled in the data rate and then alternately output for every one line. Here, the data rate of the Y signal is generally 4 fsc. Therefore, double speed converter 97
Is given a clock of 8 fsc for doubling the data rate.

Now, a state of such inter-line interpolation is shown in FIG.

FIG. 6 conceptually shows the phase shift due to the horizontal synchronization phase variation of the pixel.

The broken lines in the figure represent the lines on the display screen when the horizontal synchronization phase fluctuation is not corrected and the columns perpendicular to the lines, and the points Δ ○ on the display screen are when the horizontal synchronization phase fluctuation is not corrected. Pixels displayed at the intersections of the lines and the columns perpendicular to the lines represent the positions that should be originally displayed. In the figure, ○ indicates the pixels on the line included in the input video signal.
Represents the pixels on the line generated by the line interpolation.
As shown in the figure, when the horizontal synchronization phase variation is not corrected, the pixels are displaced in the horizontal direction due to the influence of the horizontal synchronization phase variation, and the pixels that are not aligned in the vertical direction on adjacent lines are aligned in the vertical direction. Since they are displayed side by side, the relationship between the originally displayed position of each pixel and the displayed position is deviated by an amount corresponding to the horizontal synchronization phase fluctuation amount, and the image is deformed. That is, conceptually, the vertical axis is inclined.

Therefore, in the progressive scan conversion circuit 50, the line indicated by the solid line in the figure and a column perpendicular to the line are assumed, and the pixel ◯ on the line included in the input video signal is converted into the solid line in the figure by the line interpolation. Convert to the pixel ● on the intersection of the line and the column perpendicular to the line. Also, by line interpolation,
Instead of the pixel Δ, the pixel ∘ on the intersection of the line indicated by the solid line in the figure and the column perpendicular to the line is obtained from the pixel ∘ on the line included in the input video signal. As a result, the relationship between the position of each pixel that should be originally displayed and the relationship between the displayed positions is eliminated, and the image is not transformed.

As will be understood from the relationship in the figure, such pixels  and ▲ can be found by performing line interpolation from the pixel ◯ in consideration of the amount of horizontal synchronization phase fluctuation. Specifically, the pixel ● is the multiplier 60, 94.
Of the pixel ∘ by the filter coefficient control signal ct and the filter control circuit 32 changes the multiplication coefficients k0 and k3 of the pixel ▲ according to the horizontal phase fluctuation signal hi. You can

When the amount of motion is small, the data delayed by one field by the field memory 54 of FIG. 5 is interpolated and mixed by the multipliers 91 and 93, the adder 92, and the 1/2 level converter 96. It is delayed by the circuit 59, mixed with the line interpolation result output from the 1/2 level converter 59, and sent to the above-described double speed converter 61.

Next, FIG. 7 shows the configuration of the signal processing circuit 18 when the signal processing circuit 18 is a wide conversion processing circuit.

In the figure, reference numeral 65 is a wide conversion processing circuit for Y signals, 66 is a vertical expansion circuit, 67 is a horizontal expansion circuit, and 68 and 69 are wide conversion processing circuits for I and Q signals, respectively. Further, 70 is a memory circuit, 71 is a 1-line delay circuit, 72 and 73 are coefficient multipliers, 74 is an adder, 75 is a 1-sample delay circuit, 76 and 77 are coefficient multipliers, 78 is an adder, 79, Reference numerals 80 and 81 denote output terminals for Y, I, and Q signals after the wide conversion processing, respectively.

The wide conversion processing circuit performs vertical expansion, horizontal expansion, reduction, etc. of the screen by digital video signal processing.

The operation will be described below.

The Y signal input to the memory 70 is delayed by a predetermined number of lines for the purpose of interpolation calculation processing for each plurality of lines in the vertical conversion circuit 66, which will be described later. The output data multiplier 72 of the memory 70 multiplies by the coefficient k3, the line memory 71 delays by one line, and the multiplier 73 multiplies the data by the coefficient k3.

For this addition, for example, in the case of vertical expansion of 4/3 times shown in FIG. 8A, the line number ln-
4m for sample points of 3m line of 1, ln ...
This is done so that the data at the point Δ of the line is generated.

If a horizontal sync fluctuation occurs at this time, the coefficients of the coefficient multipliers 72 and 73 are set to the coefficient control signal for the same reason as the progressive scan conversion described above with reference to FIGS. As shown in FIG. 8B by ct, the relationship between the positions to be originally displayed of the pixels of each line generated by the line interpolation and the relationship between the displayed positions is eliminated. To do.

As described above, according to the wide conversion processing circuit of the present invention, the horizontal synchronization phase fluctuation can be corrected simultaneously with the vertical expansion conversion.

The data vertically converted in this way is then sent to the horizontal conversion circuit 67.

In the horizontal conversion circuit, the 1-sample delay circuit 7
5. Horizontal interpolation processing is performed by the filter calculation by the coefficient multipliers 76 and 77 and the adder 78, and horizontal expansion /
Perform reduction processing.

By changing the coefficient control of the multipliers 76 and 77 according to the horizontal sync phase fluctuation by the control signal ct, the horizontal sync phase fluctuation can be directly corrected by horizontal interpolation.

The wide conversion processing circuits 68 and 69 also operate in the same manner as the conversion circuit 65 described above, and process wide conversion of the I and Q signals while also correcting the horizontal sync phase fluctuation. The filter calculation processing of the wide conversion processing circuits 65, 68, 69 is performed based on the clock CK1.

The embodiments of the present invention have been described above.

The digital VC shown in FIG.
The O29 may be configured as shown in FIG.

As shown, in this configuration, instead of the phase / amplitude conversion circuit 43 and the rectangular wave formation circuit 44 of FIG. 2, a phase-amplitude binary data converter 82, a comparator 83, and a phase threshold value generation circuit 84. Is provided. In this configuration, the cumulative phase data ps is directly converted into the binary clock CK1 by the function of the phase-amplitude binary data converter 82.

That is, in the binary data converter 82, the comparator 83 compares the accumulated phase data ps from the latch circuit 42 with the magnitude of the phase threshold value pr from the phase threshold value generating circuit 84, and ps ≧ pr When it is, a "1" level signal is output, and when ps <pr, a "0" level signal is output. At this time, the phase threshold pr is 180 ° (π radian)
Is. By doing so, the comparator 83
Is a binary clock CK1 locked to the burst signal
Can be output.

In the comparator 83, the accumulated phase data is converted into signed amplitude data, and the sign of the data is discriminated by the function of the threshold value generating circuit 84. You may make it output a "0" level signal at the time of a code | symbol.

The digital VCO 2 described above is used.
In the digital VCO 29 shown in FIG. 9 and FIG. 2, the outputs of the register 39, the adder 41, and the latch circuit 42 are all digital data whose maximum value is 2 to the power of X (X is a natural number). The transmission path is an X-bit bus.

The generation clock frequency of the system clock CK1 in the digital VCO 29 may be a frequency other than 4 and 8 times the subcarrier frequency fsc, for example, a frequency that is a multiple of 4 which is 8 times or more. Further, as the phase comparator forming the PLL in the clock generation circuit 26, a multivalued or binary input digital multiplier can be used.

[0093]

As described above, according to the present invention, a synchronization process capable of generating a highly stable burst lock clock and detecting the phase variation of the horizontal synchronization with high accuracy to contribute to signal processing. A circuit can be provided.

That is, according to the present invention, regardless of the standard / non-standard signal of the input video signal, the signal processing is basically performed by using one burst lock clock system, and the detected horizontal synchronization phase fluctuation is detected. Can be done with consideration.

Therefore, an interface circuit for data phase conversion, which is necessary when a plurality of types of system clocks are used, a standard / non-standard signal determination circuit, etc. are unnecessary.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a video signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a digital VCO according to an embodiment of the present invention.

FIG. 3 shows an operation of the digital VCO according to the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a horizontal synchronization phase fluctuation detection circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a signal processing circuit (sequential scan conversion circuit) according to an embodiment of the present invention.

FIG. 6 is a diagram showing an operation of the signal processing circuit (sequential scan conversion circuit) according to the embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a signal processing circuit (wide conversion circuit) according to an embodiment of the present invention.

FIG. 8 is a diagram showing an operation of the signal processing circuit (wide conversion circuit) according to the embodiment of the present invention.

FIG. 9 is a second digital VCO according to the embodiment of the present invention.
It is a figure which shows the structural example.

FIG. 10 is a diagram showing a configuration of a conventional clock generation circuit.

FIG. 11 is a diagram showing a configuration of a conventional video signal processing device.

[Explanation of symbols]

15 ... A / D converter, 18 ... Signal processing circuit, 24 ... Burst signal extraction circuit, 25 ... Synchronous signal separation circuit, 26 ... Digital clock generation circuit, 27 ... Phase comparator, 29 ...
Digital VCO, 31 ... Horizontal sync phase fluctuation detection circuit,
32 ... Filter coefficient control circuit, 33 ... Synchronous reproduction circuit, 4
0 ... Crystal oscillator, 41 ... Adder, 42 ... Latch circuit, 4
3 ... Phase-amplitude data converter

Claims (5)

[Claims] 1. An A / D converter for converting an input television signal into a digital signal, a means for separating and extracting a burst signal component contained in the digitally converted television signal, and a unit included in the digitally converted television signal. A means for separating and extracting the horizontal synchronization signal component, a digital PLL circuit for digitally generating a burst lock clock locked to the burst signal represented by the extracted burst signal component, and a horizontal synchronization represented by the extracted horizontal synchronization signal component. A synchronization processing circuit for a television apparatus, comprising: horizontal synchronization variation detecting means for obtaining a variation in the phase of a signal with the burst lock clock as a reference. 2. An A / D converter for converting an input television signal into a digital signal, a means for separating and extracting a burst signal component contained in the digitally converted television signal, and a means for including the digitally converted television signal. A means for separating and extracting the horizontal synchronization signal component, a digital PLL circuit for digitally generating a burst lock clock locked to the burst signal represented by the extracted burst signal component, and a horizontal synchronization represented by the extracted horizontal synchronization signal component. A horizontal synchronization fluctuation detecting means for obtaining the fluctuation amount of the phase of the signal with the burst lock clock as a reference; and a line interpolation filter for performing line interpolation processing on the digitally converted television signal using a predetermined filter coefficient. According to the fluctuation amount of the phase of the horizontal synchronizing signal detected by the horizontal synchronizing fluctuation detecting means, The filter coefficients used by down interpolation filter, the television signal processing circuit characterized by having a filter coefficient control means for changing such that the influence of variations in the phase of the horizontal sync signal is corrected by the line interpolation processing. 3. The television signal processing circuit according to claim 3, wherein the A / D converter and the line interpolation filter are the bar.
A television signal processing circuit, which operates in synchronization with a strok clock. 4. The television signal processing circuit according to claim 2, wherein the digital PLL circuit has a digital oscillator for generating a burst lock clock having a frequency corresponding to input data, and a burst signal component. A digital phase comparator for digitally obtaining a phase difference signal representing the phase difference between the burst signal and the divided clock obtained by dividing the burst lock clock, and the low frequency of the phase difference signal obtained by the digital phase comparator. A digital low-pass filter for extracting a component and outputting it as phase difference data, wherein the digital oscillator is
A television signal processing circuit, wherein phase difference data output from a digital low-pass filter is used as input data. 5. The television signal processing circuit according to claim 4, wherein the digital VCO is synchronized with a phase difference data output from the low-pass filter and a clock having a predetermined frequency, and the digital VCO has a predetermined reference. A cumulative addition means for adding and accumulating the phase data and outputting as phase data is compared with a value of the phase data output by the cumulative addition means and a predetermined threshold value, and a logical value 1 and a logical value are obtained according to the comparison result. A television signal processing circuit comprising a phase-to-two level clock converting means for outputting one of the values 0.