JPH084132B2 - Photoelectric conversion device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a photoelectric conversion device of a type that accumulates carriers generated by photoexcitation.

[Prior Art] FIG. 4 (A) is a schematic plan view of a photoelectric conversion device described in Japanese Patent Application No. 58-120755, and FIG. 4 (B) is a sectional view taken along the line AA ′. FIG. 4C is an equivalent circuit diagram thereof.

In each figure, photoelectric conversion cells are arranged on an n-silicon substrate 101, and each cell is electrically insulated from an adjacent cell by an element isolation region 102 made of SiO ₂ , Si ₃ N ₄ , or polysilicon. ing.

 Each cell has the following configuration.

Low impurity concentration formed by epitaxial technology
A p base region 104 and ap region 105 are formed on the n ⁻ region 103 by doping a p type impurity (for example, boron), and an n ⁺ emitter region 106 is formed in the p base region 104.

The p base region 104 and the p region 105 are the p channel described later.
It also serves as the source and drain of the MOS transistor.

An oxide film 107 is formed on the n ⁻ region 103 in which each region is formed in this way, and a gate electrode 108 of the MOS transistor and a capacitor electrode 109 are formed on the oxide film 107. The capacitor electrode 109 faces the p base region 104 with the oxide film 107 in between, and constitutes a capacitor for controlling the base potential.

In addition, the emitter electrode 110 connected to the n ⁺ emitter region 106, the electrode 111 connected to the p region 105, and the substrate 101.
Collector electrode with an ohmic contact layer on the back side of the
112 are formed respectively.

 Next, the operation of the photoelectric conversion cell will be described.

Light enters from the p base region 104 side, and carriers (here, holes) corresponding to the amount of light are accumulated in the p base region 104 (accumulation operation).

The base potential changes due to the accumulated carriers, and by reading the potential change from the emitter electrode 110, an electric signal corresponding to the amount of incident light can be obtained (reading operation).

Next, a refresh operation for removing holes accumulated in the p base region 104 will be described.

5 (A) and 5 (B) are voltage waveform diagrams for explaining the refresh operation.

As shown in FIG. 7A, the MOS transistor is turned on only when a negative voltage above the threshold is applied to the gate electrode 108.
N state.

To perform the refresh operation in FIG.
The emitter electrode 110 is grounded and the electrode 111 is kept at ground potential. Then, first, a negative voltage is applied to the gate electrode 108 to turn on the p-channel MOS transistor. As a result, the potential of the p base region 104 becomes a constant value regardless of the level of the accumulated potential. Then, the capacitor electrode 10
By applying a positive voltage pulse for refresh to 9,
The base region 104 is forward biased with respect to the n ⁺ emitter region 106, and the accumulated holes are removed through the grounded emitter electrode 110. Then, when the refresh pulse falls, the p base region 104 returns to the initial state of negative potential (refresh operation).

In this way, after the potential of the p base region 104 is set to a constant potential by the MOS transistor, a refresh pulse is applied to erase the residual charge, so that a new storage operation is performed without depending on the previous storage potential. be able to.
In addition, the residual charge can be quickly extinguished, and high-speed operation becomes possible.

Note that by applying a voltage for complete refresh to the electrode 111, the refresh operation can be completed simply by turning on the MOS transistor.

Thereafter, the operations of accumulating, reading, and refreshing are similarly repeated.

[Problems to be Solved by the Invention] However, in the above conventional photoelectric conversion device, the refresh MS transistor is formed on the light receiving surface, the wiring for supplying a constant voltage to the electrode 111, the gate of the refresh MOS transistor. There is a problem in that the aperture ratio is reduced particularly when an area sensor is configured because a wiring or the like for supplying a pulse is required. Also, the large number of drive pulses complicates the configuration.

[Means for Solving the Problems] In the photoelectric conversion device according to the present invention, a plurality of photoelectric conversion cells having a semiconductor region for accumulating carriers generated by photoexcitation are arranged, and the semiconductor regions of adjacent photoelectric conversion cells are arranged. The insulated gate type transistors serving as the first and second main electrode regions are provided, and the insulated gate type transistors are turned on by applying a first potential to the gates of the insulated gate type transistors, and the plurality of photoelectric conversion cells are provided. Control of resetting a signal of the semiconductor region of the semiconductor device and turning off the insulated gate transistor by applying a second potential to the gate of the insulated gate transistor to separate the semiconductor regions of the plurality of photoelectric conversion cells. In addition, the gate electrode of the insulated gate transistor is shielded from light. [Operation] Insulated gate transistor When a voltage is applied to the data in the ON state to the gate electrode can be simultaneously set to a constant potential regardless of the potential of the semiconductor region of a desired number of cells in the accumulation amount of carrier. Further, when the insulated gate type transistor is turned off, the photoelectric conversion cells can be electrically isolated from each other.

Also, an insulated gate transistor in which a plurality of photoelectric conversion cells having a semiconductor region for accumulating carriers generated by photoexcitation are arranged and the semiconductor regions of adjacent photoelectric conversion cells are used as the first and second main electrode regions are provided. The gate of the insulated gate transistor is provided by turning on the insulated gate transistor by applying a first potential to the gate of the insulated gate transistor to reset signals in the semiconductor regions of the plurality of photoelectric conversion cells. Since the insulated gate transistor is turned off by applying a second potential to the semiconductor region so that the semiconductor regions of the plurality of photoelectric conversion cells are separated, a reset for eliminating accumulated carriers in each photoelectric conversion cell is performed. Of the gate for the transistor for power supply, the wiring for supplying a signal to the gate, and the other of the transistor for reset Necessary to fabricate a main electrode region in each photoelectric conversion cell is eliminated.

Therefore, the aperture ratio of the portion related to photoelectric conversion in each photoelectric conversion cell is not reduced. Moreover, since the gate electrode of the insulated gate transistor is formed in the boundary region between adjacent photoelectric conversion cells, it does not affect the aperture ratio of the photoelectric conversion cells.

Further, in the present invention, since the gate electrode of this insulated gate type transistor is shielded from light, optical noise is not mixed into the gate electrode, and the boundary portion of each photoelectric conversion cell is shielded from light to prevent each photoelectric conversion. Optical cells are correctly separated by the cells, and crosstalk of optical signals between photoelectric conversion cells hardly occurs.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 (A) is a schematic plan view of an embodiment of the photoelectric conversion device according to the present invention, FIG. 1 (B) is a sectional view taken along the line I-I, and FIG. 1 (C) is its II. It is a II sectional view.

In each figure, an n ⁻ layer 2 serving as a collector region is formed on an n type silicon substrate 1 by epitaxial growth, and a p base region 3 and an n ⁺ emitter region 4 are formed therein to form a bipolar transistor. .

The p base regions 3 are arranged two-dimensionally as shown in FIG. 1 (A), and each horizontal cell is separated from the upper and lower cells by an element isolation region. The element isolation region is composed of an oxide film 5 formed by LOCOS oxidation and an n ⁺ region 6 formed thereunder as shown in FIG.

In addition, between the p base regions 3 adjacent in the horizontal direction,
As shown in FIG. 1 (B), a gate electrode 8 is formed with the oxide film 7 interposed therebetween. Therefore, p-channel MOS is formed by using the adjacent p base regions 3 as source / drain regions.
A transistor is configured.

This MOS transistor is a normally-off type, and is in an OFF state if the potential of the gate electrode 8 is the ground potential or a positive potential. Therefore, p base region 3 between adjacent cells is electrically isolated. On the contrary, when the potential of the gate electrode 8 is a negative potential exceeding the threshold potential Vth, the gate electrode 8 is turned on, and the p base regions 3 of the cells are electrically connected to each other.

The gate electrode 8 is commonly connected to the drive line 10 row by row as shown in FIG. 3A, and the capacitor 9 for controlling the potential of the p base region 3 is also similarly connected to the drive line 10.
It is connected to the. As shown in the figure, the drive line 10 extends horizontally on the oxide film 5 which is an element isolation region.

Further, after forming the transparent insulating layer 11, an emitter electrode 12 is formed, and the emitter electrode 12 is connected to a vertical line 13 for each column. Further, a collector electrode 14 is formed on the back surface of the substrate 1 with an ohmic contact layer interposed therebetween.

FIG. 2 (A) is an equivalent circuit diagram of one cell in this embodiment, and FIG. 2 (B) is a voltage waveform diagram for explaining its operation.

First, it is assumed that carriers (here, holes) corresponding to the amount of input light are accumulated in the p base region 3. Also, the terminal of the transistor Qc has a negative voltage Vc and the collector electrode
It is assumed that positive voltages are applied to 14 respectively.

In this state, drive line 10 is supplied with positive voltage pulse φd
Apply only Trd. As a result, the potential of the p base region 3 rises via the capacitor Cox, and the signal is read out to the emitter electrode 12 as described above.

Then, a negative voltage pulse φd is applied to the drive line 10 for the period Tr.
Apply only h. This turns on the p-channel MOS transistor Qc, resetting the base potential to the voltage Vc,
A complete refresh is done. Further, the pulse φr is set to the high level and the transistor Qr is turned on to reset the vertical line 13.

As described above, the refresh operation is performed after turning on the MOS transistor Qc and then turning on the emitter electrode 1
The pulse 2 of positive voltage may be applied while 2 is grounded. In this case, Vc does not have to be a negative voltage and may be a ground voltage or a positive voltage.

When the above refresh operation is completed, the accumulation operation is started, and the same operation is repeated thereafter.

 FIG. 3 is a schematic circuit diagram of this embodiment.

In this embodiment, the photoelectric conversion cells are arranged in m × n areas. The specific structure is as shown in FIG.

In the cells C _{11 to} C ₁ n, C _{21 to} C ₂ n, ... Of each horizontal line, the gate electrode 8 of the MOS transistor Qc is commonly connected to each drive line 10, and each drive line 10 is illustrated. Vertical scan pulses φd _{1 to} φdm are respectively input from the horizontal scan circuits which are not provided. The waveform of the vertical scanning pulse is as shown in FIG.

Further, the MOS transistor Qc having the p-base region 3 of each cell as a source / drain region is connected in series for each horizontal line. However, the edge cells C _{11 to} Cm ₁
P regions for forming MOS transistors Qc are formed in the respective cells, and the MOS transistors Qx ₁ to Cmn are formed in the cells C ₁ n to Cmn.
Qxm is connected in series. Then, a constant voltage Vc is applied to both ends.

Further, the cells C _{11 to} Cm ₁ , C _{12 to} Cm ₂ in each vertical direction, ...
The emitter electrodes in are connected to the vertical lines 13 in common, and the vertical lines 13 are respectively connected to the reset transistors Qr _{1 to} Qr.
It is grounded via rn. A reset pulse φr is commonly input to the gate electrodes of the transistors Qr _{1 to} Qrn.

Therefore, when a positive drive pulse φd is applied to an arbitrary drive line 10, the signals S _{1 to} Sn from the cells on that line are applied.
Are read on the vertical lines 13, respectively.

The read signals S _{1 to} Sn are serially read to the outside by a horizontal scanning circuit (not shown).

Then, when a negative voltage pulse φd is applied, all the MOS transistors Qc and Qx of that line are turned on, all the p base regions 3 of that line are reset to a constant voltage Vc, and a complete refresh operation is performed. . At the same time, the pulse φr turns on the transistors Qr _{1 to} Qrn, grounding each vertical line 13 and removing the residual charge.

As described above, in this embodiment, even if the area sensor is configured, no special wiring is required for performing the complete refresh operation. That is, the pulses required to drive the area sensor are substantially only the vertical scanning pulses φd _{1 to} φdm and the reset pulse φr.

In addition, MO for complete refresh as in the past
Since the S transistor is not formed on the light receiving surface, it is possible to obtain an area sensor that can operate at high speed without reducing the aperture ratio.

[Effects of the Invention] As described in detail above, in the photoelectric conversion device according to the present invention, a plurality of photoelectric conversion cells having a semiconductor region for accumulating carriers generated by photoexcitation are arranged and adjacent photoelectric conversion cells are provided. An insulated gate transistor having a semiconductor region as the first and second main electrode regions is provided, and the insulated gate transistor is turned on by applying a first potential to the gate of the insulated gate transistor, and the plurality of insulated gate transistors are turned on. By resetting a signal in the semiconductor region of the photoelectric conversion cell and applying a second potential to the gate of the insulated gate transistor, the insulated gate transistor is turned off to separate the semiconductor regions of the plurality of photoelectric conversion cells. Therefore, the gate for the reset transistor for eliminating the accumulated carriers of each photoelectric conversion cell and the Necessary to fabricate the other main electrode region of the transistor wiring and reset for supplying a signal to the over preparative in each photoelectric conversion cell is eliminated.

Therefore, the aperture ratio of the portion related to photoelectric conversion in each photoelectric conversion cell is not reduced. Moreover, since the gate electrode of the insulated gate transistor is formed in the boundary region between adjacent photoelectric conversion cells, it does not affect the aperture ratio of the photoelectric conversion cells.

Further, in the present invention, since the gate electrode of this insulated gate type transistor is shielded from light, optical noise is not mixed into the gate electrode, and the boundary portion of each photoelectric conversion cell is shielded from light to prevent each photoelectric conversion. Optical cells are correctly separated by the cells, and crosstalk of optical signals between photoelectric conversion cells hardly occurs.

[Brief description of drawings]

FIG. 1 (A) is a schematic plan view of an embodiment of a photoelectric conversion device according to the present invention, FIG. 1 (B) is a sectional view taken along the line I-I, and FIG. 1 (C) is its II. -II sectional view, FIG. 2 (A) is an equivalent circuit diagram of one cell in the present embodiment, FIG. 2 (B) is a voltage waveform diagram for explaining its operation, and FIG. A schematic circuit diagram of this embodiment, FIG. 4 (A) is a schematic plan view of a photoelectric conversion device described in Japanese Patent Application No. 58-120755, and FIG.
4A is a sectional view taken along the line -A ', FIG. 4C is an equivalent circuit diagram thereof, and FIGS. 5A and 5B are voltage waveform diagrams for explaining the refresh operation. 1 n-type silicon substrate 2 n ^- layer 3 p base region 4 n ⁺ emitter region 5 oxide film 8 gate electrode 9 capacitor electrode 10 drive line 12 emitter Electrode 13 ... Vertical line 14 ... Collector electrode

Claims (1)

[Claims] 1. An insulated gate in which a plurality of photoelectric conversion cells having semiconductor regions for accumulating carriers generated by photoexcitation are arrayed, and the semiconductor regions of adjacent photoelectric conversion cells serve as first and second main electrode regions. Type transistor is provided, and by applying a first potential to the gate of the insulated gate type transistor, the insulated gate type transistor is turned on to reset the signals of the semiconductor regions of the plurality of photoelectric conversion cells, and the insulated gate type transistor is provided. By applying a second potential to the gate of the transistor, the insulated gate transistor is turned off to control the semiconductor regions of the plurality of photoelectric conversion cells to be separated, and the gate electrode of the insulated gate transistor is shielded from light. A photoelectric conversion device characterized by the above.