JPH08330957A - D/a conversion device - Google Patents

Abstract

PURPOSE: To perform oversampling D/A conversion of a high multiplying factor with a simple and inexpensive constitution. CONSTITUTION: Input digital data DATAIN having a sampling frequency Fs is subjected to n-fold oversampling by an n-fold oversampling digital filter 20. In this case, the band of >=Fs /2 is stopped. Digital data DATAP having a frequency nFs is subjected to linear interpolation by an interpolation filter 22 by resampling in a period 1/mnFs , delay by the period 1/mnFs , and addition of resampled data and each delay data to multiply the sampling frequency by (m) furthermore. With respect to digital data DATAS having the frequency mnFs after linear interpolation, sampled data are subjected to D/A conversion by k D/A converters 271 to 27k in order one by one, and outputs of D/A converters 271 to 27k are added by an analog adder 29.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter,
In particular, the present invention relates to a D / A conversion device that performs D / A conversion by oversampling digital data to be D / A converted.

[0002]

2. Description of the Related Art In a digital audio device such as a CD player, a DAT, and an MD system, digital data of a sampling frequency F _s reproduced from a recording medium is not directly D / A converted, but a band of F _s / 2 or more is blocked. While oversampling by 8 times, for example, D
/ A conversion is performed. The reason is that if the digital data is D / A converted as it is, the step change width of the D / A converted output becomes large and a large output distortion occurs, and folding noise exists in a relatively low range, so the output waveform is smooth. In order to surely remove the aliasing noise with the post filter (smoothing filter), the high-order steep characteristic must be obtained, which is difficult and expensive to manufacture, and the phase characteristic in the high frequency range is deteriorated. This point, D / A
If oversampling is performed before the conversion, the step change width of the D / A conversion output can be reduced to reduce the output distortion, and the aliasing noise component shifts to the high frequency side. Characteristics, easy manufacture, low cost, and good phase characteristics can be obtained.

Oversampling is 16 times more than 8 times,
The effect increases as the magnification increases from 16 times to 32 times. However, it is difficult to increase the D / A conversion speed of a D / A converter for mass production of audio and the like due to cost constraints, and the D / A converter of about 8 times (8F _s ) is the limit. Therefore, conventionally, by combining a plurality of D / A converters for mass production, which do not have a high D / A conversion speed,
A method of realizing high-magnification oversampling by performing A conversion has been proposed. Specifically, as shown in FIG. 6, F _s / 2 is applied to the input digital data (16-bit parallel data) by using the digital filter 10.
32 times oversampling is performed while blocking the above band. Fill in (D-F / is constituted by F of 16) 11 ₁ to 11 ₄ outputs the cascaded four-stage latch circuit of the digital filter 10, the 32F _s clock C
K is given and delayed by T (= 1 / 32F _s ) each, and the outputs of the respective latch circuits 11 _{1 to} 11 ₄ are individually applied to the D / A converter 12
Enter _{1 to} 12 ₄ . Each D / A converter 12 _{1 to} 12 ₄
Are those sampling frequency to convert the digital data 8F _s, according 8F _s clock CK ₁ ~CK ₄ input from the timing generating circuit (not shown), a digital data input from the corresponding latch circuits 11 ₁ to 11 ₄ D / A conversion. Each D / A converter 12 _{1 to} 12
₄ is a clock CK _{1 of} 8F _s whose phase is shifted by 90 °
Although only 8F _s D / A conversion is performed according to CK ₄ , the D / A conversion output is added by the adder 13 (a 1/4 multiplier is provided on each input side of the adder 13). 32F _s D / A conversion is equivalently performed.

The output of the adder 13 is smoothed by the post filter 14, but the output distortion of the adder 13 is very small because it is 32 times oversampled, and the aliasing noise component is close to 32 F _s. Since it is shifted, the post filter 14 can be made to have a low-order and fairly gentle characteristic, which is extremely easy and inexpensive to manufacture,
It is possible to obtain quite good phase characteristics. Further, by adding the outputs of the plurality of D / A converters 12 _{1 to} 12 ₄ , it is possible to attenuate the uncorrelated noise components generated by the D / A converters 12 _{1 to} 12 ₄ .

[0005]

[SUMMARY OF THE INVENTION However, in the prior art described above, although it is possible reduce the burden of the D / A converter, the digital filter must perform advanced filtering operations at a sampling rate of 32F _s,
There is a problem that an expensive digital filter must be used because the operation speed is high and the circuit configuration is complicated. The present invention is simple in view of the above-mentioned problems of the prior art,
D that can perform high-magnification oversampling with an inexpensive configuration
The purpose is to provide a / A converter.

[0006]

In the D / A converter of the present invention, digital data having a sampling frequency F _s is oversampled n times, and at this time, F _s /
An n-fold oversampling digital filter means for blocking two or more bands, and linear interpolation for multiplying the sampling frequency by m times are performed on the digital data of the sampling frequency nF _s output from the n-fold oversampling digital filter means. Interpolating means, k D / A converting means for sequentially taking sample data one by one for digital data output from the interpolating means, and performing D / A conversion, and k D / A converting means. And an adder that adds the outputs of the sampling frequency nF _s and the interpolation means add 1
/ Sampling means for resampling period of MnF _s, delaying the digital data output from the sampling means by the period of 1 / MnF _s and (m-1) stage delay means, the output of the sampling means and the delay means And adding means for adding.

[0007]

According to the D / A converter of the present invention, the n-times oversampling digital filter means performs n-times oversampling with respect to the digital data of the sampling frequency F _s, this time, F _s / 2 or more Stop the band. Resampling at a period of 1 / mnF _s by interpolation means for nF _s digital data,
The sampling frequency is further multiplied by m by performing linear interpolation by delaying each cycle of 1 / mnF _s and adding resampled data and each delayed data. And mnF after linear interpolation
_For the digital data of _s , the sample data is sequentially divided by k D / A converting means one by one, and D / A-converted.
The output of the / A conversion means is added by the addition means. As a result, even when oversampling by mn times, the sampling frequency of the digital filter means may be nF _s , the calculation speed may be low, and the burden on the circuit configuration may be small. Further, since the interpolating means also only performs a simple process of linear interpolation, the circuit configuration is simple, and the device as a whole is simple and inexpensive.

[0008]

1 is a circuit diagram of a D / A converter according to an embodiment of the present invention. 20 is a predetermined filtering process according to the clock CK of 8F _s for the input digital data DATA _IN of the sampling frequency F _s (16-bit parallel data), the n-times oversampling while preventing a frequency F _s / 2 or more bands An n-fold oversampling digital filter, 21 is a multiplication circuit that outputs a clock CK 'that is the clock CK frequency multiplied by m, and 22 is a digital data DATA of the sampling frequency nF _s output from the n-fold oversampling digital filter 20. It is an interpolation filter that performs interpolation for increasing the sampling frequency by m times with respect to _P.

A sampling circuit 23 of the interpolation filter 22 resamples the digital data DATA _P with a clock CK 'to multiply the sampling frequency by m (here, it is composed of 16 D-F / Fs). , 24 _{1 to} 24
_m-1 is a latch circuit of (m-1) stages cascaded to the output side of the sampling circuit 23 (here, 16 D circuits each).
-F / F), and the digital data DATA _Q of the sampling frequency mnF _s output from the sampling circuit 23 is T = 1 /
Delay every mnF _s period. Reference numeral 25 is a digital adder for adding the digital data (resampling data) DATA _Q output from the sampling circuit 23 and each delay data DATA _{R1 to} DATA _Rm-1 output from the latch circuits 24 _{1 to} 24 _m-1 , 26 Is 1 / m to the output of the digital adder 25
Is a digital multiplier for multiplying
5 and the digital multiplier 26 constitute an averaging means. By the interpolation filter 22 configured in this way, the digital data DATA _P is oversampled by m times in sampling frequency by linear interpolation, and is output as digital data DATA _S.

27 _{1 to} 27 _k are interpolation filters 22 respectively.
Of k D / A converters connected in parallel to the output side of
Each of the D / A converters 27 _{1 to} 27 _k D / A-converts digital data having a sampling frequency of mnF _s / k. Two
8 is k clocks CK _{1 to} CK whose frequency is mnF _{s and} whose phase is shifted by 360 ° / k based on the clock CK ′.
The _k generates a timing generating circuit for outputting separately the D / A converter 27 ₁ ~ 27 _k. The D / A converter 27 _i inputs the digital data DATA _S output from the interpolation filter 22 at the timing when the clock CK _i is input and performs D / A conversion (i = 1, 2, ..., K). . Reference numeral 29 is an analog adder for adding the outputs of the D / A converters 27 _{1 to} 27 _k , and 30 is a post filter (LPF) for smoothing the output of the analog adder 29.

Next, the operation of the above embodiment will be described with reference to the time chart of FIG. 2, the frequency characteristic diagram of FIG. 3 and the interpolation operation explanatory diagram of FIG. For convenience of explanation,
The description will be made assuming that n = 8, m = 4, and k = 4. The input digital data DATA _IN of the sampling frequency F _s is shown in FIG.
As shown in (1), F close to the signal band (0 to F _s / 2)
There is a folding noise component above _S / 2. n-times oversampling digital filter 20 with the sampling frequency and n = 8 times, the signal bandwidth of 0 to F _s / 2 is passed, F _S / 2 or more (however, 4F _s or less) because the band of inhibiting In the digital data DATA _P over-sampled by n times, as indicated by the diagonal lines in FIG.
Aliasing noise component is shifted to the 8F _s -F _S / 2 or more. _{However, 8F s ± F S / 2,16F} s ± F S / 2,2
There is a folding noise component in 4F _s ± F _S / 2, 32F _s ± F _S / 2, ...

Digital data DATA _P (= ...
_{D 0, D 1, D 2} , ··) is resampled according to the clock CK' frequency 32F _s by the sampling circuit 23, the sampling frequency is m = 4 times the digital data _{DATA Q (= ··, D 0} , D ₀ , D ₁ , D ₁ , D ₁ , D
₁ , D ₂ , D ₂ , D ₂ , D ₂ , ...) are obtained (see FIGS. 2 and 4). However, the frequency spectrum of digital data DATA _Q is the same as that of DATA _P (see Fig. 3 (2)). The digital data DATA _Q is sequentially latched by the latch circuits 24 _{1 to} 24 ₄ according to the clock CK ′, and T = 1.
It is delayed by a cycle of / 32F _s . The digital data DATA _Q is the delay data of the latch circuits 24 _{1 to} 24 ₄ .
After being added together with DATA _{R1 to} DATA _{R3 in the} digital adder 25 and set to 1 / m = 1/4 in the digital multiplier 26, digital data DATA _S obtained by linearly interpolating the digital data DATA _P as shown in FIG. {= ..., D ₀ ,
(D ₀ + 3D ₁ ) / 4, (2D ₀ + 2D ₁ ) / 4, (3
D ₀ + D ₁ ) / 4, D ₁ , (D ₁ + 3D ₂ ) / 4, (2
D ₁ + 2D ₂ ) / 4, (3D ₁ + D ₂ ) / 4, D ₃ ,
.} Is formed (see FIG. 2).

Considering the system from the output side of the sampling circuit 23 to the digital multiplier 25, the transfer function H (z) is H (z) = (1 + z ^-1 + z ^-2 + z ^-3 ) / 4. = (1/4) * (1 + z- ¹ ) (1 + z- ² ). If z ^-1 = exp (-jωT), then H (z) = {(1/2) (1 + exp (-jωT))}-{(1/2) (1 + exp (-j2ωT))} = exp ( -JωT / 2)-{(1/2) (exp (jωT / 2) + exp (-jωT / 2))}-exp (-jωT)-{(1/2) (exp (jωT) + exp (-jωT ))} = Exp (−3jωT / 2) · cos (ωT / 2) · cos (ωT). Amplitude characteristic M is, M = | cos (ωT / 2) · cos (ωT) | becomes, as shown by a broken line M in FIG. _{3 (2), 8F s,} 16
F _s, with a dip in 24F _s.

Therefore, the digital data DATA _P is oversampled four times while passing through the interpolation filter 22, and at the same time, 8F _s ± F _S / 2 and 16F _s ± F _S /
2,24F _s ± F _S / 2 of the folding noise components will be removed (see FIG. 3 (3)).

The digital data DATA _s of the sampling frequency 32F _s output from the interpolation filter 22 are divided into one by _one according to the rising timing of the clocks CK _{1 to} CK ₄ , and the D / A converters 27 ₁ to 27 ₁ to 27 is inputted to _4, is converted D / a (see FIG. 2). For each D / A converter 27 _{1-27 4} the sampling frequency performs D / A conversion operation of 8F _s, 8F during output _{s ± F s / 2,16F s ±} F s / 2,24F s
A folding noise component occurs at ± F _s / 2 (Fig. 3
(4)), 8F _s , 16F _s , 24F _s
/ A converter 27 _{1-27 4} output spectrum since the phase is shifted by _{90 °, 8F s ± F s} / 2,16F s ± F s / 2 when viewed in the output of the analog adder 29,
The folding noise components of 24F _s ± F _s / 2 are canceled (see FIG. 3 (5)). By adding the D / A conversion outputs, the uncorrelated noise components of the D / A converters 27 _{1 to} 27 ₄ are also attenuated by the cancellation. Therefore, the input digital data DATA _IN is D / A converted while being oversampled 32 times.

Due to the 32 × oversampling, the first-order folding noise component above the signal band is 32F _s −F _s.
Shifted to / 2 or more. Therefore, the post filter 30 for smoothing the output of the analog adder 27 has a very gradual characteristic, can have a very low order, is easy to manufacture and is inexpensive, and has a phase characteristic (especially high) in the signal band. The phase characteristics in the range) can be made quite good.

According to this embodiment, even when performing 32-times oversampling, the oversampling digital filter 20 may sampling frequency in 8F _s, requires less burden on the circuit configuration with requires only a calculation speed is low . The 8-times oversampling digital filter for audio is easily available since mass-produced inexpensive ICs are commercially available. Further, since the interpolation filter 22 also only performs a simple process of linear interpolation, the circuit configuration is simple and the cost is not burdened.
Further, the sampling frequency of the D / A converters 27 _{1 to} 27 ₄ may be 8 F _s , and the conversion speed may be low and the load on the circuit configuration may be small. An inexpensive 8F _s D / A converter for audio is also available on the market, so it is easy to obtain. From the above, the configuration as a whole D / A conversion device can be made simple and inexpensive.

In the above embodiment, n = 8 and m = k
However, the present invention is not limited to this. For example, n = 4, m = 8, k = 2, etc.
Of course, other values may be combined as long as n, m, and k ≧ 2. In addition, the interpolation filter, instead of multiplying the output of the digital adder 25 by 1 / m,
As shown in (1) or (2), the sampling circuit 23
The digital multiplier 31 or 32 provided on the input side or the output side of 1 is used for multiplication by 1 / m, or FIG.
It may be multiplied separately 1 / m is provided a digital multiplier 33 ₁ ~ 33 _m individually to each input of the digital adder 25 as shown in.

[0019]

According to the D / A converter of the present invention, the n-fold oversampling digital filter means
The digital data of the sampling frequency F _s is oversampled n times, and the band of F _s / 2 or more is blocked at this time. The digital data to interpolation means nF _s, 1 / MnF resampling in a period of _s, the delay of each period of 1 / MnF _s, the sampling frequency by performing linear interpolation by adding the resampled data and the delayed data Furthermore, it is m times. Then, with respect to the digital data of mnF _s after the linear interpolation, the sample data is sequentially divided by k D / A converting means one by one and D / A converted, and the output of the D / A converting means is added by the adding means. Therefore, even when oversampling of mn times is performed, the digital filter means has a sampling frequency of n.
F _s is sufficient, the calculation speed is low, and the burden on the circuit configuration is small. Further, since the interpolating means also only performs a simple process of linear interpolation, the circuit configuration is simple, and the device as a whole is simple and inexpensive.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a D / A conversion device according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the D / A conversion device.

FIG. 3 is a frequency spectrum of digital data output from each unit of the D / A converter.

FIG. 4 is an explanatory diagram showing a linear interpolation operation of an interpolation filter.

FIG. 5 is a circuit diagram showing a modified example of an interpolation filter.

FIG. 6 is a circuit diagram of a conventional D / A conversion device.

[Explanation of symbols]

20 n times oversampling digital filter 22 Interpolation filter 23 Sampling circuit 24 _{1 to} 24 _m-1 latch circuit 25 Digital adder 26, 31, 32, 33 _{1 to} 33 _m Digital multiplier 27 _{1 to} 27 _k D / A converter 28 Timing Generation Circuit 29 Analog Adder 30 Post Filter

Claims (1)

[Claims] 1. An n-fold over-sampling digital filter means for over-sampling digital data having a sampling frequency F _s by n-fold and blocking a band of F _s / 2 or more, and an n-fold over-sampling digital filter. Interpolation means for interpolating the sampling frequency nF _s of the digital data output from the means, and one sample data for the digital data output from the interpolation means. Import in sequence D /
The D / A conversion means for A conversion, and the addition means for adding the outputs of the D / A conversion means for k are provided, and the interpolation means is a sampling output from the n times oversampling digital filter means. Frequency nF _s
Sampling means for resampling the digital data of 1 / mnF _s and digital data output by the sampling means for 1 / m
A D / A conversion device comprising: (m-1) stage delay means for delaying each cycle of nF _s ; and adder means for adding the outputs of the sampling means and each delay means.