JPH08327978A - Active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE: To obtain a device which has a high opening rate and long service time and prevents the occurrence of a decrease in after-images by connecting counter electrodes to scanning electrodes and impressing an AC voltage nearly positive/negative symmetrical with the non-selecting voltage of scanning voltage as reference on pixel electrodes. CONSTITUTION: The driving of the device is executed by charging and holding the voltage to be impressed on liquid crystals in the pixel electrodes 104 formed in a matrix form by switching active elements. The counter electrodes 105 of this device are connected to the scanning electrodes. Thereby, the scanning electrodes are made to commonly have the role of the counter electrode wirings to supply the voltage to the counter electrodes 105 form outside. The need for the counter electrode wirings is thus eliminated, these regions can be used as opening regions, and the opening rate is improved. The device is so constituted that the AC voltage nearly positive/negative symmetrical with the non- selecting voltage of the scanning voltage as the reference is impressed on the pixel electrodes 105. As the result, the driving of the liquid crystals with the AC voltage is made possible and the service time is improved even if the non- selecting voltage of the scanning voltage is used as the counter voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using an active element typified by a thin film transistor (TFT) is widely used as a display terminal for OA equipment because of its thinness and light weight and high image quality comparable to a cathode ray tube. Is beginning to The display system of this liquid crystal display device is roughly classified into the following two types. One is a method in which the liquid crystal is sandwiched between two substrates having transparent electrodes, operated by a voltage applied to the transparent electrodes, and light transmitted through the transparent electrodes and incident on the liquid crystal is modulated and displayed. Currently, all popular products use this method. The other is a method in which the liquid crystal is operated by an electric field almost parallel to the substrate surface between two electrodes formed on the same substrate, and the light incident on the liquid crystal from the gap between the two electrodes is modulated and displayed. Although there is no product using this method, it is a promising technology for an active matrix liquid crystal display device because of its features such as wide viewing angle and low load capacity. Regarding the characteristics of the latter method, Japanese Patent Application Publication No. 5-505247 and Japanese Patent Publication No. 63-219.
It is described in No. 07.

[0003]

However, in the display system in which the liquid crystal is operated by an electric field almost parallel to the substrate surface, the opaque electrodes are formed in a comb-teeth shape, so that the opening area through which light can be transmitted is small and the display screen is small. However, there is a problem that it is necessary to use a bright backlight with high power consumption to solve the problem. Therefore, it is necessary to reduce the number of electrodes and the number of wirings connecting the electrodes as much as possible to expand the opening region, that is, improve the aperture ratio. Further, when another electrode having a different potential approaches the two electrodes for controlling the alignment of the liquid crystal, the alignment of the liquid crystal is disturbed and an alignment defect region (domain) is generated. As a result, there is a problem that the effective aperture area is reduced and the aperture ratio is lowered, and it is necessary to reduce the alignment defect region and improve the effective aperture ratio.

The present invention solves the above problems, and an object of the present invention is to provide an active matrix type liquid crystal display device having a high aperture ratio in the active matrix type liquid crystal display device using the latter display system. It is in.

Another object of the present invention is to provide an active matrix type liquid crystal display device in which a defective alignment region (domain) does not occur.

[0006]

According to the active matrix type liquid crystal display device of the present invention, a plurality of scanning electrodes on the substrate, a plurality of signal electrodes intersecting the plurality of scanning electrodes in a matrix, and a plurality of scanning electrodes. A plurality of semiconductor switching elements formed corresponding to the respective intersections of the electrodes and the plurality of signal electrodes, a plurality of pixel electrodes connected to each of the plurality of switching elements, and a plurality of scanning electrodes. And a plurality of counter electrodes are formed.

Each of the plurality of pixel electrodes and the plurality of counter electrodes is arranged in each region surrounded by the plurality of scanning electrodes and the plurality of signal lines. An alternating voltage that is substantially positive-negative symmetrical with respect to the non-scanning voltage of the scanning electrode is applied to the corresponding pixel electrode by each of the plurality of switching elements.

The semiconductor switching element is preferably a thin film transistor element having enhancement type characteristics. The absolute value of the threshold value V _TH of such a thin film transistor element is set to exceed the absolute value of the maximum voltage V _0N applied to the liquid crystal layer in order to maximize the light transmittance of the liquid crystal layer, or , The maximum voltage V _ON applied to the liquid crystal layer in order to maximize and minimize the light transmittance of the liquid crystal layer.
It is better to exceed 1/2 of the difference between the minimum voltage V _OFF and the minimum voltage V _OFF .

Further, according to the aspect of the active matrix type liquid crystal display device of the present invention, the substrate on which the semiconductor switching elements are formed has a protective film for protecting these semiconductor switching elements, and semiconductor switching is performed on the protective film. A back electrode formed corresponding to each of the elements. Alternatively, the substrate on which the plurality of semiconductor switching elements are formed has a back electrode formed below these semiconductor switching elements via an insulating film. This back electrode is preferably arranged along the scan electrode.

Further, according to the aspect of the active matrix type liquid crystal display device of the present invention, the substrate on which the plurality of semiconductor switching elements are formed has a protective film for protecting these semiconductor switching elements. Impurities are ion-implanted on the top. Alternatively, the substrate on which the plurality of semiconductor switching elements are formed has an insulating film under these semiconductor switching elements, and impurities are ion-implanted on the insulating film.

Further, according to the aspect of the active matrix type liquid crystal display device of the present invention, a plurality of enhancements formed corresponding to the intersections of the plurality of scanning electrodes and the signal electrodes arranged in a matrix on the substrate. Each of a plurality of pixel regions surrounded by a plurality of scan electrodes and a plurality of signal electrodes on the substrate, and a pixel electrode connected to the corresponding semiconductor switching element. , And counter electrodes connected to the corresponding scanning lines are alternately arranged in a comb shape. A thin film transistor element is preferable as the semiconductor switching element.

According to an embodiment of the thin film transistor device, the semiconductor active layer is doped with acceptors or donors. Alternatively, the semiconductor active layer is made of an amorphous silicon film.

Further, according to an embodiment of the thin film transistor element, the gate electrode is offset to the source electrode or drain electrode side. A gap may be added to the gate electrode.

[0014]

Next, the operation of the present invention will be described.

The active matrix type liquid crystal display device is driven by switching the voltage applied to the liquid crystal to the active element and charging and holding the voltage in the pixel electrodes divided and formed in a matrix.

In the present invention, first, the counter electrode is connected to the scan electrode. Thus, the scanning electrode can also serve as the counter electrode wiring for supplying a voltage to the counter electrode from the outside, and the counter electrode wiring can be omitted. Secondly, an AC voltage that is substantially positive and negative symmetrical with respect to the non-selection voltage of the scanning voltage is applied to the pixel electrode. As described above, a transistor having enhancement type characteristics is formed and used as a switching element capable of applying an AC voltage to the pixel electrode. This allows the second
Thus, the negative voltage can be held with respect to the non-selection voltage of the scanning voltage charged in the pixel electrode. As a result, the pixel electrode is charged and held with an AC voltage that is substantially positive and negative symmetrical with respect to the non-selection voltage of the scanning voltage, and the AC voltage can be applied to the liquid crystal.

According to the first aspect, the counter electrode wiring becomes unnecessary,
The region can be used as an opening region, and the aperture ratio can be significantly improved. However, in the conventional active matrix type liquid crystal display device, if the voltage of the counter electrode (counter voltage) is matched with the non-selection voltage of the scanning voltage, direct current drive is possible, but alternating current drive is not possible for the reason described later. This is because when the liquid crystal is driven by direct current, it deteriorates due to a steady current flowing through the liquid crystal layer and the service life is significantly reduced. Therefore, according to the second aspect, the liquid crystal can be driven by the AC voltage even when the non-selection voltage of the scanning voltage is used as the counter voltage (even if the counter voltage is matched with the non-selection voltage), and the service life is improved. Let

Here, in the present invention, the reason why the liquid crystal can be AC-driven by using the non-selection voltage of the scanning voltage as the counter voltage will be described below.

Most transistor elements used as typical active elements used in conventional active matrix liquid crystal display devices have a gate voltage of 0.
The drain current starts to flow near V (see FIGS. 6 and 502), that is, the gate threshold voltage V _TH
Is around 0V. Therefore, if the non-selection voltage of the scanning voltage is used as the counter voltage, the negative voltage with respect to the counter voltage (non-selection voltage) cannot be retained even if charged. This is because the non-selection voltage (V _GL ) of the scanning voltage is higher than the pixel voltage (V _SL ) (see FIGS. 10 (c) and (d)), so that the transistor element is conductive even in the non-selection period. This is because it is in a state. Therefore, in order to drive the liquid crystal with an alternating current, a counter electrode must be separately provided, and the counter voltage must be set to a voltage higher than the non-selection voltage of the scanning voltage (when it has an n-type characteristic).

Therefore, if a transistor having an enhancement type characteristic in which the gate threshold voltage V _TH is sufficiently large is used as in the present invention, even if the non-selection voltage of the scanning voltage is higher than the pixel voltage to some extent. Since the transistor is in a non-conducting state, a negative voltage can be held in the pixel electrode and the liquid crystal can be AC-driven.

As described above, it is possible to obtain an active matrix type liquid crystal display device which has a high aperture ratio and can drive the liquid crystal with an alternating current and has a long service life.

Secondly, there is another action. When another electrode having a different potential approaches the two electrodes that control the alignment of the liquid crystal, the alignment of the liquid crystal is disturbed and an alignment defect region (domain) is generated. Secondly, the potentials of the counter electrode and the scan electrode match in most of the period, and an unnecessary electric field is not applied to the liquid crystal in the region between the counter electrode and the scan electrode, so that alignment failure does not occur. Therefore, the effective aperture ratio is improved without reducing the effective aperture area. Also,
As a result, the DC voltage applied to the region between the signal electrode and the scan electrode is also significantly reduced, and the deterioration of the liquid crystal during that period is also reduced.

As described above, it is possible to obtain an active matrix type liquid crystal display device in which a defective alignment region (domain) does not occur, and the effective aperture ratio can be improved.

[0024]

EXAMPLE A liquid crystal display device of the present invention is a liquid crystal display panel in which a liquid crystal composition is sealed between a glass substrate on which a thin film transistor element or the like is formed and a glass substrate on which a color filter or the like is formed, and electrically It is composed of a driving circuit which is connected and generates a voltage applied to the liquid crystal.

The embodiments of the present invention will be described more specifically below.

[Embodiment 1] As the substrate, two transparent glass substrates 101 and 201 having a thickness of 1.1 mm and having a polished surface are used. A thin film transistor is formed over one of these substrates 101. 1 to 4 show the structure of the thin film transistor and various electrodes formed in this embodiment.
2 is a plan view of a pixel, FIG. 1 is a sectional view taken along the line AA ′ in FIG. 2, FIG. 3 is a sectional view taken along the line BB ′ in FIG. 2, and FIG. 4 is a sectional view taken along the line CC ′ in FIG. A sectional view taken along the line is shown.

As shown in FIG. 1, in this embodiment, the electric field E between the pixel electrode 104 and the counter electrode 105 controls the alignment of the liquid crystal molecules 301 of the liquid crystal layer 300, and the pixel electrode 1
04, the brightness of the light incident between the counter electrode 105,
Modulate and emit. As shown in FIG. 2, one pixel includes a scanning electrode 102, a signal electrode 103, a pixel electrode 104, an electrode group of a counter electrode 105, a thin film transistor element 150,
It is composed of an auxiliary capacitance element 160. As shown in FIG. 3, the thin film transistor element 150 includes a pixel electrode 104 (source electrode), a signal electrode 103 (drain electrode), and a scanning electrode 10.
2 (gate electrode) and a semiconductor layer 106 made of amorphous silicon. Thin film transistor element 1
50 is a staggered structure in this embodiment. Auxiliary capacity 16
0 has a structure in which the gate insulating film 108 is sandwiched between the pixel electrode 104 and the scan electrode 102 in the preceding row as shown in FIG.

In this embodiment, the scanning electrode 102 and the counter electrode 105, the signal electrode 103 and the pixel electrode 104 are formed on the same metal layer. Further, in order to make ohmic contact between the amorphous silicon 106 and the signal electrode 103 and the pixel electrode 104, an ohmic contact layer 107 is formed between them by phosphorus-doped n + -type amorphous silicon. Further, the electrode widths of the signal electrode 103, the pixel electrode 104, and the counter electrode 105 are each 10
μm, 6 μm, 6 μm, pixel electrode 104 and signal electrode 10
3 is set to 5 μm, and the pixel electrode 104 and the counter electrode 10 are
When the gap portion 5 is divided into four, the electrode gap d _SG between the pixel electrode 104 and the counter electrode 105 is set to 15 μm. Here, in this embodiment, as shown in FIG.
The counter electrode 105 is connected to the scan electrode 102 in the preceding row, and the scan electrode 102 also serves as the counter electrode wiring. As a result, the region used for the counter electrode wiring can be used as the opening, and the aperture ratio is greatly improved.

On the other substrate 201, in order to improve the contrast, the pixel electrode 104 and the counter electrode 1 are formed.
A low-conductivity light-shielding layer (black matrix) 202 is formed in the gaps other than the areas 05, and three colors of R (red), G (green), and B (blue) for color display are formed on the light-shielding layer 202. The color filter 203 is formed in a stripe shape. A transparent resin 204 that flattens the surface is laminated on the color filter.

An alignment film 12 is formed on the outermost surfaces of these two substrates.
After forming 0 and 220 and performing rubbing treatment, the liquid crystal composition layer 300 is sealed between the substrates, and the liquid crystal composition layer 300 is sealed between the two polarizing plates 13.
A liquid crystal display panel is formed by sandwiching 0,230. In this embodiment, polyimide is used as the alignment film. The rubbing directions on the upper and lower interfaces were substantially parallel to each other, and the angle formed with the direction of the applied electric field was 85 degrees (φ _LC1 = φ _LC2 = 85 °). The liquid crystal composition layer 300 has a positive dielectric anisotropy Δε and a value of 7.3 (1 KHz), and has a refractive index anisotropy Δ.
A nematic liquid crystal composition having n of 0.073 (589 nm, 20 ° C.) was used. The gap d between the substrates is 4.1 when the spherical polymer beads are dispersed and sandwiched between the substrates and the liquid crystal is sealed.
μm. Nitto Denko G1220DU is used as the polarizing plate, and the polarization transmission axis of one polarizing plate is slightly smaller than the rubbing direction, that is, φ _P1 = 85 ° (that is, φ _LC1 = φ _P1 ).
And the other was orthogonal to it, that is, φ _P2 = −5 °. (The relationship between the electric field direction, the rubbing direction, and the polarization transmission axis is shown in FIG. 36.) With the above configuration, when a voltage is applied between the pixel electrode 104 and the counter electrode 105, a dark voltage as shown in FIG. We obtained normally closed characteristics in which a bright state is maintained at high voltage. In this embodiment, the contrast ratio is 100: 1,
The voltage V _OFF = 2.6V for obtaining the minimum transmittance and the voltage V _ON = 5.5V for obtaining the maximum transmittance are set.

Here, in this embodiment, in order to make the characteristics of the thin film transistor completely enhanced, the following constitution was adopted. Al was used for the gate electrode (scan electrode 102) of the thin film transistor, and a silicon nitride film was used for the gate insulating film 108. The thickness of the silicon nitride film is 350
and the film thickness of the amorphous silicon 106 is 15 n.
m. In the present embodiment, the film thickness of the amorphous silicon 106 is reduced to obtain a complete enhancement type characteristic. Since it is extremely thin at 15 nm, when the channel is etched, the amorphous silicon 106
The etching stopper 109 is provided so as not to disappear. With this configuration, the drain current I _D is shown in 501 of FIG. 6 (a) - to obtain a gate voltage V _G characteristics. The gate threshold voltage V _TH of this thin film transistor is shown in FIG.
It can be seen from (b) that it is 9.3V.

Although there are various parameters for controlling the gate threshold voltage V _TH , in the present embodiment, the film thickness of the amorphous silicon is reduced to be shifted to the high voltage side to obtain a perfect enhancement type characteristic. did. Further, in the thin film transistor element of this embodiment, the inclination of the subthreshold region _{s = dV G / dlog (I} D) is 0.9, maintaining the following non-conducting state drain current I _D = 1 × 10 ^-13 A The maximum value of the gate voltage V _{G that} can be achieved is 5.7V. In the transistor element of this embodiment, the maximum negative voltage −V _ON applied to the liquid crystal is applicable up to 5.7V,
As described above, in the structure of this embodiment, the voltage V _ON applied to the liquid crystal layer to bring the liquid crystal layer into the bright state is 5.5 V, so that the maximum negative voltage (- 5.
5 V) can be sufficiently retained in the pixel electrode during the non-selection period. Although the slope s of the subthreshold region changes depending on the transistor characteristics, the gate threshold voltage V
The maximum value of the gate voltage V _{G that} can maintain the non-conduction state in which _TH (9.3 V) and the drain current are 1 × 10 ^-13 A or less (5.7)
V) is defined as a margin voltage V _M (3.6 V: V _M = 4 s), the condition under which the negative voltage can be sufficiently held is V _TH > | V _ON | + V _M (9 .1V).

The gate threshold voltage V _TH is as shown in FIG.
In the range of _{V TH <V G <V D} + V TH (a), the square root √I _D of the drain current is plotted against the gate voltage V _G, when linear approximation, and the straight line and the gate voltage V _G axis Is defined as the gate voltage V _{G at} the intersection.

Next, the driving method of this embodiment will be described. FIG. 7 shows an equivalent circuit of one pixel of the liquid crystal display panel of this embodiment, and FIG. 8 shows the system configuration of this embodiment. In the present embodiment, the controller 401 receives an image signal from the host, converts it into a control signal and display data for the thin film transistor type liquid crystal display device, and the liquid crystal drive power supply circuit 402 supplies the control signal and display data. The vertical scanning circuit 403 and the video signal driving circuit 404 select the power supply voltage, and the scanning voltage,
A signal voltage is generated and supplied to the liquid crystal display panel 400.

FIG. 9 shows the drive waveforms of this embodiment. Figure 9
7A shows the scan voltage V _G applied to the scan electrode 102 in FIG. 7, and FIG. 9B shows the signal voltage V _D applied to the signal electrode 103 in FIG. Further, FIG. 9C shows the pixel voltage V _S (source voltage) at that time, and FIG. 9D shows the voltage applied to the liquid crystal layer. The scanning voltage V _G is composed of a selection voltage and a non-selection voltage, and has a pulse width of 3
The period was set to 4.5 μs, the repetition period was 16.6 ms (60 Hz), the selection voltage V _{GH was} 22 V, and the non-selection voltage V _{GL was} 0 V. Further, as the voltage (opposite voltage) applied to the scan electrode 102 in the preceding row, a voltage waveform in which the scan voltage V _G in FIG. 9A is out of phase by one scan period is applied. In this case, most of the period is the non-selection voltage.

Since the maximum voltage applied to the liquid crystal is 5.5 V, the signal voltage V _D is applied up to ± 5.5 V according to the display gradation centering on the center voltage V _DC . The center voltage V _DC of the signal voltage V _D is the variation Δ of the pixel voltage V _S that occurs when the thin film transistor changes from the ON state to the OFF state.
The value of V _S is set higher than the non-selection voltage V _GL of the scanning voltage, and the liquid crystal drive voltage V _LC (the voltage between the pixel electrode 104 and the scanning electrode 102 (counter electrode 105) in the preceding row: = V _S −V _GL )
Is set to be substantially (effectively) symmetrical to the positive and negative sides.
As a result of observing the pixel voltage, V _DC = 2V was set. The minimum voltage V _SL of the pixel voltage is −5.5 V, the gate voltage V _{GS of the} thin film transistor is 5.5 V, and the drain current I _D = 7 × 10 ⁻¹⁴ A, so that the pixel voltage can be sufficiently held. it can. In addition, the charging voltage V _DH on the positive side of the pixel voltage is 7.5 V, and the selection voltage V _GH of the scanning voltage is 22.
Since it is V, the gate voltage V _GS is 14.5 V, and the drain current I _D = 4 × 10 ⁻⁷ A, so that it is fully turned on and the charging operation can be performed. The ratio of on-current / off-current is about 7
There are digits, and it can be said that the thin film transistor performs sufficient switching operation under the above conditions.

In this embodiment, in the display system in which an electric field parallel to the surface of the substrate having a wide viewing angle and a low load is applied to operate the liquid crystal, a voltage is applied to the counter electrode by the scanning electrode. Since it is not necessary to form a wiring for supplying a voltage and that portion can be used for the opening, the aperture ratio is significantly improved. Further, as compared with the case where the counter electrode wiring is formed, the number of wirings is significantly reduced and the number of wiring crossings is also reduced to 1/2, so that the yield is also significantly improved.

Particularly, in the present invention, V _TH is 9.3 V and | V.
_By setting _ON | + V _M = 9.1 V or more, the negative voltage can be charged and held with the non-selection voltage of the scanning voltage as a reference, and the liquid crystal can be AC-driven. Therefore, the deterioration of the liquid crystal can be suppressed and the service life becomes long. In addition, residual charges accumulated in the protective film and the like can be suppressed, and high-quality display in which an afterimage phenomenon does not occur can be obtained. Further, better, in this embodiment, an electric field exactly the same as the region between the pixel electrode 104 and the counter electrode 105 is applied to the region between the scanning electrode 102 and the pixel electrode 104. This is because the scanning voltage and the counter voltage match in most of the period (non-selection period), and the non-selection voltage of the scanning voltage is used as the counter voltage. For this reason, an alignment failure region due to application of an unnecessary electric field to the region between the scan electrode 102 and the pixel electrode 104 is eliminated, and the effective opening region is expanded.
Therefore, it becomes unnecessary to cover the light shielding film 202 with the misalignment region, and as a result, the boundary of the light shielding film 202 can be further widened and the aperture ratio can be improved.

Comparative Example A thin film transistor element having the characteristics shown by 502 in FIG. 6 was used in the structure of this example and was driven. This gate threshold voltage V _TH is 2.2V. As a result, the pixel electrode voltage V _S (source voltage) is shown in FIG.
It became like (c). Since V _TH is lower than | V _ON |, when a negative voltage is applied to the liquid crystal with reference to the non-selection voltage of the scanning voltage, the thin film transistor element cannot be held because the thin film transistor element is in a conductive state and the liquid crystal is charged. The applied voltage has leaked. Therefore, a DC voltage is applied to the liquid crystal, an afterimage is remarkably generated, and the liquid crystal is deteriorated in a short time.

Although the counter electrode is connected to the scanning electrode in the preceding row in the present embodiment described above, it may be provided from the scanning wiring in the succeeding row. Further, in the present embodiment, the liquid crystal having the positive dielectric anisotropy Δε is used, but the liquid crystal having the negative dielectric anisotropy Δε can be similarly configured. Further, in the present embodiment, the thin film transistor is formed by the inverted stagger structure, but the cross-sectional structure of the transistor is the positive stagger structure,
A coplanar structure may be used without any particular limitation.

[Embodiment 2] The structure of this embodiment is the same as that of the embodiment 1 except for the following requirements.

The driving method of this embodiment is different from that of the first embodiment. The drive waveforms of this embodiment are shown in the figure. The scan voltage V _G ′ of the scan electrode of the preceding row is shown in FIG. 11A, the scan voltage V _G of the scan electrode of the own row is shown in FIG. 11B, and the signal voltage V _D is shown in FIG.
11C shows the pixel voltage V _S and FIG. 11E shows the voltage waveform applied to the liquid crystal layer. In the present embodiment, as shown in FIG. 11, two types of voltages V _GL1 and V _GL2 are used as the non-selection voltage of the scanning voltage, which alternately change for each frame and further use different voltage waveforms for each row. . In addition, the difference (V _GL1 −V _GL2 ) between the two types of non-selected voltage values is
_ON + V _OFF ) / 2, and the pixel voltage was set within the range of (V _ON -V _OFF ) / 2 centering on each non-selection voltage. As a result, the maximum negative voltage of the gate voltage V _GS during the non-selection period is − (V _ON −V _OFF ) / 2, and therefore the gate threshold voltage V of the transistor is
_TH is _{(| V ON | - | V} OFF |) / 2 + be configured to exceed the V _M, the negative maximum voltage of (-V _ON) can be held in the pixel electrode. A s = 0.9 Similarly the inclination of the subthreshold region is that of Example 1, when V _M = 3.6V, or a gate threshold voltage V _TH> 4.1V. Therefore, from the conditions of Example 1 (V _TH > 9.1V), 5.0
The condition could be relaxed only by V.

As a result, the conditions for forming the thin film transistor were alleviated, and it became easier to obtain a thin film transistor that fulfills the above conditions. Furthermore, the maximum amplitude of the signal voltage V _DH −V
_DL is, from 2V _ON = 11V in Example 1 (3V _ON -
V _OFF ) /2=7.0V, the circuit scale of the LSI (signal driver) that drives the signal electrodes can be reduced, and the power consumption can be reduced to about 40% of that of the first embodiment. Further, since the polarity applied to the liquid crystal is necessarily inverted for each line, even if a small amount of direct current component is generated, the flicker caused by it is canceled for each line, and the image quality is improved.

[Third Embodiment] In the first embodiment, a method of thinning a semiconductor layer is used as a method of increasing the threshold value of the thin film transistor. However, in this method, the threshold value strongly depends on the film thickness of the semiconductor layer and the film forming conditions. Therefore, a subtle difference in the film thickness of the semiconductor layer causes the threshold value to fluctuate greatly, resulting in variation in the threshold value for each thin film transistor. In view of this, the present embodiment provides a new thin film transistor that can control the threshold value and reduce variations in the threshold value.

The configuration of this embodiment is the same as that of the second embodiment except for the following requirements. In this embodiment, a thin film transistor which has a back electrode for controlling the potential of the amorphous silicon layer and whose threshold value is controlled is used.

FIG. 12 shows a schematic sectional view of the thin film transistor of this embodiment. The thin film transistor used in this example is characterized in that the back electrode 1 is provided between the protective film 110 and the alignment film 120.
40. In this embodiment, the back electrode 170
Was used as Cr. Further, in this embodiment, the back electrode 14
0 is formed on the scanning electrode as shown in FIG. 13 and is connected to the back voltage control circuit 405 shown in FIG.

FIG. 15 shows the change in the threshold voltage of the thin film transistor used in this example due to the back surface voltage. The numbers in the figure indicate the film thickness of the amorphous silicon layer 106,
In this embodiment, the thickness is 800 nm. As is clear from FIG. 15, by controlling the voltage of the back electrode, the threshold value of the thin film transistor can be controlled. In this embodiment, the gate threshold voltage V _TH > 4.1V because the structure is the same as that of the second embodiment. Therefore, -30V was input as the back voltage. Further, since the threshold value V _TH is controlled by the back surface voltage, compared with the case of the first embodiment,
It was possible to reduce the variation in the threshold value.

As described above, in this embodiment, the back electrode is newly provided and the threshold value of the thin film transistor is controlled, so that the variation in the threshold value can be reduced in addition to the effect of the first embodiment. [Embodiment 4] This embodiment is the same as Embodiment 3 except for the following requirements.

FIG. 16 shows a schematic sectional structure of the thin film transistor used in this example. In this embodiment, the thickness of the semiconductor layer is 100 nm. In the examples, in order to reduce the thickness of the semiconductor layer, an etching stopper for preventing the division of the channel during channel etching was provided.

In FIG. 15, the film thickness of the semiconductor layer 106 is set to 100.
The change in the threshold value due to the back surface potential is shown in the case of nm. As compared with the case where the film thickness shown in the figure is 800 nm (Example 3), the value of the back surface voltage required to obtain the same threshold value can be reduced from -30V to -10V. This allows
The power consumption of the back voltage control circuit 405 could be reduced.

As described above, in the present embodiment, in addition to the effect of the third embodiment, it is possible to reduce the generated voltage value of the back voltage control circuit and reduce the power consumption.

[Embodiment 5] This embodiment is the same as Embodiment 3 except for the following requirements.

FIG. 17 is a schematic sectional view of the thin film transistor of this embodiment. In this embodiment, the protective film has a two-layer structure,
The back electrode 140 is formed between the first layer protective film 111 and the second layer protective film 112.

In this embodiment, the thickness of the first protective film 111 is set to about 300 nm and the distance between the semiconductor layer 106 and the back electrode 140 is shortened to make the threshold voltage of the thin film transistor more sensitive to the back voltage. As a result, the back voltage can be further reduced and the power consumption can be reduced.

As described above, in the present embodiment, in addition to the effect of the third embodiment, it is possible to reduce the generated voltage value of the back voltage control circuit and reduce the power consumption.

[Embodiment 6] This embodiment is the same as Embodiment 3 except for the following requirements.

FIG. 18 shows a schematic sectional view of the thin film transistor of this embodiment. In this embodiment, the thin film transistor has a positive stagger structure, and the back electrode 140 is formed between the glass substrate 101 and the insulating film 114 formed thereon.

In this embodiment, since the thin film transistor has the positive stagger structure, the semiconductor film 106 can be easily thinned without using an etching stopper, and the back electrode is the lowermost layer, so that the liquid crystal layer can be formed by the back voltage. The effect of the electric field was reduced. As a result, the liquid crystal alignment failure due to the back voltage can be reduced.

As described above, in the present embodiment, in addition to the effects of the third and fourth embodiments, the liquid crystal alignment defect due to the back voltage can be reduced.

[Embodiment 7] This embodiment is the same as Embodiment 3 except for the following requirements.

FIG. 19 shows a schematic sectional view of the thin film transistor of this embodiment. A schematic plan view is shown in FIG. In order to prevent fluctuations in the characteristics of thin film transistors due to photocurrent,
In the thin film transistor, at least the region of the amorphous silicon film in the channel portion needs to be shielded from light. Further, in order to secure the light shielding more, it is desirable that the entire area of the amorphous silicon film in the thin film transistor portion is shielded. However, in the pigment BM of Example 1,
The light blocking ratio was insufficient to suppress the photocurrent of the TFT. Therefore, in this embodiment, in order to further increase the light blocking rate,
The thin film transistor was shielded from light by using the back electrode 140 together with the light shielding film 202 made of pigment used in Example 1. However, it is essential that the back electrode 140 has a light-shielding property similar to that of metal. In the present embodiment, the back electrode 140 also serves as a light-shielding film to increase the light-shielding rate of the TFT portion.
It was possible to further reduce the characteristic variation of the TFT due to the photocurrent.

As described above, in the present embodiment, in addition to the effect of the third embodiment, the characteristic variation of the TFT can be further reduced.

[Embodiment 8] This embodiment is the same as Embodiment 3 except for the following requirements.

In this embodiment, the threshold voltage of the TFT is controlled by controlling the potential of the back electrode by avalanche injection.

In this embodiment, the scanning electrode 102 is connected to the ground, a large negative voltage is applied to the signal electrode 103,
The value of the electric field applied to the insulating film between the signal electrode 103 and the back electrode 140 was made higher than the value at which avalanche injection of electrons occurred, and electrons were injected into the back electrode 140 by avalanche injection. As a result, the back electrode 140 is negatively charged, and the threshold value of the thin film transistor shifts to the positive side according to the amount of electrons injected per unit area. Therefore, the threshold value of the thin film transistor can be controlled by controlling the amount of injected electrons or holes. Whether or not the avalanche injection occurs is determined not by the potential difference between the electrodes but by the strength of the electric field applied to the insulator separating the electrodes. Therefore, the signal electrode 10
It is desirable that the film thickness of the insulating film between the third electrode 3 and the back electrode 140 is sufficiently thin within a range where the insulating property can be secured. Further, by appropriately setting the potential difference between the signal electrode and the scanning electrode,
It becomes possible to prevent injection of electrons or holes into the gate insulating film and to inject a required amount of electrons or holes into the back electrode. Further, since the electric field applied to the insulating film when the panel is used is smaller than the electric field applied to the insulating film at the time of injection, the electrons or holes once injected are stable for a long period of time.

By using the thin film transistor of this embodiment, the back electrode does not have to be connected to an external circuit, and the back voltage control circuit 405 becomes unnecessary.

As described above, in this embodiment, in addition to the effect of the third embodiment, the back voltage control circuit can be omitted and the circuit scale of the external circuit can be reduced.

In the third to sixth embodiments, the back electrode wiring may be formed on the scanning electrode wiring via the insulating film or may be formed on the signal electrode wiring via the insulating film. Good. Alternatively, it may be formed on both the scan electrode wiring and the signal electrode wiring via an insulating film, or may not be formed on one or both of the scan electrode wiring and the signal electrode wiring, but at a completely different position. You may. Also, in the case of the positive stagger type, the relative order in which each electrode is formed on the substrate is the reverse of that in the reverse stagger type, and the relative positional relationship between each electrode wiring and the back electrode wiring across the insulating film is opposite. Inverted from the stagger type case, but also in those cases, all of Examples 3 to 5
Included in. Further, in the case of the planar type, the relative positional relationship between the back electrode wiring and each electrode wiring can be either one of the above-mentioned inverted stagger type and the positive stagger type, or the relative positional relationship can be the same. Included in 3 to 6.

[Embodiment 9] This embodiment is the same as Embodiment 8 except for the following requirements.

In this embodiment, the back electrodes 140 are independent as shown in FIG. Therefore, the area of intersection of the back electrode 140 with the scanning electrode 102 and the signal electrode 103 is reduced, and the back electrode 140 and the scanning electrode 102 are reduced.
The probability of a short circuit between the back electrode 140 and the signal electrode 103 is reduced, and the defective rate is reduced. Further, even if there is a short circuit, the effect is limited to only the thin film transistor in which the short circuit occurs, does not affect the entire panel, and further reduces the defective rate.

As described above, in this embodiment, in addition to the effects of the fifth embodiment, it is possible to obtain a liquid crystal display panel with further improved yield.

Although amorphous silicon is used for the semiconductor layer 106 in these examples, the type thereof is not particularly limited. Further, in these examples, the scanning electrode, the signal electrode, the pixel electrode, the back electrode, and the counter electrode were made of either Cr or Cr / Al two-layer film, but other metals, alloys, semiconductors, The type such as a transparent conductive film is not limited.
However, only when the back electrode also serves as a light-shielding film, the material used for the back electrode is required to have a light-shielding property.

[Embodiment 10] This embodiment is the same as Embodiments 1 and 2 except for the following requirements.

The equation showing the threshold value of the thin film transistor is
It is given by the following formula.

[0075]

## EQU1 ## V _t = φ _ms −Q _f / C _ox + 2 × φ _f −Q _b / C _ox Equation 1 V _t : Threshold voltage φ _ms : Difference in work relationship between metal and semiconductor via gate insulating film Q _f : charge density of gate insulating film φ _f : band bending due to electric field Q _b : charge density of semiconductor layer C _ox : capacitance of gate insulating film As shown in Equation 1, the amount of positive and negative charges in the semiconductor layer is controlled. By doing so, the gate threshold voltage of the thin film transistor can be controlled. In addition, Q _{b in} Expression 1 is −qN _a ,
Alternatively, it is proportional to qN _d . Here, q is the charge amount of electrons, N _a is the density of acceptors in the semiconductor layer, and N _d is the density of donors in the semiconductor. Therefore, the gate threshold voltage of the thin film transistor can be controlled by controlling the amount of acceptor or donor in the semiconductor.

In this example, the amorphous silicon of the semiconductor layer 106 was doped with B (boron). The threshold value of the thin film transistor could be controlled by introducing the acceptor into the semiconductor layer 106. FIG. 22 shows changes in the threshold voltage depending on the B doping amount of the thin film transistor of this example. In the present embodiment, by doping 100 ppm of B, the gate threshold voltage V _{TH of the} second embodiment is increased.
> 4.1V was satisfied.

The threshold control according to this embodiment is the same as that of the third embodiment.
As described above, it is not necessary to form the back electrode, the forming process is simplified, and the productivity is improved. Further, as shown in FIG. 22, when B is doped by 2 ppm or more, the threshold value becomes insensitive to the doping amount, so that the variation in the gate threshold voltage can be suppressed.

As described above, in this embodiment, by using the semiconductor in which the acceptor is introduced into the semiconductor layer of the thin film transistor, in addition to the effect of the first embodiment, the variation of the gate threshold voltage is suppressed and the productivity is improved. .

[Embodiment 11] This embodiment is the same as Embodiment 10 except for the following requirements.

FIG. 23 shows a schematic sectional view of the thin film transistor of this embodiment. In this embodiment, a two-layer structure of a semiconductor layer 150 doped with a semiconductor layer of a thin film transistor and an intrinsic semiconductor layer 151 is used.

When an acceptor is introduced into the semiconductor layer in order to increase the gate threshold voltage, the conduction by holes in the non-channel region of the semiconductor increases as the amount of the acceptor increases. In this case, the current blocking capability of the thin film transistor is reduced, that is, the off characteristic is degraded, which in turn degrades the voltage holding characteristic of the liquid crystal panel.

Therefore, in this embodiment, the semiconductor layer has a two-layer structure of the doped semiconductor layer 150 on the channel side and the intrinsic semiconductor layer 151 on the non-channel side. This allows
It is possible to prevent conduction from being generated by holes in the non-channel region of the semiconductor, and the off-characteristics of the thin film transistor are improved as compared with the case of Example 8.

As described above, in the present embodiment, in addition to the effect of the tenth embodiment, the deterioration of the off characteristic of the thin film transistor is suppressed, the voltage holding characteristic is improved, and the display quality is improved.

[Examples 12 to 13] This example is the same as Examples 1 and 2 except for the following requirements.

In the twelfth and thirteenth embodiments, SiON and SiO are used as the material of the gate insulating film 108 of the amorphous silicon thin film transistor, respectively, so that the gate threshold voltage is controlled and the yield of the thin film transistor is improved. did.

Table 1 shows the gate threshold voltages obtained for the respective gate insulating film materials of the thin film transistors manufactured in Examples 10 and 11.

[0087]

[Table 1]

In this example, the conditions of Example 2 could not be satisfied, but they could be satisfied by using a liquid crystal operating at a lower voltage than Example 2 or by reducing the inter-electrode gap. it can. Therefore, by combining the semiconductor layer 106 and the gate insulating film 108, the gate threshold voltage required by the combination can be satisfied.
Further, since the gate threshold voltage is determined by the combination of the semiconductor layer 106 and the gate insulating film 108, the variation is small.

In this embodiment, the first embodiment is the same as the tenth embodiment.
In addition to the above effect, the variation in the gate threshold voltage is suppressed and the productivity is improved.

[Embodiment 14] This embodiment is the same as Embodiments 12 and 13 except for the following requirements. FIG. 24 shows a schematic view of the cross-sectional structure of the thin film transistor of this example. The gate insulating film had a two-layer structure using SiON or SiO160 on the gate electrode side and SiN161 on the channel side.

In this embodiment, the semiconductor layer is formed by continuously forming the SiN 161 which is the gate insulating film on the channel side and the amorphous silicon 106 by plasma CVD.
The interface between 106 and the gate insulating film 161 can be prevented from being contaminated, and the mobility is improved.

As described above, in this embodiment, the gate insulating film is S
In addition to the effects of the tenth and eleventh embodiments, a two-layer structure of iN and SiON or SiO
Mobility is improved.

[Embodiment 15] This embodiment is the same as Embodiment 1 and Embodiment 2 except for the following requirements.

FIG. 25 shows a schematic view of the cross-sectional structure of the thin film transistor of this example. In the present embodiment, P (phosphorus) is ion-implanted into the protective film 110, and the semiconductor layer 1 is negatively charged by P.
The gate threshold voltage of the thin film transistor element was shifted in the positive direction by making the back surface potential of 06 negative. The region 190 for ion implantation was controlled between the semiconductor layer 106 and 300 nm to 1000 nm.

As described above, the same effect as that of the third embodiment can be obtained.

[Embodiment 16] This embodiment is the same as Embodiments 1 and 2 except for the following requirements.

FIG. 26 shows a schematic view of the cross-sectional structure of the thin film transistor of this example. In this embodiment, the gate insulating film 1
B (boron) is ion-implanted at the interface with the scan electrode 102 of No. 08, and the positive charge due to B cancels a certain amount of the negative charge induced when the scan voltage is applied to the positive electrode. The threshold voltage was shifted in the positive direction.

As described above, the same effect as in Example 3 could be obtained.

[Embodiment 17] This embodiment is the same as Embodiment 15 except for the following requirements.

FIG. 27 shows a schematic view of the cross-sectional structure of the thin film transistor of this example. In this embodiment, the structure of the thin film transistor element is a positive stagger structure and the insulating substrate 114 is made of P
(Phosphorus) was ion-implanted. As a result, the gate threshold voltage of the thin film transistor element could be shifted in the positive direction as in Example 15.

Further, in this embodiment, the n + amorphous silicon region 192 for making ohmic contact between the signal electrode 103 and the pixel electrode 104 and the semiconductor layer 106 can be formed in the same manner by ion implantation. In this embodiment, after forming the gate insulating film before forming the scanning electrode 102,
P was ion-implanted into the insulating substrate 114. At this time, since metal is used for the signal electrode 103 and the pixel electrode 104, P is blocked at that portion and the signal electrode 1
03 and the pixel electrode 104 and the semiconductor layer 106, a region in which P is injected is formed. As a result, the amorphous silicon in that portion becomes n +, and ohmic contact can be obtained. Therefore, it is not necessary to separately provide a step of forming n + amorphous silicon, and the productivity is improved. Further, it is not necessary to perform etching for separating the n + amorphous silicon into the signal electrode 103 and the pixel electrode 104, and the deterioration of the ON characteristics due to the etching is eliminated.

As described above, the same effect as that of the third embodiment can be obtained, the productivity is improved, and good transistor characteristics can be obtained.

[Embodiment 18] In this embodiment, the gate electrode (scanning electrode 102) of the thin film transistor is offset to the source electrode (signal electrode 103) side or the drain electrode (pixel electrode 104) side. The control of the threshold voltage is realized.

In the thin film transistor, the potential difference between the gate (scan electrode 102) and the source (signal electrode 103) or the drain (pixel electrode 104) exceeds the threshold value, and the channel region becomes conductive. This means that electric charges sufficient to form a channel region were induced at the interface of the semiconductor layer 106 on the contact side. This charge is generated by the electric field applied to the gate insulating film 108.
This is induced in the semiconductor layer 106 at the interface with the gate insulating film 108 so as to cancel out the space charges induced at the interface of the gate insulating film 108. Therefore, in order to change the gate threshold voltage of the thin film transistor in the positive direction, the value of the electric field applied to the gate insulating film 108 is reduced to reduce the amount of space charge induced at the interface of the gate insulating film. Is considered to be effective.

As described above, in the thin film transistor having a structure in which the gate electrode is missing in a part of the channel region, the strength of the electric field applied to the insulating film on the region where the gate electrode does not exist depends on the region where the gate electrode exists. It is considered to be smaller than the electric field strength applied to a certain insulating film. This is because in a thin film transistor having a structure in which the gate electrode is completely offset to either the source electrode side or the drain electrode side and the gate electrode does not exist at all in the channel region, the region of the gate insulating film that is not in contact with the gate electrode Since a sufficient electric field is not applied to at least a part of
It is also clear from the fact that the switching characteristics are not exhibited. Therefore, the potential difference between the gate electrode and the signal electrode or the pixel electrode, which is necessary to induce sufficient charges to form the channel layer in the semiconductor layer in the region without the gate electrode, is In addition, it is considered that the potential difference becomes larger than the potential difference between the gate electrode and the signal electrode or the pixel electrode, which is necessary for inducing sufficient charges to form the channel layer.

Based on the above, a schematic cross-sectional structure diagram and a schematic plan structure diagram of the thin film transistor of this embodiment are respectively shown in FIG.
8 (a) and (b). A feature of the thin film transistor of this embodiment is that it has a structure in which the gate electrode of the thin film transistor is offset to either the source electrode side or the drain electrode side.

In this embodiment, by properly setting the offset of the gate electrode, the gate threshold voltage could be increased in the positive direction without losing the switching characteristics. Further, in this embodiment, the gate threshold voltage is controlled by the shape of the gate electrode. This means that once the photomask is formed, it is not necessary to add a step for controlling the threshold value or use a new gas thereafter. For this reason, in this embodiment, an increase in manufacturing cost due to control of the gate threshold voltage could be suppressed.

As described above, in this embodiment, in addition to the effects of the third embodiment, mass productivity is improved.

[Embodiment 19] This embodiment is the same as Embodiment 18 except for the following requirements.

FIG. 29 shows a schematic cross-sectional structural diagram and a schematic plan structural diagram of the thin film transistor of this example, respectively (a) and
Shown as (b). As shown in FIG. 29, the feature of the thin film transistor of this embodiment is that there are two or more gate electrodes in the channel region, and thus there is at least one region where the gate electrode is missing in the channel region. .

In the thin film transistor having a structure in which the gate electrode is biased to either the source electrode or the drain electrode as shown in Example 18, the threshold value is It depends largely on the relative positional relationship. This means that it is necessary to increase the alignment accuracy in manufacturing each electrode of the thin film transistor, and the time required for the alignment of the photomask increases, which causes a decrease in productivity. In order to avoid this, the structure may be such that the threshold value does not depend on the relative positional relationship of the electrodes. When the structure has two or more gate electrodes in the channel region as shown in FIG. 29, the threshold value is determined by the distance between the gate electrodes, and its accuracy is determined by the etching accuracy of the gate electrodes. Therefore, regarding the alignment accuracy of each electrode,
It suffices that the gap between the gate electrodes is in the channel region, and the accuracy of the eighteenth embodiment is not required. Therefore, the strict alignment as in the eighteenth embodiment is unnecessary,
Productivity improved.

As described above, in this embodiment, in addition to the effects of the eighteenth embodiment, the productivity is further improved.

If the number of gate electrodes in the channel region is two or more, regardless of the shape, they are included in the category of this embodiment.

Further, by combining at least two or a plurality of the above-mentioned Embodiments 3 to 14, it is possible to control the threshold voltage in a wider range than when each of the embodiments is used alone. Realization is all within the scope of the present invention.

[Embodiment 20] The construction of this embodiment is the same as that of Embodiment 1 except for the following requirements. In this embodiment, both a thin film transistor having n-type characteristics and a thin film transistor element having p-type characteristics are used. FIG. 30 shows an equivalent circuit of 4 × 4 pixels of the present embodiment, and FIG. 31 shows respective characteristics of the transistor element used in the present embodiment. In this embodiment, a thin film transistor element 601 having n-type characteristics and a thin film transistor element 60 having p-type characteristics are provided for each row.
2 were alternately configured.

FIG. 32 shows the drive waveforms of this embodiment. In this embodiment, the scanning voltage waveform for controlling the n-type thin film transistor element 601 and the p-type thin film transistor element 60 for each row.
A scanning voltage waveform for controlling 2 was applied, and the non-selection voltages V _GLP and V _GLN of the respective scanning voltages were set to different voltage values. Furthermore, p-type thin film transistor element 602
The scanning voltage non-selection voltage V _GLP is set to a higher scanning voltage non-selection voltage V _GLN of the n-type thin film transistor element 601, so that | V _GLP −V _GLN | ≧ | V _ON | Set. As a result, the counter voltage of the pixel having the n-type thin film transistor element 601 becomes higher than the non-selection voltage of the scanning voltage, and the gate threshold voltage V _TH of the thin film transistor element 601 does not satisfy the conditions of the first embodiment ( When | V _TH | <| V _ON |), the negative voltage can be applied to the liquid crystal and held. On the contrary, the p-type thin film transistor element 60
The counter voltage of the pixel having 2 becomes lower than the non-selection voltage of the scanning voltage.

However, in the p-type thin film transistor element and the n-type thin film transistor element, the relative polarities of the operating voltages are reversed, and the counter voltage becomes lower than the off voltage of the scanning voltage. This is equivalent to the counter voltage becoming higher than the non-selection voltage of the scanning voltage in the pixel. (That is, the condition for applying and holding the voltage of the positive electrode to the liquid crystal is that the n-type thin film transistor element 601
This is equivalent to the condition of applying and holding the voltage of the negative electrode of the pixel having the liquid crystal to the liquid crystal. ) All thin film transistor elements are n-type, p
In the case of having only one of the characteristics of the types, it is possible to relax the condition of the gate threshold voltage V _TH by making the OFF voltage of the scanning voltage different for each row, but the number of rows is increased. Then, the power supply voltage of the scanning voltage, the number of voltage levels of the scanning voltage, and the required withstand voltage level of the vertical scanning circuit significantly increase, which is not practical. However, in the present embodiment, the p-type and the n-type are alternately repeated, so that the off-voltage shift can be canceled row by row, and a pixel group having a p-type thin film transistor element and an n-type thin film transistor element can be offset. It is possible to set the scanning voltage of each of the pixel groups having the same in all rows in the same manner. Therefore, even if the number of rows is increased, the power supply voltage of the scanning voltage and the withstand voltage level required for the vertical scanning circuit are not increased, and the number of voltage levels of the scanning voltage may be four levels.

As described above, in this embodiment, the gate threshold voltage V _TH of the thin film transistor element capable of AC driving the liquid crystal is │V _TH │ <│V _ON │, that is, a transistor having depletion type characteristics is used. However, the voltage of the negative electrode can be applied to and retained in the liquid crystal, and a thin film transistor element having an arbitrary gate threshold voltage V _TH can be used. [Embodiment 21] The construction of this embodiment is the same as the following except for the following requirements.
This is equivalent to Example 20.

In this embodiment, the video signal circuit and the vertical scanning circuit are built in the liquid crystal panel. FIG. 33 shows its configuration. Since p-type and n-type thin film transistors are formed in the liquid crystal panel, a C-MOS can be easily formed,
A low power consumption circuit can be incorporated. As a result, the connection with the peripheral circuit was facilitated, and the reduction in yield due to the connection failure could be greatly improved. Moreover, since the peripheral circuits are built in, the frame is eliminated, and a more compact structure can be achieved.

As described above, in this embodiment, in addition to the effects of the twentieth embodiment, mass productivity is further improved.

[Embodiment 22] The construction of this embodiment is the same as that of the embodiment 2 except for the following requirements.

In this embodiment, the driving method of the second embodiment is further developed to reduce the maximum operating voltage of the LSI (signal driver) for driving the signal electrode, thereby realizing the reduction of the circuit scale and the reduction of the voltage.

The drive waveforms of this embodiment are shown in the figure. The scanning voltage V _G ′ of the scanning electrode of the preceding row is shown in FIG. 34 (a), the scanning voltage V _G of the scanning electrode of its own row is shown in FIG. 34 (b), and the signal voltage V _D
34C, the pixel voltage V _S is shown in FIG. 34D, and the voltage applied to the liquid crystal layer is shown in FIG. 34E. In the present embodiment, as in the second embodiment, two kinds of voltages V _GL1 and V _GL2 are used as the non-selection voltage of the scanning voltage, and they alternately change for each frame, and a different voltage waveform is used for each row. The difference (V _GL1 −V _GL2 ) between the two non-selected voltage values is (V _ON + V _OFF ).
It was set to be equal to / 2. Further, a rectangular wave (AC has a period of 2 scanning periods and a duty of 50%) that is _converted into an alternating current for each scanning period is superimposed on the two types of non-selection voltages V _GLH and V _GLL, and the amplitude of the superimposed rectangular wave is (V _ON + V Set to _OFF ) / 2.
By using this superposed rectangular wave and changing the counter voltage, the difference between the pixel voltage and the counter voltage, that is, the voltage applied to the liquid crystal is increased, and the positive and negative operating ranges of the signal voltage are matched. You can As a result, the maximum amplitude of the signal voltage applied to the signal electrode is V _ON -V
_OFF = 2.9V, which is (3V _ON- V _OFF ) / 2 of the second embodiment.
It was possible to reduce by 4.1V as compared with = 7.0V.
As a result, the withstand voltage of the signal driver is 5.0 V or 3.
An LSI manufactured by a 3V general-purpose process can be used, the cost can be significantly reduced, and the power consumption can be reduced to about 10% of that of the first embodiment.

[Embodiment 23] The construction of this embodiment is the same as that of Embodiment 1 except for the following requirements.

FIG. 35 shows a planar structure of the thin film transistor and various electrodes of this embodiment. In this embodiment, the counter electrode 1
05 is configured to be adjacent to the signal electrode, and the signal electrode 10
The counter electrode 105 is arranged between the pixel electrode 104 and the pixel electrode 104.

In this embodiment, since the counter electrode 105 is arranged between the signal electrode 103 and the pixel electrode 104, most of the lines of electric force from the signal electrode 103 terminate in the counter electrode 105. Since the scanning electrode 102 is given a potential from the vertical scanning circuit 403 so as to be constant at the non-selection voltage in most of the period except the period for charging its own row, it absorbs the voltage fluctuation of the signal electrode 103 and outputs the signal. The influence of the voltage fluctuation of the electrode on the voltage of the pixel electrode is drastically reduced. Therefore, even if the voltage of the signal electrode fluctuates according to the video signal, the voltage of the pixel electrode does not change, so that crosstalk between the signal electrode and the pixel electrode, particularly streak-shaped image quality defects (vertical smear) that occur in the longitudinal direction of the signal electrode. ) Disappears.

As described above, in this embodiment, the same effect as that of the first embodiment can be obtained, and further, the active matrix type liquid crystal display device of high image quality without crosstalk can be obtained.

Furthermore, in this embodiment, the arrangement of the electrodes is different from that of the first embodiment, and therefore the effect regarding the alignment defect is different. In this embodiment, the counter electrode 105 and the scanning electrode 102 not connected to the counter electrode 105 are close to each other. However, since the counter voltage and the scan voltage are almost the same, the electric field is present in the region between them. Hardly applied. Therefore,
When the normally closed characteristic is used as in the first embodiment, light does not pass through that region, so that it is not necessary to shield that portion. Further, in the area between the pixel electrode 104 and the scanning electrode 102, a voltage is applied according to the pixel voltage similarly to the area between the pixel electrode 104 and the counter electrode 105, and a black video signal voltage is applied to the pixel electrode. When the battery is charged, since black, that is, light is not transmitted, the black is well sunk and the contrast is not lowered even if the region is not shielded. Therefore, the light shielding film may not be provided in that region, the boundary of the light shielding film can be widened, and the opening region can be enlarged.

[0129]

As described in detail above, according to the present invention,
In a display system in which an electric field parallel to the substrate surface is applied to liquid crystal to modulate light, an active matrix type liquid crystal display device having a high aperture ratio can be obtained by reducing the number of wirings and the area of defective alignment. At the same time, an active matrix type liquid crystal display device which can be mass-produced with a high yield can be obtained by reducing the number of wirings. Furthermore, by AC driving, a high image quality active matrix type liquid crystal display device can be obtained in which the service life is long and the afterimage does not decrease.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a pixel portion according to a first embodiment of the present invention (FIG. 2A-A ′ line).

FIG. 2 is a diagram showing a planar configuration of a pixel portion according to the first embodiment.

FIG. 3 is a diagram showing a cross-sectional structure of a pixel portion taken along the line BB ′ of FIG.

FIG. 4 is a diagram showing a cross-sectional structure of a pixel portion taken along the line CC ′ of FIG. 2;

FIG. 5 is a diagram showing electro-optical characteristics of Example 1.

6 shows the electrical characteristics of the transistor element of Example _{1 ((a): I D} -V G characteristics, (b): the gate threshold voltage V _TH).

7 is a diagram showing an equivalent circuit of the liquid crystal panel of Example 1. FIG.

FIG. 8 is a diagram showing a system configuration of the liquid crystal display device of Example 1.

FIG. 9 is a diagram showing drive voltage waveforms according to the first embodiment.

FIG. 10 is a diagram showing a drive voltage waveform of a comparative example.

FIG. 11 is a diagram showing drive voltage waveforms according to the second embodiment.

FIG. 12 is a view showing a schematic cross-sectional structure of a thin film transistor element of Example 3.

FIG. 13 is a diagram showing a planar configuration of a back electrode of Example 3.

FIG. 14 is a diagram showing a system configuration of a liquid crystal display device according to a third embodiment.

FIG. 15 is a diagram showing a relationship between a back surface potential and a threshold value of the thin film transistor element of Example 3.

FIG. 16 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 4.

FIG. 17 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 5.

FIG. 18 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 6.

FIG. 19 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 7.

FIG. 20 is a diagram showing a planar configuration of a back electrode of Example 7.

FIG. 21 is a diagram showing a planar configuration of a back electrode of Example 8.

22 is a diagram showing the relationship between the B doping amount and the threshold value of the thin film transistor element of Example 9. FIG.

FIG. 23 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 10.

FIG. 24 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 14.

FIG. 25 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 15.

FIG. 26 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 16;

FIG. 27 is a diagram showing a schematic cross-sectional structure of a thin film transistor element of Example 17.

28A and 28B are diagrams showing the structure of the thin film transistor element of Example 18 ((a): schematic cross-sectional structure, (b): schematic planar structure).

29A and 29B are diagrams showing the structure of the thin film transistor element of Example 19 ((a): schematic cross-sectional structure, (b): schematic planar structure).

FIG. 30 is a diagram illustrating an equivalent circuit of 4 × 4 pixels according to a twentieth embodiment.

FIG. 31 is a diagram showing electrical characteristics of the transistor element of Example 20.

FIG. 32 is a diagram showing a drive voltage waveform according to the twentieth embodiment.

FIG. 33 is a diagram showing a system configuration of Example 21.

FIG. 34 is a diagram showing a drive voltage waveform according to the twenty-second embodiment.

FIG. 35 is a diagram showing a planar configuration of a pixel section of Example 23.

FIG. 36 is a view showing an angle formed by a molecular long axis orientation direction (rubbing direction) φ _LC on the interface with respect to an electric field direction and a polarizing plate polarization axis direction φ _P.

[Explanation of Codes] 100 ... Lower Substrate, 101, 201 ... Glass Substrate, 10
2 ... Scan electrode, 103 ... Signal electrode, 104 ... Pixel electrode (source electrode of thin film transistor), 105 ... Counter electrode, 106 ... Semiconductor layer, 107 ... Ohmic contact layer, 1
08 ... Gate insulating film, 109 ... Etching stopper, 1
10 ... Protective film, 120, 220 ... Alignment film, 130, 23
0 ... Polarizing plate, 140 ... Back electrode, 150 ... Semiconductor layer, 1
60 ... Auxiliary capacitance, 200 ... Upper substrate, 202 ... Light-shielding film,
203 ... Color filter, 204 ... Flattening film, 300 ...
Liquid crystal composition layer, 301 ... Liquid crystal molecule, 400 ... Liquid crystal display panel, 401 ... Controller, 402 ... Liquid crystal driving power supply circuit, 403 ... Vertical scanning circuit, 404 ... Video signal driving circuit, 405 ... Back voltage control circuit.

Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication H01L 21/336 (72) Inventor Masato Oe 7-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Inside Hitachi Research Laboratory

Claims (27)

[Claims] 1. A pair of substrates, at least one of which is transparent, and a liquid crystal layer in which a liquid crystal composition is sealed between the pair of substrates, wherein one of the pair of substrates has a plurality of scanning electrodes. When,
A plurality of signal electrodes that intersect the plurality of scan electrodes in a matrix, a plurality of semiconductor switching elements formed corresponding to the respective intersections of the plurality of scan electrodes and the plurality of signal electrodes, and the plurality of switching elements. A plurality of pixel electrodes connected to each of the elements and a plurality of counter electrodes connected to each of the plurality of scan electrodes are formed, and each of the plurality of pixel electrodes and the plurality of counter electrodes is
The voltage applied to the corresponding pixel electrode arranged in each region surrounded by the plurality of scanning electrodes and the plurality of signal lines and corresponding to each of the plurality of switching elements is based on the non-scanning voltage of the scanning electrode. An active matrix type liquid crystal display device characterized in that the AC voltage is substantially positive and negative symmetrical. 2. The active matrix type liquid crystal display device according to claim 1, wherein each of the semiconductor switching elements is a thin film transistor element having enhancement type characteristics. 3. The absolute value of the threshold value V _TH of the thin film transistor element according to claim 2, wherein the maximum voltage V applied to the liquid crystal layer is V in order to maximize the light transmittance of the liquid crystal layer.
_An active matrix type liquid crystal display device characterized by exceeding an absolute value of _0N . 4. The absolute value of the threshold value V _TH of the thin film transistor element according to claim 2, wherein a maximum voltage V _ON applied to the liquid crystal layer is set so that the light transmittance of the liquid crystal layer becomes maximum and minimum. And an active matrix type liquid crystal display device characterized by exceeding 1/2 of the difference between the minimum voltage V _OFF . 5. The substrate according to claim 1, wherein the substrate on which the plurality of semiconductor switching elements are formed corresponds to a protective film for protecting these semiconductor switching elements, and the semiconductor switching elements are provided on the protective film. An active matrix type liquid crystal display device having a back electrode formed as described above. 6. The active matrix type liquid crystal display device according to claim 5, wherein the back electrode is arranged along the scanning electrode. 7. The active matrix type liquid crystal display device according to claim 5, wherein the back electrode is formed so as to shield the channel region of the semiconductor switching element from light. 8. The active matrix type liquid crystal display device according to claim 5, wherein the back electrode is a floating electrode. 9. The active matrix type device according to claim 1, wherein the substrate on which the plurality of semiconductor switching elements are formed has a back electrode formed under the semiconductor switching elements via an insulating film. Liquid crystal display device. 10. The active matrix type liquid crystal display device according to claim 9, wherein the back electrode is arranged along the scanning electrode. 11. The active matrix liquid crystal display device according to claim 10, wherein the back electrode is a floating electrode. 12. The substrate according to claim 1, wherein the substrate on which the plurality of semiconductor switching elements are formed has a protective film for protecting these semiconductor switching elements, and impurities are ion-implanted on the protective film. An active matrix liquid crystal display device characterized in that 13. The substrate according to claim 1, wherein the substrate on which the plurality of semiconductor switching elements are formed has an insulating film below these semiconductor switching elements, and impurities are ion-implanted on the insulating film. An active matrix liquid crystal display device characterized by: 14. The semiconductor switching device according to claim 13, further comprising a metallic source electrode connected to the corresponding signal electrode and a metallic drain electrode connected to the corresponding pixel electrode. An active matrix type liquid crystal display device having a positive stagger structure. 15. The semiconductor switching element according to claim 2, wherein the semiconductor switching element has p-type or n-type characteristics, and a p-type thin film transistor element and an n-type thin film transistor element are arranged alternately for each row of the scanning electrodes. An active matrix liquid crystal display device characterized by the above. 16. A plurality of scan electrodes and signal electrodes formed in a matrix, and a plurality of semiconductor switching elements having enhancement-type characteristics formed corresponding to the intersections of the respective scan electrodes and signal electrodes. A first substrate having: a second substrate provided so as to face the first substrate; and a liquid crystal layer in which a liquid crystal composition is sealed between the first and second substrates. In each of the plurality of pixel regions surrounded by the plurality of scan electrodes and the plurality of signal electrodes on the first substrate, a pixel electrode connected to the corresponding semiconductor switching element and a corresponding scan line An active matrix type liquid crystal display device, characterized in that counter electrodes connected to the electrodes are alternately arranged in a comb shape. 17. The active matrix type liquid crystal display device according to claim 16, wherein the semiconductor switching element is a thin film transistor element. 18. The absolute value of the threshold voltage V _TH of the thin film transistor element according to claim 17, wherein the absolute value of the maximum voltage V _0N applied to the liquid crystal layer is the maximum because the light transmittance of the liquid crystal layer is maximized. An active matrix liquid crystal display device characterized by exceeding the value. 19. The absolute value of the threshold value V _TH of the thin film transistor element according to claim 17, wherein the maximum voltage V _ON applied to the liquid crystal layer is the maximum and the minimum light transmittance of the liquid crystal layer. And an active matrix type liquid crystal display device characterized by exceeding 1/2 of the difference between the minimum voltage V _OFF . 20. The thin film transistor element according to claim 17, wherein the scanning electrode is used as a gate electrode, and a gate insulating layer formed on the gate electrode and a semiconductor active layer formed on the gate insulating layer. An active matrix liquid crystal display device characterized in that 21. The active matrix liquid crystal display device according to claim 20, wherein the semiconductor active layer has a semiconductor active layer doped with an acceptor or a donor. 22. The active matrix type liquid crystal display device according to claim 21, further comprising an intrinsic semiconductor layer laminated on the semiconductor active layer doped with an acceptor or a donor. 23. The active matrix type liquid crystal display device according to claim 20, wherein the semiconductor active layer is made of an amorphous silicon film. 24. The active matrix type liquid crystal display device according to claim 23, wherein the gate insulating layer formed on the gate electrode of the thin film transistor element has a SiON film or a SiO film. 25. The active matrix type liquid crystal display device according to claim 24, wherein the gate insulating layer is formed by laminating a SiON film and a SiO film. 26. The thin film transistor element according to claim 20, wherein the thin film transistor element has a source electrode and a drain electrode formed on the semiconductor active layer, and the source electrode and the drain electrode correspond to the corresponding signal electrode and pixel electrode, respectively. An active matrix type liquid crystal display device, characterized in that the gate electrodes are connected to each other and are offset to the source electrode or drain electrode side. 27. The active matrix type liquid crystal display device according to claim 26, wherein the gate electrode has a gap.