JPH0832647A - Serial communication controller - Google Patents

Abstract

PURPOSE:To provide a serial communication controller which can judge a reception error that time reception time becomes shorter than time required for normally receiving data as abnormal data and which can improve the reliability of reception data. CONSTITUTION:In the case of abnormal data in which one transmitted byte is shorter than normal time, transmission is completed before a down counter 51a overflows, and the down counter 51a is returned to an initial value f1. Thus, a reset signal (j) is not outputted from an AND circuit 53, the down counter 52a is overflown without stopping counting and an overflow signal (g) is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication control device capable of surely detecting a reception error due to an external factor.

[0002]

2. Description of the Related Art An input / output port, which is an interface, is used for mutual use of data between different devices, and the data transmission method of this input / output port includes a synchronous method and an asynchronous method. In the synchronous system, the same clock is used as a clock for timing transmission, and in the asynchronous system, different clocks are used on the transmitting side and the receiving side.

FIG. 5 is a block diagram showing a conventional serial communication control device. In the figure, 1 is a microcomputer of a transmitting side device, 2 is a microcomputer of a receiving side device, and 3 is a microcomputer of a transmitting side device. Input / output port 3a is a transmission register which is a serial / parallel conversion register for data transmission, 4 is an input / output port provided in the microcomputer 2 of the receiving side device, and 4a is a serial / parallel conversion register for data reception. Is a reception register. Further, T _X D is a serial data output terminal, R _X D
Is a serial data input terminal, and CLK is a clock input / output terminal in the case of a synchronous system. Also, a is T _X D to R _X
It is serial data transmitted to D. Reference numeral b denotes a clock signal supplied from the microcomputer 1 of the transmission side device to the microcomputer 2 of the reception side device. In addition,
Although FIG. 5 shows the case where the clock b of the microcomputer 1 of the transmitting side device is used in the microcomputer 2 of the receiving side device, the reverse case is also possible.

Next, the operation will be described. FIG. 6 is a state diagram showing the internal states of the transmission register and the reception register during data transfer. Microcomputer 1 of transmission side device
Transmits the data input to the transmission register 3a one by one from the least significant bit via the signal line a, and the microcomputer 2 of the receiving side device sequentially transmits these data to the reception register 4a from the most significant bit. Store.

Next, the transfer timing at this time will be described. FIG. 7 is a timing chart showing the transfer timing of the input / output port, which is an example when the data length is 8 bits and the parity bit is 1 bit. Output terminal T
The output timing of the _X D is performed by the falling edge of the clock, input timing of the input terminal RxD is performed at the rising edge of the clock. Here, the parity bit includes an odd parity that is set so that the sum of individual output data is an odd number and an even parity that is set so that it is an even number, and is added to improve the reliability of the received data. Is. For example, if the transmission data is "0000
If it is 0001 "and the selected parity is odd parity, the parity bit is" 0 ", and if the selected parity is even parity, the parity bit is" 1 ".

[0006] Further, the transmission is performed by a signal in which a total of 9 pieces of data and a start bit "0" and a stop bit "1" are added before and after the data. Here, the start bit and the stop bit are bits inserted before and after the data to confirm whether or not the data transmission is performed in 8 bits as set.

As described above, in the conventional input / output port 4,
Framing error detection function that checks the number of data from the start bit and stop bit, parity error detection function that checks the data reliability by the parity bit.Although not mentioned above, the next data before reading the received data It has a function to detect an overrun error that occurs when the previous data is lost after receiving the. However, although various error detection functions are provided as described above, it is difficult to secure the safety of transmitted / received data in all environments where there is a drop in power supply voltage, external noise, and the like.

Therefore, in order to reliably prevent a reception error due to an external factor and ensure safety, a serial communication control device capable of detecting a reception error due to an external factor at the input / output port 4 is disclosed in, for example, Japanese Patent Laid-Open No. Hei 4 -157938
Techniques have been proposed as shown in the publication. In the technique disclosed in Japanese Patent Application Laid-Open No. 4-157938, the time from the start of reception of a plurality of data to the end of reception is counted by the time measuring means, and the time measured from the start of reception by the time measuring means to the end of reception exceeds the timeout time. Sometimes, it is determined that a communication error has occurred.

FIG. 8 is a block diagram showing another conventional serial communication control device. In the figure, 11 is a microcomputer of the transmission side device, 12 is a microcomputer of the reception side device, 13 is an input / output port of the microcomputer 11 of the transmission side device, 14 is an input / output port of the microcomputer 12 of the reception side device, and 15 Receives the reception start signal d from the input / output port 14, decrements the counter setting value by 1 each time the internal clock signal c is received, and outputs the overflow signal g when it reaches 0; The count setting value corresponding to the time required for the data transmission time is set, and when the down counter 15a overflows and when the reception completion signal from the input / output port 14 is received, the down register 15a is reset to the initial value f. A timer having and. An interrupt control circuit 16 outputs an interrupt signal to the CPU (central processing unit) of the receiving side device.

Next, the operation will be described. First, the input / output port 13 of the microcomputer 11 of the transmission side device,
Also, both the input / output ports 14 of the microcomputer 12 of the receiving side device become communicable, and the reception start signal d output when the serial communication is started causes the counter to start counting down. If the reception time required at this time is the time required for normal reception, the counter stops counting by the communication completion signal e from the input / output port 14 at the end of counting by the counter 15a, and is stored in the reload register 15b. Since the initial value f being set is set in the counter, the counter 15a
Does not output the overflow signal g.

However, for example, when pulse noise from the outside is added to the clock on the transmitting side as shown in FIG. 9, the input terminal RxD fetches data in accordance with the timing of the clock, and the output terminal TxD outputs one data. Even for data (D1), the read operation is performed twice at the noise portion of the clock at the input terminal RxD. Therefore, since D1 is read as D1 'and D2', the received data will be shifted bit by bit thereafter (... D1 = D1 ', D
1 = D2 '... D6 = D7').

Therefore, the reception time required at this time is shorter than the reception time required for normal reception. Therefore, since the initial value f from the reload register 15b receiving the communication completion signal e before the count of the counter 15a is set, the counter 15a cannot output the overflow signal g as an error signal, and the receiving side device micro. The computer 12 could not judge this received data as abnormal data. As a result, there is a problem that the reliability of the serial communication control device is reduced.

Further, for example, when the "H" level of the transmitting side clock is lowered due to the lowering of the power source voltage as shown in FIG. 10, the receiving side has a level of more than half of the receiving side power source voltage in the figure. "H", below that "L"
Therefore, the fourth clock is not judged to be "H" due to the decrease in the voltage level of the transmission side clock.
This means that the number of clocks has decreased by one pulse. for that reason,
The data acquisition timing will be delayed by one pulse, and the data of the second and subsequent bits will be shifted one by one (...
D1 = D1 ', D3 = D2' ... D7 = D6 ').

Therefore, the reception time required at this time is longer than the reception time required for normal reception. Therefore, since there is no communication completion signal e from the input / output port 14 at the end of counting by the counter 15a, the initial value f stored in the reload register 15b is not set in the counter and the overflow signal g is output from the counter 15a. To be done. When the receiving side device microcomputer 12 receives the overflow signal g, the data receiving operation program is interrupted and the reception error processing subroutine is executed. As a result, the receiving side device microcomputer 12 receives the data receiving operation. There was also the problem of delaying.

[0015]

Since the conventional serial communication control device is configured as described above, in the case of a reception error that becomes shorter than the reception time required when the reception is normally performed, the counter 15a is erroneous. The overflow signal g as a signal could not be output. Therefore, the microcomputer 12 of the receiving side device cannot detect it as abnormal data, and there is a problem that the reliability of the serial communication control device is lowered. When the microcomputer 12 of the receiving side device receives the overflow signal g, the data receiving operation program is interrupted,
Since the reception error processing subroutine is executed, there is a problem that the data reception operation is delayed.

The inventions of claims 1 to 3 have been made in order to solve the above-mentioned problems, and even in the case of a reception error that becomes shorter than the reception time required for normal reception. , Microcomputer 1 of the receiving device
No. 2 can be judged as abnormal data, and an object thereof is to obtain a serial communication control device that improves the reliability of received data.

It is an object of the present invention to obtain a serial communication control device which improves the reliability of received data and does not delay the data receiving operation.

[0018]

In the serial communication control device according to the invention of claim 1, the time required for the second timer means to receive the 1-byte data is shorter than the time required for the normal reception, and it is judged to be abnormal. A time period is set, the count is started when the input / output port starts receiving, and during this count, if the input / output port finishes receiving 1-byte data, an error signal is output to the interrupt control means. Is.

According to another aspect of the serial communication control device of the present invention, the count time setting means counts the time required for receiving the first 1-byte data, and the time longer than this count time is judged to be abnormal. Is set in the first timer means, and a time, which is shorter than the count time and is determined to be abnormal, is set in the second timer means.

In the serial communication control device according to the third aspect of the present invention, the input / output port receives the serially transmitted data in synchronization with the clock, and the third timer means counts when the input / output port starts receiving. At the end of this counting, if the input / output port has not finished receiving one pulse at the end of this count, an error signal is output, and the fourth timer means starts counting when the input / output port starts receiving,
During this counting, if the input / output port finishes receiving one pulse, it outputs an error signal, and when the interrupt control means receives the error signal from the third timer means or the fourth timer means, it notifies the CPU. It outputs the interrupt signal.

In the serial communication control device according to the fourth aspect of the invention, the error flag setting means includes the first to fourth timer means.
When an error signal is received from any of the timer means, an error flag is set in the error detection bit of the microcomputer, the re-sending instruction means periodically checks the error detection bit, and if the error flag is set, It is designed to output a 1-byte data retransmission command in which an error signal has occurred.

[0022]

In the serial communication control device according to the present invention, the time required for receiving 1-byte data is shorter than the time required for normal reception, the time judged as abnormal is set, and the reception of the input / output port is started. When the I / O port finishes receiving the 1-byte data during the counting, a second timer means for outputting an error signal to the interrupt control means is provided. It is possible to detect abnormal data that is shorter than the required reception time.

According to the second aspect of the present invention, the serial communication control device counts the time required for the input / output port to receive the first 1-byte data, and determines a time longer than the count time and judged to be abnormal. By setting the count time setting means for setting to 1 timer means and shorter than the above count time and setting the time judged to be abnormal as the second timer means, it is shorter than the reception time required for normal reception. Such abnormal data can be detected, and the time to be judged as abnormal can be automatically set.

In the serial communication control device according to the third aspect of the present invention, the input / output port receives the serially transmitted data in synchronization with the clock, and the third timer means starts counting when the input / output port starts receiving. At the end of this count, if the input / output port has not finished receiving one pulse, an error signal is output, and the fourth timer means starts counting at the same time when the input / output port starts receiving. An interrupt control that outputs an error signal when the input / output port finishes receiving one pulse, and outputs an interrupt signal to the CPU when the error signal from the third timer means or the fourth timer means is received. By providing the means, it is possible to quickly detect abnormal data that is shorter or longer than the reception time required for normal reception. So that it is.

In the serial communication control device according to the invention of claim 4, when the error flag setting means receives the error signal from the first timer means to the fourth timer means,
A data receiving operation is provided by providing a retransmit instruction means for setting an error flag in the error detection bit of the microcomputer and outputting a retransmit instruction for 1-byte data in which an error signal is generated when the error flag is set. The transmission error processing subroutine can be performed without interrupting the program.

[0026]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of a serial communication control device according to this embodiment. Since the same reference numerals as those of the conventional one indicate the same or corresponding portions, the description thereof will be omitted. In the figure, reference numeral 51 denotes a down counter 51a which, when receiving a reception start signal d from the input / output port 14, decrements the counter setting value by 1 each time the internal clock signal c is received, and outputs an overflow signal i when the value reaches 0. And a count set value shorter than the time required to receive 1 byte of data is set and the down counter 51a overflows, or the reception completion signal e from the input / output port 14
Is a timer (first timer) having a reload register 51b for returning the down counter 51a to the initial value f ₁ .

When 52 receives the reception start signal d from the input / output port 14, the counter setting value is decremented by 1 each time the internal clock signal c is received, and when it reaches 0, the overflow signal g is output and AN shown in
When a down counter 52a that stops counting when it receives a reset signal j from the D circuit 53 and a count set value that is longer than the time required to normally receive 1-byte data is set and the down counter 52a overflows, or A timer (second timer) having a reload register 52b for returning the down counter 52a to the initial value f ₂ when receiving the reset signal j from the AND circuit 53.
Is.

An AND circuit 53 generates a reset signal j by receiving the reception completion signal e from the input / output port 14 and the overflow signal i from the timer 51.
A circuit, 54 is an error flag setting means for setting an error flag (rewriting from "0" to "1") in an error detection bit (register provided for exclusive use) inside the microcomputer 14, and 55 is a receiving side device. When the error flag is set in the microcomputer 12, it is a re-transmission instruction means for transmitting a re-transmission signal p of data in which a transmission error has occurred to the microcomputer 11 of the transmission side device. If the error flag setting means 54 and the re-transmission command means 55 are used in place of the interrupt control circuit 16 in the initial setting, the microcomputer 12 of the receiving side device will cause the interrupt signal k from the interrupt control circuit 16 to be received by the microcomputer 12 of the receiving side device. Is invalidated and it is detected whether or not the error flag is set in the error detection bit.

Next, the operation will be described. First, the operation when the time required to receive 1-byte data is normal will be described. FIG. 2A is a timing chart showing the operation when the time required to receive 1-byte data is normal. First, both the input / output port 13 of the microcomputer 11 of the transmission side device and the input / output port 14 of the microcomputer 12 of the reception side device are in the communication enabled state, and the reception output that is output when the serial communication is started. The down signal 51a is generated by the start signal d.
The down counter 52a starts down counting.
Since this down counter 51a is set to a count setting value shorter than the time required for 1-byte data transmission time, the down counter 51a overflows first, but before the down counter 52a overflows, the I / O port Since the reception completion signal e is output from 14, the AND circuit 53 outputs the reset signal j. Upon receiving the reset signal j, the down counter 52a stops counting and is reset to the initial value f ₁ by the reload register 51b. Therefore, since the overflow signal g is not generated from the down counter 52a, the input / output port 14 is ready to receive the second byte.

Next, the operation when the time required for receiving 1-byte data as shown in FIG. 2B becomes shorter than the normal time will be described. FIG. 2B is a timing chart showing the operation when the time required to receive 1-byte data is shorter than the normal time. First, in the same manner as above, the down counter 51a and the down counter 5 are
2a starts counting down with 2a, but since the transmitted 1-byte data is shorter than the normal time, the transmission is completed before the down counter 51a overflows, and the reception completion signal e is output from the input / output port 14. To be done. Therefore, the down counter 51a stops counting at this point and is returned to the initial value f ₁ by the reload register 51b, so that the overflow signal i is not output. Therefore, the reset signal j is not output from the AND circuit 53, the down counter 52a overflows without stopping counting, and the overflow signal g is output.

Then, the interrupt control circuit 16 outputs an interrupt signal k to the CPU of the receiving side device. As a result, the microcomputer 12 of the receiving side device interrupts the data receiving operation program and executes the receiving error processing subroutine. To do. Also, by default, the interrupt control circuit 1
If the error flag setting means 54 and the retransmission command means 55 are set to be used instead of 6, the microcomputer 12 of the receiving side device detects whether or not the error flag is set in the error detection bit. Here, since the error flag is set in the error detection bit, the retransmission command means 55 transmits the retransmission signal p of the data in which the transmission error has occurred to the microcomputer 11 of the transmission side device. When receiving the re-transmission signal p, the microcomputer 11 of the transmission side device retransmits the data in which a transmission error has occurred in a series of data transmission operations. Therefore, the microcomputer 12 of the receiving side device can execute the reception error processing without interrupting the program.

The operation when the time required to receive 1-byte data as shown in FIG. 2C becomes longer than the normal time will be described. FIG. 2C is a timing chart showing the operation when the time required to receive 1-byte data is longer than the normal time. First, similarly to the above, the down counter 51a and the down counter 52a start down counting, but since the transmitted 1-byte data is longer than the normal time, the down counter 51a overflows and the overflow signal i However, the reception completion signal e is not output from the input / output port 14. Therefore, the reset signal j is not output from the AND circuit 53, the down counter 52a overflows without stopping counting, and the overflow signal g is output. Then, the interrupt control circuit 16 sends an interrupt signal k to the CPU of the receiving device.
Is output. After that, the operation is the same as when the time required to receive 1-byte data is shorter than the normal time, and therefore the description thereof is omitted. In this embodiment, the time required to receive the 1-byte data is the down counter 51a, 5
Although it is set to 2a, the time required to receive a plurality of bytes of data may be set to the down counters 51a and 52a.

As described above, according to the first embodiment, the time required to receive 1-byte data is set shorter than the normal time, and the time required to receive 1-byte data is normal. Timer 52 set longer than time
And the microcomputer 12 of the receiving device is 1
If the time required to receive the byte data is between the two set times, it can be judged as normal received data, and if it is outside the two set times, it can be judged as abnormal data. 12 is capable of reliably determining abnormal data whose received data is shorter or longer than the time required to normally receive 1-byte data, and can execute a reception error processing subroutine.

Further, instead of the interrupt control circuit 16,
When the error flag setting means 54 and the re-transmission command means 55 are selected by the initial setting, the receiving-side device microcomputer 12 can execute the receiving error processing without interrupting the program. Therefore, the first embodiment corresponds to the invention of claim 4.

Example 2. FIG. 3 is a configuration diagram showing the configuration of a serial communication control device according to a second embodiment of the present invention, and the same reference numerals as those of the conventional one indicate the same or corresponding portions, and therefore the description thereof will be omitted. In the figure, 42 is the reload register 5
A bit (switch control bit) set by the setting completion signal n output from the reload register 51a when the counter value is set to 1a or 52b.
When "0" is set in the switch control bit 42, the switch S1 is closed and the switches S2 and S3 are open. When "1" is set, the switch S1 is open and the switches S2 and S3 are closed. Reference numeral 56 is an up counter (count time setting means) that counts the first data reception time.

Next, the operation will be described. First, when the first reception start signal d is input via the input / output port 14, the up counter 56 counts up by 1 in accordance with the internal clock c, and 1 byte of data until the reception completion signal e is input. Count the time required to receive. Since "0" is set in the switch control bit 42 at the first reception of 1-byte data, the reload register setting signal h is output to the reload register 51b and the reload register 52b. Then, the reload register 51b sets a time shorter than the time required when 1-byte data is normally received, and the reload register 52b sets a time longer than the time required when 1-byte data is normally received. To be done.

When these times are set and the switch control bit 42 is set to "1" by the setting completion signal n, the switch S1 is opened and the switch S2 and the switch S are opened.
3 is closed. Also, the bit 42 is configured to be cleared to "0" only at reset and when cleared by software, and the reload register setting signal h is set to It occurs only during data transfer.

If abnormal data is received during the initial data transfer, this abnormal data is loaded into the reload register 5
1a and 51b may be set, but in such a case, the receiving-side device microcomputer 12 continues to judge the second and subsequent received data as abnormal data, and continues to execute the error processing program. Therefore, if you continue to judge the second and subsequent received data as abnormal data and continue to execute the error processing program, for example, execute the clear processing program by software and set the time required to receive 1 byte of data. It is possible to try again.

As described above, according to the second embodiment, similarly to the first embodiment, the microcomputer 12 of the receiving side apparatus seems that the reception data is shorter or longer than the time required to normally receive 1-byte data. It is possible to reliably determine abnormal data and execute the reception error processing subroutine. The up counter 56 counts the reception time of the first reception data, sets a time shorter than this reception time in the reload register 51b, and automatically sets a time longer than this reception time in the reload register 52b. The effect is that you can.

Example 3. In the first embodiment described above, the timer 51 and the timer 52 are set to a time shorter or longer than the time required for normally receiving 1-byte data, but in the third embodiment, one pulse of the clock b is normally set. The timer 51 (third timer) and the timer 52 (fourth timer) are set to a time shorter or longer than the time required for the reception. Moreover, since the configuration is the same as that of the serial communication control device shown in the first embodiment,
Description is omitted.

Next, as a method of counting the clock b at the input / output port 14, as shown in FIG.
5a and the counter 15b start counting in synchronization with the rising edge of the clock b and stop counting in synchronization with the falling edge. Regarding the counting method, counting is performed in synchronization with the falling edge of the clock b. The count may be started and stopped in synchronization with the rising edge.

Therefore, as shown in FIG. 9, even when noise enters the transmitting clock b and the transmission data is read in synchronization with this noise pulse, the noise pulse width is shorter than the normal pulse width. An overflow signal g is output from the down counter 52a. Therefore, the receiving-side device microcomputer 12 can judge the received data as abnormal data and execute the reception error processing subroutine.

Further, as shown in FIG. 10, even when the voltage level of the transmitting side clock b is lowered and the transmission data is read with a delay of one pulse in the data acquisition timing, the "L" level pulse width is Since the pulse width is longer than the normal pulse width, the down counter 52a outputs the overflow signal g. Therefore, the receiving-side device microcomputer 12 can judge the received data as abnormal data and execute the reception error processing subroutine.

[0044]

As described above, according to the first aspect of the present invention, the time required for the second timer means to receive 1-byte data is shorter than the reception time required for normal reception.
The time determined to be abnormal is set in the counter, and counting is started when the input / output port starts receiving. If the input / output port finishes receiving 1-byte data during this counting, an error signal is sent to the interrupt control means. Since it is configured to output, it becomes possible to detect abnormal data that is shorter and longer than the reception time required for normal reception, and the reliability of received data can be improved. There is.

According to the second aspect of the invention, the time required for the input / output port to receive the first 1-byte data is counted, and the time longer than this count time and judged to be abnormal is the first timer means. In addition to the above, the count time setting means for setting the second timer means for the time determined to be abnormal, which is shorter than the above count time, is shorter than the reception time required for normal reception,
Also, it becomes possible to detect abnormal data that becomes long, and there is an effect that the reliability of received data can be improved. In addition, it becomes possible to automatically set the time when it is determined to be abnormal.

According to the third aspect of the invention, the input / output port receives the serially transmitted data in synchronization with the clock, and the third timer means starts counting when the input / output port starts receiving. At the end of counting, if the input / output port has not finished receiving one pulse, an error signal is output, and the fourth timer means starts counting when the input / output port starts receiving. An interrupt control means is provided which outputs an error signal when the port finishes receiving one pulse and outputs an interrupt signal to the CPU when the error signal is received from the third timer means or the fourth timer means. Because
Abnormal data that is shorter and longer than the reception time required for normal reception can be detected more quickly, and the reliability of the received data can be improved.

According to the fourth aspect of the invention, when the error flag setting means receives the error signal from the first timer means to the fourth timer means, the error flag is set in the error detection bit of the microcomputer, The error detection bit is regularly checked, and if the error flag is set, the re-transmission command means for outputting the re-transmission command of the 1-byte data in which the error signal is generated is provided, so that the program is not interrupted. The effect is that reception error processing can be executed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a reception error detection apparatus according to an embodiment of the present invention.

FIG. 2 is a timing chart showing operations when the time required to receive 1-byte data is (a) normal, (b) short, and (c) long.

FIG. 3 is a configuration diagram showing a configuration of a serial communication control device that is Embodiment 2 of the present invention.

FIG. 4 is a pulse diagram for explaining count timings of input / output ports in the third embodiment.

FIG. 5 is a configuration diagram showing a conventional serial communication control device.

FIG. 6 is a state diagram showing internal states of a transmission register and a reception register during data transfer.

FIG. 7 is a timing chart showing transfer timings of input / output ports.

FIG. 8 is a configuration diagram showing a conventional serial communication control device.

FIG. 9 is a timing chart showing a state in which pulse noise from the outside is added to the transmission clock b.

FIG. 10 is a timing chart showing a state in which the “H” level of the transmitting clock b is lowered due to the lowering of the power supply voltage.

[Explanation of symbols]

13, 14 I / O ports, 16 interrupt control circuit,
51 timers (second timer means, third timer means), 5
2 timers (first timer means, fourth timer means), 54
Error flag setting means, 55 retransmission instruction means, 56
Up counter (count time setting means).

Claims (4)

[Claims] 1. An input / output port for receiving serially transmitted data in synchronism with a clock, and a time required for receiving 1-byte data is longer than a time required for normal reception and is determined to be abnormal. Is set, and when the input / output port starts receiving, counting is started, and at the end of this count, if the input / output port has not finished receiving 1-byte data, first timer means for outputting an error signal. In a serial communication control device having an interrupt control means for outputting an interrupt signal to the CPU when an error signal is received from the first timer means, reception of a normal time required to receive 1-byte data is performed. It is set to be shorter than the time required for, and the time determined to be abnormal is set. In the serial communication control device, a second timer means is provided for outputting an error signal to the interrupt control means when the input / output port finishes receiving 1-byte data. 2. The time required for the input / output port to receive the first 1-byte data is counted, and a time longer than this count time and judged to be abnormal is set in the first timer means. 2. The serial communication control device according to claim 1, further comprising count time setting means for setting, in the second timer means, a time which is shorter than the count time and which is determined to be abnormal. 3. An input / output port for receiving serially transmitted data in synchronism with a clock, and a time required for receiving one pulse of the clock is longer than a time required for normal reception and judged to be abnormal. A count time is set, a count is started when the reception of the input / output port is started, and at the end of the count, if the input / output port has not finished receiving one pulse, an error signal is output.
The timer means and the time required to receive one pulse of the clock are set shorter than the time required to receive normally, and the time determined to be abnormal is set, and the counting is started when the reception of the input / output port is started. When the input / output port finishes receiving one pulse, the CPU outputs the error signal from the fourth timer means for outputting an error signal and the third timer means or the fourth timer means. An interrupt control means for outputting an interrupt signal to the serial communication control device. 4. An error flag setting means for setting an error flag in an error detection bit of the CPU when an error signal is received from any one of the fourth timer means from the first timer means, and 7. Retransmission command means for periodically confirming an error detection bit and, when said error flag is set, outputting a re-transmission command of 1-byte data in which an error signal has occurred. The serial communication control device according to any one of claims 1 to 3.