JPH0831973A - Packaging method of flip-chip ic and semiconductor device - Google Patents
Packaging method of flip-chip ic and semiconductor deviceInfo
- Publication number
- JPH0831973A JPH0831973A JP6159769A JP15976994A JPH0831973A JP H0831973 A JPH0831973 A JP H0831973A JP 6159769 A JP6159769 A JP 6159769A JP 15976994 A JP15976994 A JP 15976994A JP H0831973 A JPH0831973 A JP H0831973A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- flip
- pad electrode
- flip chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、フリップチップＩＣ実
装方法及び半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip IC mounting method and a semiconductor device.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図５はかかる
従来のフリップチップＩＣの実装工程図である。この図
において、１はフリップチップＩＣ３を搭載する基板、
２は基板１上に形成される電極であり、基板１と強固に
固定されている。４はフリップチップＩＣ３に形成さた
半田バンプである。2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there were the following. FIG. 5 is a mounting process diagram of such a conventional flip chip IC. In this figure, 1 is a substrate on which the flip chip IC 3 is mounted,
Reference numeral 2 denotes an electrode formed on the substrate 1, which is firmly fixed to the substrate 1. Reference numeral 4 is a solder bump formed on the flip chip IC 3.
【０００３】まず、図５（ａ）に示すように、基板１上
にフリップチップＩＣ３を位置決めする。次に、図５
（ｂ）に示すように、基板１上にフリップチップＩＣ３
を搭載し、基板１とフリップチップＩＣ３を加熱し、半
田バンプ４をリフローし、電極２と半田バンプ４を電気
・機械的に接続する。First, as shown in FIG. 5A, the flip chip IC 3 is positioned on the substrate 1. Next, FIG.
As shown in (b), the flip chip IC 3 is formed on the substrate 1.
Then, the substrate 1 and the flip chip IC 3 are heated, the solder bumps 4 are reflowed, and the electrodes 2 and the solder bumps 4 are electrically and mechanically connected.
【０００４】次に、図５（ｃ）は、リフローが完了し、
フリップチップＩＣ３と基板１が、半田バンプ４と電極
２を経由し強固に接続された状態を示す。図６は従来の
フリップチップＩＣ実装方法における熱膨張率差による
機械的ストレス発生状態を示す図である。この図に示す
ように、フリップチップＩＣ３と基板１の熱膨張率差に
より、基板１とフリップチップＩＣ３は相対的に位置が
変動し、各部には剪断方向に力が加わるが、断面積が最
も小さい半田バンプ４がわずかに変形し、小さなクラッ
ク５を生じることにより、機械的ストレスを吸収するよ
うに作用する。Next, in FIG. 5C, the reflow is completed,
The flip chip IC 3 and the substrate 1 are firmly connected via the solder bumps 4 and the electrodes 2. FIG. 6 is a diagram showing a mechanical stress generation state due to a difference in coefficient of thermal expansion in a conventional flip chip IC mounting method. As shown in this figure, due to the difference in the coefficient of thermal expansion between the flip chip IC 3 and the substrate 1, the positions of the substrate 1 and the flip chip IC 3 relatively change, and a force is applied to each part in the shearing direction, but the cross-sectional area is the largest. The small solder bumps 4 are slightly deformed, and small cracks 5 are generated, so that the mechanical stress is absorbed.
【０００５】[0005]
【発明が解決しようとする課題】このように、上記した
従来の実装方法では、フリップチップＩＣとその搭載基
板の熱膨張率差による機械的ストレスが、フリップチッ
プＩＣと、その搭載基板を電気・機械的に接続している
半田バンプ部に集中して作用し、半田バンプ部が切断さ
れ、機能障害を生じる問題点があり、半田バンプの形状
により接続の信頼性が変わるため、半田バンプの形状を
精密に制御する必要があった。As described above, in the above-described conventional mounting method, the mechanical stress caused by the difference in the coefficient of thermal expansion between the flip chip IC and the mounting substrate causes the flip chip IC and the mounting substrate to electrically and electrically. There is a problem that it concentrates on the solder bumps that are mechanically connected, cutting the solder bumps and causing functional failure.The connection reliability changes depending on the shape of the solder bumps. Had to be precisely controlled.
【０００６】また、安価であるが、フリップチップＩＣ
の熱膨張率と大きく異なる基板材料（例えば、ガラスエ
ポキシ基板）は、接続の信頼性が低いという理由で、高
い信頼性が要求される物には使用されず、ＳｉＮ等の高
価な基板が主に使用されていたために、用途が限定さ
れ、低価格化が要求される一般向けには採用することが
できなかった。A flip chip IC, which is inexpensive,
The substrate material (for example, glass epoxy substrate) that greatly differs from the coefficient of thermal expansion is not used for the objects that require high reliability because the connection reliability is low, and expensive substrates such as SiN are mainly used. Since it has been used for, the application was limited, and it was not possible to adopt it for the general public that requires low price.
【０００７】本発明は、以上述べた、問題点を除去し、
半田バンプ及び搭載基板の熱膨張率に依存しない接続の
信頼性が高いフリップチップＩＣ実装方法及び半導体装
置を提供することを目的とする。The present invention eliminates the above-mentioned problems,
An object of the present invention is to provide a flip-chip IC mounting method and a semiconductor device which have a highly reliable connection that does not depend on the thermal expansion coefficient of the solder bump and the mounting substrate.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するために、フリップチップＩＣを基板上へ搭載する
フリップチップＩＣ実装方法において、フリップチップ
ＩＣが搭載される基板上から一端部が浮いた折曲部を有
するパッド電極を形成する工程と、このパッド電極上に
フリップチップＩＣの半田バンプをリフローにより接続
する工程とを施すようにしたものである。In order to achieve the above object, the present invention provides a flip chip IC mounting method for mounting a flip chip IC on a substrate, wherein one end of the flip chip IC is mounted on the substrate. The step of forming a pad electrode having a floating bent portion and the step of connecting the solder bump of the flip chip IC by reflow on the pad electrode are performed.
【０００９】また、前記パッド電極の形成は、前記基板
上にイオン化傾向が高いダミー金属膜を選択的に形成す
る工程と、前記ダミー金属膜上に該ダミー金属膜よりは
イオン化傾向が低い配線導体を形成する工程と、この配
線導体をエッチングでパッド電極をパターン形成時に、
前記ダミー金属膜を完全にエッチングにより除去し、前
記パッド電極をフリップチップＩＣを搭載する基板上よ
り剥離させる工程とを施すようにしたものである。The pad electrode is formed by selectively forming a dummy metal film having a high ionization tendency on the substrate and a wiring conductor having a lower ionization tendency than the dummy metal film on the dummy metal film. And a step of forming a pad electrode by etching this wiring conductor,
The dummy metal film is completely removed by etching, and the pad electrode is removed from the substrate on which the flip chip IC is mounted.
【００１０】更に、前記パッド電極の形成は、前記基板
上にダミー樹脂膜を選択的に形成する工程と、このダミ
ー樹脂膜上に配線導体を形成する工程と、この配線導体
をエッチングでパッド電極をパターン形成時に、溶剤等
で樹脂を完全に除去し、このパッド電極を前記基板上よ
り剥離させる工程とを施すようにしたものである。ま
た、フリップチップＩＣを搭載する基板を有する半導体
装置において、一端部が浮いた折曲部を有するパッド電
極が形成される基板と、この基板のパッド電極に半田バ
ンプにより接続されてなるフリップチップＩＣを設ける
ようにしたものである。Further, the pad electrode is formed by selectively forming a dummy resin film on the substrate, forming a wiring conductor on the dummy resin film, and etching the wiring conductor to form a pad electrode. When the pattern is formed, the step of completely removing the resin with a solvent or the like and peeling the pad electrode from the substrate is performed. Further, in a semiconductor device having a substrate on which a flip chip IC is mounted, a substrate on which a pad electrode having a bent portion whose one end is floated is formed, and a flip chip IC which is connected to the pad electrode of this substrate by a solder bump. Is provided.
【００１１】[0011]
【作用】本発明によれば、上記したように、フリップチ
ップＩＣを搭載する基板において、その基板上に形成さ
れたパッド電極（例えば、Ｃｕ）の下層に、パッド電極
よりもイオン化傾向の高い金属膜（例えば、Ａｌ）を、
剥離が必要な部分にのみ形成しておき、パッド電極をエ
ッチングする時に、同時にイオン化傾向の高い金属膜を
全て除去し、パッド電極を基板表面より剥離させ、その
剥離させたパッド電極上にフリップチップＩＣの半田バ
ンプを載せ、一括リフローし、半田バンプと基板上より
剥離させたパッド電極を電気・機械的に接続する。According to the present invention, as described above, in the substrate on which the flip chip IC is mounted, a metal having a higher ionization tendency than the pad electrode is formed under the pad electrode (eg, Cu) formed on the substrate. A film (eg Al)
It is formed only on the part that needs to be peeled off, and when the pad electrode is etched, at the same time all the metal film with a high ionization tendency is removed, the pad electrode is peeled off from the substrate surface, and the flipped chip is placed on the peeled pad electrode. The solder bumps of the IC are mounted and reflowed at once, and the solder bumps and the pad electrodes separated from the substrate are electrically and mechanically connected.
【００１２】[0012]
【実施例】以下、本発明の実施例について順次説明す
る。図１は本発明の実施例を示す半導体装置の断面図で
ある。この図において、１１はフリップチップＩＣ１４
を搭載する基板、１２は配線導体、１３はその配線導体
１２が基板１１より浮いたパッド電極、１４はフリップ
チップＩＣ、１５はフリップチップＩＣ１４に形成され
た半田バンプである。EXAMPLES Examples of the present invention will be sequentially described below. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. In this figure, 11 is a flip chip IC 14
Is a wiring conductor, 13 is a pad electrode on which the wiring conductor 12 floats from the substrate 11, 14 is a flip chip IC, and 15 is a solder bump formed on the flip chip IC 14.
【００１３】このように、フリップチップＩＣ搭載基板
（以下、単に基板という）１１上に密着した配線導体１
２から折曲部１６を経て、パッド電極１３は基板１１上
より浮いている。このパッド電極１３に半田バンプ１５
により、フリップチップＩＣ１４が電気・機械的に接続
される。したがって、従来技術で述べたように、半田バ
ンプ部に集中していた熱膨張率差による機械的ストレス
は、ここでは、その折曲部１６及び基板１１上より浮い
た部分が変形することにより吸収されるので、半田バン
プ部でクラックが発生しなくなり、接続の信頼性を確保
することができる。In this way, the wiring conductor 1 closely attached to the flip-chip IC mounting substrate (hereinafter, simply referred to as substrate) 11
The pad electrode 13 floats above the substrate 11 from 2 through the bent portion 16. Solder bumps 15 are formed on the pad electrodes 13.
Thus, the flip chip IC 14 is electrically and mechanically connected. Therefore, as described in the prior art, the mechanical stress due to the difference in the coefficient of thermal expansion concentrated on the solder bump portion is absorbed here by the bent portion 16 and the portion floating above the substrate 11 being deformed. As a result, cracks do not occur in the solder bumps, and the reliability of connection can be ensured.
【００１４】図２は本発明の実施例を示すフリップチッ
プＩＣ搭載基板のパッド電極の第１の形成工程断面図で
ある。この図において、２１はフリップチップＩＣ（図
示なし）を搭載する基板、２２はパッド電極２５（後
述）よりもイオン化傾向の高い金属膜であり、例えば、
Ａｌ等を用いる。２３は配線導体であり、例えば、Ｃｕ
等を用いる。２４はパッド電極２５を形成するためのレ
ジストである。FIG. 2 is a sectional view of a first step of forming pad electrodes on a flip-chip IC mounting substrate showing an embodiment of the present invention. In this figure, 21 is a substrate on which a flip-chip IC (not shown) is mounted, 22 is a metal film having a higher ionization tendency than a pad electrode 25 (described later).
Al or the like is used. Reference numeral 23 is a wiring conductor, for example, Cu
Etc. are used. Reference numeral 24 is a resist for forming the pad electrode 25.
【００１５】まず、図２（ａ）に示すように、フリップ
チップＩＣ（図示なし）を搭載する基板２１上の特定領
域に金属膜２２を形成する。次に、図２（ｂ）に示すよ
うに、上記金属膜２２上を含む基板２１上の全面に配線
導体２３を形成する。次に、図２（ｃ）に示すように、
上記配線導体２３上にレジスト２４を印刷等により塗布
し、レジスト２４をパターニングする。First, as shown in FIG. 2A, a metal film 22 is formed in a specific region on a substrate 21 on which a flip chip IC (not shown) is mounted. Next, as shown in FIG. 2B, the wiring conductor 23 is formed on the entire surface of the substrate 21 including the metal film 22. Next, as shown in FIG.
A resist 24 is applied on the wiring conductor 23 by printing or the like, and the resist 24 is patterned.
【００１６】次に、図２（ｄ）に示すように、レジスト
２４をマスクにして配線導体２３及び全ての特定領域の
金属膜２２をエッチングにより除去する。ここで、金属
膜２２は配線導体２３がエッチングされ、そのエッチン
グ液（例えば、塩化第二鉄及びクロム酸と塩酸の混合液
等）が金属膜２２に接触すると、金属膜２２はイオン化
傾向が低い配線導体２３よりもイオン化傾向が高い金属
膜であるため、その配線導体２３の基板２１面側がエッ
チングで除去される前に完全に除去され、金属膜２２上
に基板２１上より剥離されるパッド電極２５が形成され
る。このように、基板２１より浮いたパッド電極２５が
形成されると、レジスト２４は除去する。Next, as shown in FIG. 2D, the wiring conductor 23 and the metal film 22 in all specific regions are removed by etching using the resist 24 as a mask. Here, when the wiring conductor 23 of the metal film 22 is etched and the etching liquid (for example, ferric chloride and a mixed liquid of chromic acid and hydrochloric acid) comes into contact with the metal film 22, the metal film 22 has a low ionization tendency. Since the metal film has a higher ionization tendency than the wiring conductor 23, the wiring conductor 23 is completely removed before the substrate 21 surface side is removed by etching, and the pad electrode is peeled from the substrate 21 on the metal film 22. 25 is formed. When the pad electrode 25 floating above the substrate 21 is formed in this way, the resist 24 is removed.
【００１７】なお、パッド電極２５には、基板２１上よ
り剥離された部分と、基板２１上に固定されている部分
の境部に折曲部が形成され、この折曲部分及び、基板２
１上より剥離されたパッド電極２５が変形することによ
り、機械的ストレスを吸収する。図３は本発明の実施例
を示すフリップチップＩＣ搭載基板のパッド電極の第２
の形成工程断面図である。In the pad electrode 25, a bent portion is formed at a boundary between a portion separated from the substrate 21 and a portion fixed on the substrate 21, and the bent portion and the substrate 2 are formed.
The pad electrode 25 peeled from above 1 is deformed to absorb mechanical stress. FIG. 3 shows the second embodiment of the pad electrode of the flip-chip IC mounting substrate showing the embodiment of the present invention.
FIG. 6 is a sectional view of a forming step of
【００１８】まず、図３（ａ）に示すように、フリップ
チップＩＣ（図示なし）を搭載する基板３１上の特定領
域に、特定の溶剤にのみ溶解する樹脂膜３２を形成す
る。次いで、図３（ｂ）に示すように、樹脂膜３２を含
む基板３１上の全面に配線導体３３を形成する。次に、
図３（ｃ）に示すように、配線導体３３上にレジスト３
４を印刷等により塗布し、レジスト３４をパターニング
する。First, as shown in FIG. 3A, a resin film 32 which is soluble only in a specific solvent is formed in a specific region on a substrate 31 on which a flip chip IC (not shown) is mounted. Next, as shown in FIG. 3B, the wiring conductor 33 is formed on the entire surface of the substrate 31 including the resin film 32. next,
As shown in FIG. 3C, the resist 3 is formed on the wiring conductor 33.
4 is applied by printing or the like, and the resist 34 is patterned.
【００１９】次に、図３（ｄ）に示すように、レジスト
３４をマスクにして配線導体３３をエッチング液で除去
後に、樹脂膜３２等を溶剤〔ＮＭＤ３、ＮＭＰ（Ｎ−メ
チル２ピロリジノン）等〕で除去し、基板２１上より剥
離されたパッド電極３５を形成する。このパッド電極３
５を形成後にレジスト３４を除去する。このように、図
２の第１の工程で用いた金属膜２２の代わりに、第２の
工程では、特定の溶剤にのみ溶解する樹脂膜３２を用い
る。Next, as shown in FIG. 3D, after the wiring conductor 33 is removed with an etching solution using the resist 34 as a mask, the resin film 32 and the like are removed with a solvent [NMD3, NMP (N-methyl-2pyrrolidinone), etc.]. ] Then, the pad electrode 35 separated from the substrate 21 is formed. This pad electrode 3
After forming 5, the resist 34 is removed. As described above, instead of the metal film 22 used in the first step of FIG. 2, the resin film 32 that is soluble only in a specific solvent is used in the second step.
【００２０】図４は本発明の実施例を示すパッド電極の
剥離状態を示す平面図であり、図４（ａ）は矩形の領域
剥離状態を示す平面図、図４（ｂ）は選択剥離状態を示
す平面図である。図４（ａ）に示すように、フリップチ
ップＩＣ（図示なし）を搭載する基板４１上には配線導
体４２が形成され、その配線導体４２の一端部が基板４
１より浮いたパッド電極４３を配置し、そのパッド電極
４３に矩形のフリップチップＩＣ４４を実装することが
できる。FIG. 4 is a plan view showing a peeled state of a pad electrode showing an embodiment of the present invention, FIG. 4 (a) is a plan view showing a rectangular area peeled state, and FIG. 4 (b) is a selectively peeled state. FIG. As shown in FIG. 4A, a wiring conductor 42 is formed on a substrate 41 on which a flip chip IC (not shown) is mounted, and one end portion of the wiring conductor 42 is formed on the substrate 4
It is possible to dispose the pad electrode 43 that is more floating than 1 and mount the rectangular flip chip IC 44 on the pad electrode 43.
【００２１】このように、特定領域内の全てのパッド電
極４３を基板４１上より剥離させるようにしている。ま
た、図４（ｂ）に示すように、フリップチップＩＣ（図
示なし）を搭載する基板４５上には配線導体４６が形成
され、その配線導体４６の一端部が基板４５より浮いた
パッド電極４７を配置する。As described above, all the pad electrodes 43 in the specific region are separated from the substrate 41. Further, as shown in FIG. 4B, a wiring conductor 46 is formed on a substrate 45 on which a flip-chip IC (not shown) is mounted, and one end of the wiring conductor 46 is a pad electrode 47 floating above the substrate 45. To place.
【００２２】この場合は、各パッド電極４７ごとに細か
く基板４５上より剥離させる部分を選択した例であり、
基板４５から浮いたパッド電極４７を形成する領域をコ
ントロールすることにより、接続箇所を自由に設定でき
る。また、本発明は、上記実施例に限定されるものでは
なく、本発明の趣旨に基づき種々の変形が可能であり、
それらを本発明の範囲から排除するものではない。In this case, each pad electrode 47 is an example in which a portion to be peeled off from the substrate 45 is selected finely.
By controlling the region where the pad electrode 47 floating from the substrate 45 is formed, the connection location can be set freely. Further, the present invention is not limited to the above embodiments, various modifications are possible based on the spirit of the present invention,
They are not excluded from the scope of the invention.
【００２３】[0023]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、半田バンプ接続用パッド電極を基板より選択的
に剥離させたので、半田バンプ接続後のフリップチップ
ＩＣとその搭載基板の熱膨張率差による機械的ストレス
が、従来のように半田バンプ部に集中することなく、搭
載基板上から剥離したパッド電極及びその折曲部に分散
するので、半田バンプ形状を精密にコントロールしなく
ても、接続の信頼性が確保できる。As described above in detail, according to the present invention, since the solder bump connection pad electrode is selectively peeled from the substrate, the flip chip IC after the solder bump connection and the mounting substrate thereof are mounted. Mechanical stress due to the difference in coefficient of thermal expansion is not concentrated on the solder bumps as in the past, but is distributed to the pad electrodes and the bent parts peeled off from the mounting substrate, so the solder bump shape is not precisely controlled. However, the reliability of the connection can be secured.
【００２４】また、搭載基板として、フリップチップＩ
Ｃと熱膨張率が大きく異なるが、安価な基板（例えば、
ガラスエポキシ基板）が使用可能となり、製品の低価格
化が可能である。更に、フリップチップＩＣとその搭載
基板の接続だけでなく、主基板と副基板等の接続にも適
用可能である。As a mounting substrate, a flip chip I
Although the coefficient of thermal expansion is greatly different from that of C, an inexpensive substrate (for example,
(Glass epoxy substrate) can be used, and the product price can be reduced. Further, the present invention can be applied not only to the connection of the flip chip IC and its mounting substrate, but also to the connection of the main substrate and the sub substrate.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の実施例を示す半導体装置の断面図であ
る。FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention.
【図２】本発明の実施例を示す半導体装置のフリップチ
ップＩＣ搭載基板のパッド電極の第１の形成工程断面図
である。FIG. 2 is a sectional view of a first step of forming pad electrodes on a flip-chip IC mounting substrate of a semiconductor device showing an embodiment of the present invention.
【図３】本発明の実施例を示す半導体装置のフリップチ
ップＩＣ搭載基板のパッド電極の第２の形成工程断面図
である。FIG. 3 is a sectional view of a second forming step of the pad electrode of the flip-chip IC mounting substrate of the semiconductor device showing the embodiment of the present invention.
【図４】本発明の実施例を示すパッド電極の剥離状態を
示す平面図である。FIG. 4 is a plan view showing a peeled state of a pad electrode showing an example of the present invention.
【図５】従来のフリップチップＩＣの実装工程図であ
る。FIG. 5 is a mounting process diagram of a conventional flip chip IC.
【図６】従来のフリップチップＩＣ実装方法における熱
膨張率差による機械的ストレス発生状態を示す図であ
る。FIG. 6 is a diagram showing a mechanical stress generation state due to a difference in thermal expansion coefficient in a conventional flip chip IC mounting method.
１１，２１，３１，４１，４５ フリップチップＩＣ
搭載基板 １２，２３，３３，４２，４６ 配線導体（Ｃｕ） １３，２５，３５，４３，４７ パッド電極 １４，４４ フリップチップＩＣ １５ 半田バンプ １６ 折曲部 ２２ 金属膜（Ａｌ膜） ２４，３４ レジスト ３２ 樹脂膜11,21,31,41,45 Flip chip IC
Mounting board 12,23,33,42,46 Wiring conductor (Cu) 13,25,35,43,47 Pad electrode 14,44 Flip chip IC 15 Solder bump 16 Bent part 22 Metal film (Al film) 24,34 Resist 32 resin film
Claims (4)
フリップチップＩＣ実装方法において、（ａ）フリップ
チップＩＣが搭載される基板上から一端部が浮いた折曲
部を有するパッド電極を形成する工程と、（ｂ）該パッ
ド電極上にフリップチップＩＣの半田バンプをリフロー
により接続する工程とを施すことを特徴とするフリップ
チップＩＣ実装方法。1. A flip-chip IC mounting method for mounting a flip-chip IC on a substrate, the method comprising: (a) forming a pad electrode having a bent portion whose one end floats above the substrate on which the flip-chip IC is mounted. And (b) a step of connecting the solder bumps of the flip chip IC to the pad electrodes by reflow, the flip chip IC mounting method.
方法において、前記パッド電極の形成は、前記基板上に
イオン化傾向が高いダミー金属膜を選択的に形成する工
程と、前記ダミー金属膜上に該ダミー金属膜よりはイオ
ン化傾向が低い配線導体を形成する工程と、該配線導体
をエッチングでパッド電極をパターン形成時に、前記ダ
ミー金属膜を完全にエッチングにより除去し、前記パッ
ド電極をフリップチップＩＣを搭載する基板上より剥離
させる工程とを施すことを特徴とするフリップチップＩ
Ｃ実装方法。2. The flip chip IC mounting method according to claim 1, wherein the pad electrode is formed by a step of selectively forming a dummy metal film having a high ionization tendency on the substrate, and on the dummy metal film. The step of forming a wiring conductor having a lower ionization tendency than the dummy metal film, and the pad electrode is patterned by etching the wiring conductor, the dummy metal film is completely removed by etching, and the pad electrode is flip chip IC. And a step of peeling from the substrate on which the flip chip I is mounted.
C mounting method.
方法において、前記パッド電極の形成は、前記基板上に
ダミー樹脂膜を選択的に形成する工程と、該ダミー樹脂
膜上に配線導体を形成する工程と、該配線導体をエッチ
ングでパッド電極をパターン形成時に、溶剤等で樹脂を
完全に除去し、該パッド電極を前記基板上より剥離させ
る工程とを施すことを特徴とするフリップチップＩＣ実
装方法。3. The flip-chip IC mounting method according to claim 1, wherein the pad electrode is formed by a step of selectively forming a dummy resin film on the substrate and forming a wiring conductor on the dummy resin film. And a step of completely removing the resin with a solvent or the like when the pattern of the pad electrode is formed by etching the wiring conductor and peeling the pad electrode from the substrate. Method.
する半導体装置において、（ａ）一端部が浮いた折曲部
を有するパッド電極が形成される基板と、（ｂ）該基板
のパッド電極に半田バンプにより接続されてなるフリッ
プチップＩＣを具備する半導体装置。4. In a semiconductor device having a substrate on which a flip-chip IC is mounted, (a) a substrate on which a pad electrode having a bent portion with one end floating is formed, and (b) solder on the pad electrode of the substrate. A semiconductor device having a flip-chip IC connected by bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6159769A JPH0831973A (en) | 1994-07-12 | 1994-07-12 | Packaging method of flip-chip ic and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6159769A JPH0831973A (en) | 1994-07-12 | 1994-07-12 | Packaging method of flip-chip ic and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0831973A true JPH0831973A (en) | 1996-02-02 |
Family
ID=15700871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6159769A Withdrawn JPH0831973A (en) | 1994-07-12 | 1994-07-12 | Packaging method of flip-chip ic and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831973A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG82591A1 (en) * | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with solder via |
| SG82590A1 (en) * | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with strips and via-fill |
| KR20040017625A (en) * | 2002-08-22 | 2004-02-27 | 주식회사 칩팩코리아 | Flip chip package |
| JP2007324396A (en) * | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | Semiconductor device, and its manufacturing method |
-
1994
- 1994-07-12 JP JP6159769A patent/JPH0831973A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG82591A1 (en) * | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with solder via |
| SG82590A1 (en) * | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with strips and via-fill |
| KR20040017625A (en) * | 2002-08-22 | 2004-02-27 | 주식회사 칩팩코리아 | Flip chip package |
| JP2007324396A (en) * | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | Semiconductor device, and its manufacturing method |
| JP4729438B2 (en) * | 2006-06-01 | 2011-07-20 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4728751A (en) | Flexible electrical connection and method of making same | |
| US4048438A (en) | Conductor patterned substrate providing stress release during direct attachment of integrated circuit chips | |
| US6949470B2 (en) | Method for manufacturing circuit devices | |
| US5731636A (en) | Semiconductor bonding package | |
| KR100614548B1 (en) | Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device | |
| US5109601A (en) | Method of marking a thin film package | |
| JP3210881B2 (en) | BGA package board | |
| JP2004119726A (en) | Method of manufacturing circuit device | |
| US4873123A (en) | Flexible electrical connection and method of making same | |
| JP2001156203A (en) | Printed wiring board for mounting semiconductor chip | |
| US7030033B2 (en) | Method for manufacturing circuit devices | |
| US6323438B1 (en) | Printed circuit board and semiconductor device using the same | |
| JPH0831973A (en) | Packaging method of flip-chip ic and semiconductor device | |
| US4965700A (en) | Thin film package for mixed bonding of chips | |
| JP2008118129A (en) | Substrate for flip chip bonding and manufacturing method thereof | |
| JP3496569B2 (en) | Semiconductor device, its manufacturing method and its mounting structure | |
| JPH08111578A (en) | Manufacture of board for mounting ball grid array package | |
| JPH0357617B2 (en) | ||
| JPH11224890A (en) | Semiconductor device and its manufacturing | |
| JP3207266B2 (en) | Manufacturing method of circuit wiring board with circuit component mounting terminals | |
| JPH11321146A (en) | Mask for solder-printing, and its manufacture | |
| KR100343454B1 (en) | Wafer level package | |
| JP2000195890A (en) | Manufacture of semiconductor device | |
| JP2001085558A (en) | Semiconductor device and mountig method therefor | |
| JP2001148393A (en) | Bump forming method, semiconductor device and its manufacturing method, wiring board, and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20011002 |