JPH08305781A - Multiplier - Google Patents

Abstract

PURPOSE: To reduce a circuit area for forming capacitance by respectively connecting capacity coupling parts to two inversional amplifier parts, selecting capacitance with a switch in each capacity coupling part and executing multiplication of two stages. CONSTITUTION: An inversional amplifier part I1 consists of connecting three MOS inverters I11 to I13 in series and the output of the final MOS inverter I13 is fed back to its input by a feedback capacitance CF1. An inverting amplifier part I2 consists of connecting three MOS inverters I21 to I23 in series and the output of the final MOS inverter I23 is fed back to its input by a feedback capacitance CF2. Respective capacity couplings CP1, CP2 are connected to respective amplifier part I1, I2 and capacitance is selected by a switch in each capacity coupling part, so that multiplication of two stages can be executed by circuit size almost equal to a conventional circuit. Thereby, each capacitance capacity can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit, and more particularly to a multiplication circuit for performing direct multiplication of analog input and digital input.

[0002]

2. Description of the Related Art The applicant of the present application discloses in Japanese Unexamined Patent Publication No. 06-195483.
In No. 6, a multiplier is proposed which multiplies an analog input voltage by a digital multiplier. In this multiplier, an input voltage is connected to a capacitive coupling in which a plurality of capacitances are connected in parallel, and a capacitance is selectively connected to the input voltage by a switch to adjust weighting for the input voltage. The output of the capacitive coupling is connected in two stages to an inverting amplifying section in which a feedback capacitance is connected to a series MOS inverter, and the linear characteristic of the output is guaranteed.

Since this multiplier weights only by the capacitance of capacitive coupling, if a large multiplier is set, a large capacitance is required, and there is a problem that the circuit area increases.

[0004]

SUMMARY OF THE INVENTION The present invention was devised to solve the above-mentioned conventional problems, and an object of the present invention is to provide a multiplication circuit capable of reducing the circuit area for forming a capacitance. .

[Means for Solving the Problems]

In the multiplication circuit according to the present invention, a capacitive coupling is connected to each of the inverting amplifiers of the first stage and the second stage, and a capacitance is selected by a switch in each capacitive coupling, whereby a circuit of approximately the same scale as the conventional circuit is provided. It realizes a two-stage multiplication.

[0006]

According to the multiplication circuit of the present invention, the product of the two-stage multipliers becomes a substantial multiplier, so that the capacitance capacity for each multiplier can be set small.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a multiplication circuit according to the present invention will be described with reference to the drawings.

In FIG. 1, a plurality of switches SW1, S
It has a switch circuit composed of W2, SW3, and SW4, and the input voltage is connected in parallel to each switch in this switch circuit. The output of the switch circuit is a capacitive coupling CP1 composed of a plurality of capacitances C1, C2, C3, C4.
Is input to each of the switches SW1, SW2, S
The outputs of W3 and SW4 are capacitances C1, C2 and C.
3 and C4, respectively, so that the capacitance to which the input voltage should be connected can be selected. The inputs of the switches SW1 to SW4 are used to switch between the input voltage and the ground, and Vin or 0V is applied to the capacitance.

The output of the capacitive coupling CP1 is input to the inverting amplifier I1 so that the capacitive coupling voltage output is transmitted to the subsequent stage with good linear characteristics and drive capability.

The inverting amplifier I1 is formed by connecting three stages of MOS inverters I11, I12 and I13 in series, and the output of the final stage MOS inverter I13 is fed back to the input of I1 by the feedback capacitance CF1. The three-stage MOS inverter has a sufficiently large gain,
Further, by feeding back the output to the input, the input and the output match, and as a result, the inverted output of the input can be stably supplied regardless of the load of the subsequent stage.

A ground capacitance CG11 is connected to the output of the MOS inverter I13 and is grounded via this ground capacitance. In addition, the MOS inverter I
Resistances RE11 and RE12 are connected to the output of 12, and RE11 connects the power supply Vdd to the output of I12,
RE12 connects the output of I12 to ground.

These resistances RE11 and RE12 form a balanced resistance with a pair, and a ground capacitance C
Together with G1, it contributes to the prevention of I1 transmission.

The output of the inverting amplifier I1 is input to a switch circuit composed of a plurality of switches SW5, SW6, SW7 and SW8, and the output of the inverting amplifier I1 is connected in parallel to each switch in this switch circuit. The output of the switch circuit is a plurality of capacitances C5, C6, C7, C8.
Input to the capacitive coupling CP2, that is, the outputs of the switches SW5, SW6, SW7, and SW8 are connected to the capacitances C5, C6, C7, and C8, respectively, which selects the capacitance to which the input voltage should be connected. I'm supposed to get it.

The output of the capacitive coupling CP2 is input to the inverting amplification unit I2, and the voltage output of the capacitive coupling is transmitted to the subsequent stage with good linear characteristics and drive capability.

The inverting amplifier I2 is formed by connecting three stages of MOS inverters I21, I22 and I23 in series, and the output of the final stage MOS inverter I23 is fed back to the input of I2 by the feedback capacitance CF2. As a result, similarly to I1, the input from CP2 can be inverted and output with sufficient linearity and drive capability.

Also in the inverting amplifier I2, the ground capacitance CG21 and the balanced resistance RE2 similar to I1 are used.
1, RE22 is connected to prevent outgoing calls.

The capacitive coupling CP1 is connected to a ground capacitance CG12 which is connected in parallel with C1 to C4 and whose input side is connected to the ground instead of Vin, and C
The input side of P2 is parallel to C5 to C8 and I
The grounding capacitance CG22 is connected to the ground instead of the one output.

In a state where all the switches SW1 to SW8 are closed, the output VI1 of I1 is VI1 + Vb = -Vin (C1 + C2 + C3 + C4) / CF1 (1) with the offset voltage being Vb, and the output Vout of I2 is Vout + Vb = -VI1 (C5 + C6 + C7 + C8) / CF2 (2)

If Vb is connected as the ground, Vb
= 0, and the formulas (1) and (2) are summarized as follows: Vout = -Vin (C1 + C2 + C3 + C4) (C5 + C6 + C7 + C8) / (CF1 * CF2) (3).

Here, the combined capacitance of the capacitors whose switches are closed (hereinafter referred to as the effective combined capacitance) is C1.
˜C4 for ΣC1i and C5-C8 for ΣC2i
By expressing, a general multiplication result can be defined. For example, if only SW1, SW3, and SW6 are closed, then ΣC1i = C1 + C3 (4) ΣC2i = C6 (5).

When the multiplication result is expressed based on the above generalization,
It becomes like Formula (6). Vout = −Vin (ΣC1i × ΣC2i) / (CF1 × CF2) (6) As described above, the multiplication result is given as a product of the product of the effective combined capacitances of the capacitive couplings CP1 and CP2. It is possible to perform multiplication with a large multiplier while keeping it relatively small.

C1: C2: C3: C4 = 1: 2: 4: 8
The ratio is set to the capacity ratio of C, and by setting the effective combined capacity, it is possible to perform multiplication with binary digital as a multiplier.
Similar settings are made for No. 8.

Ground capacitances CG12 and CG2
2 has the effect of suppressing the upper limit of the multiplier, and has the effect of further improving the linearity of the output. For example C1: C2: C3: C
4: CG12: CF1 = 1: 2: 4: 8: 1: 16, C
5: C6: C7: C8: CG22: CF2 = 1: 2:
It is set like 4: 8: 1: 16, and the maximum output is (1
It is suppressed to 5/16) × (15/16). However, omitting such a ground capacitance simplifies the design of the multiplier and may be omitted in an actual circuit.

[0024]

As described above, in the multiplication circuit according to the present invention, capacitive coupling is connected to each of the inverting amplifiers of the first and second stages, and the capacitance is selected by the switch in each capacitive coupling. Since the two-stage multiplication is performed in a circuit of a large scale, each capacitance capacity can be set small, and the circuit area for forming the capacitance can be saved, which is an excellent effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a multiplication circuit according to the present invention.

[Explanation of symbols]

I1, I2. ． ． Inverting amplifiers I11, I12, I13, I21, I22, I23
． ． ． Inverters CP1, CP2. ． ． Capacitive coupling C1, C2, C3, C4, C5, C6, C7, C8
． ． ． Capacitance CF1, CF2. ． ． Feedback capacitances CG1, CG2. ． ． Ground capacitance RE11, RE12, RE21, RE22. ． ． Equilibrium resistance Vin. ． ． Input voltage Vout. ． ． Output voltage.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Raken Ken 3-5-18 Kitazawa Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. (72) Nao Takatori 3-5-18 Kitazawa Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. Takayama (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayama Co., Ltd.

Claims (5)

[Claims] 1. A first switch circuit composed of a plurality of switches to which an input voltage is connected in parallel, and a first capacitive coupling connected to the output side of each switch of the first switch circuit and having an integrated output, respectively. A first inverting amplification section composed of an odd-numbered series MOS inverter connected in series to the output of the first capacitive coupling; and a second switch circuit composed of a plurality of switches in which outputs of the first inverting amplification section are connected in parallel. A second capacitive coupling connected to the output side of each switch of the second switch circuit and having an integrated output;
And a second inverting amplification section including an odd-numbered series MOS inverter connected in series to the output of the capacitive coupling. 2. A grounding capacitance is connected between the respective outputs of the first and second inverting amplifiers and the ground, and the grounding capacitance of the MOS inverter is provided in a stage preceding the final stage MOS inverter of the first and second inverting amplifiers. 2. The multiplication circuit according to claim 1, wherein the outputs are connected to the power supply voltage and the ground by a pair of balanced resistances, and the outputs of the first and second inverting amplification sections are connected to the inputs by feedback capacitances. . 3. The multiplication circuit according to claim 1, wherein each capacitance of the first and second capacitive couplings is set to a capacitance distribution corresponding to each digit of a binary number. 4. The first and second capacitive couplings are further connected with a capacitance having a capacitance corresponding to a minimum digit of a binary number,
The multiplication circuit according to claim 1, wherein an input of the capacitance is grounded. 5. The first feedback capacitance has a capacitance equal to the total capacitance of the first capacitive couplings, and the second feedback capacitance has a capacitance equal to the total capacitance of the second capacitive couplings. 1. The multiplication circuit according to 1.