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JPH08298298A - Semiconductor carrier - Google Patents

Semiconductor carrier

Info

Publication number
JPH08298298A
JPH08298298A JP7101938A JP10193895A JPH08298298A JP H08298298 A JPH08298298 A JP H08298298A JP 7101938 A JP7101938 A JP 7101938A JP 10193895 A JP10193895 A JP 10193895A JP H08298298 A JPH08298298 A JP H08298298A
Authority
JP
Japan
Prior art keywords
copper
semiconductor
copper foil
semiconductor carrier
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7101938A
Other languages
Japanese (ja)
Inventor
Yasuo Tanaka
恭夫 田中
Yoshihiko Sekine
良彦 関根
Hiroyuki Urabe
博之 浦部
Morio Take
杜夫 岳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Priority to JP7101938A priority Critical patent/JPH08298298A/en
Publication of JPH08298298A publication Critical patent/JPH08298298A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Laminated Bodies (AREA)
  • Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)

Abstract

PURPOSE: To obtain a semiconductor carrier and a plastic semiconductor package having an excellent heat resistance, moisture resistance, insulating ability, low dielectric constant, and chemical resistance by using an electric insulating layer which is made by impregnating total aromatic liquid crystal polyester nonwoven fabric with cyanate resin component and then hardening it. CONSTITUTION: A conductor circuit is formed on a copper lined laminated sheet; a semiconductor chip 3 is placed on one surface; solder balls are provided at pad portions made of poreless copper foil on the opposite surface; and the terminal of semiconductor chip 3 and a pad copper foil 5 are brought into a continuity. Moreover, the conductor circuit and copper foil 5 are bonded to an electric insulating layer which was produced by impregnating a total aromatic liquid crystal polyester unwoven cloth with a cyanate resin component and then hardening, thereby forming a semiconductor carrier. By doing this, subminiature radius hole machining by laser beam can be performed in an outermost electric insulating layer, from which a semiconductor carrier and a plastic semiconductor package, which can be highly densified, can be produced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高耐熱、高絶縁性、高
耐湿性、低誘電率の半導体キャリアーおよびプラスチッ
ク半導体パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor carrier having a high heat resistance, a high insulation property, a high humidity resistance and a low dielectric constant and a plastic semiconductor package.

【0002】半導体キャリアーおよびプラスチック半導
体パッケージに用いられる、銅張積層板の電気絶縁層
は、ガラス布に熱硬化性樹脂を含浸、硬化させたもの、
アラミド繊維に熱硬化性樹脂を含浸、硬化させたもの、
ポリイミド樹脂を用いたもの等があげられる。
The electric insulating layer of a copper clad laminate used for semiconductor carriers and plastic semiconductor packages is a glass cloth impregnated with a thermosetting resin and cured,
Aramid fiber impregnated with thermosetting resin and cured,
Examples include those using a polyimide resin.

【0003】ガラス布に熱硬化性樹脂を含浸、硬化させ
たものは、一般に良く用いられるが、導体回路と接続す
るためのスルーホールを形成するためには、ドリルを用
いる方法が一般的であるが、超小径孔あけには限界があ
り、半導体キャリアーおよびプラスチック半導体パッケ
ージの高密度化には限界があった。
A glass cloth impregnated with a thermosetting resin and hardened is generally used, but a drill is generally used to form a through hole for connecting to a conductor circuit. However, there is a limit to the drilling of ultra-small diameters, and there is a limit to increasing the density of semiconductor carriers and plastic semiconductor packages.

【0004】アラミド繊維に熱硬化性樹脂を含浸、硬化
させたものは、耐湿性が劣り、信頼性を低下させる。
A aramid fiber impregnated with a thermosetting resin and cured has poor moisture resistance and lowers reliability.

【0005】ポリイミド樹脂硬化物を用いた物は、耐熱
性、耐湿性が劣り、信頼性を低下させる。以上例示した
電気絶縁層では、半導体キャリアーおよびプラスチック
半導体パッケージとしての信頼性が著しく劣る結果とな
る。
A cured product of a polyimide resin is inferior in heat resistance and moisture resistance and lowers reliability. The electrical insulating layer exemplified above results in extremely poor reliability as a semiconductor carrier and a plastic semiconductor package.

【0006】[0006]

【発明が解決しようとする課題】本発明は、上記した従
来の半導体キャリアーおよびプラスチック半導体パッケ
ージ材料の欠点を解消し、信頼性が高い、高密度の半導
体キャリアーおよびプラスチック半導体パッケージに関
するものである。
SUMMARY OF THE INVENTION The present invention relates to a highly reliable, high-density semiconductor carrier and a plastic semiconductor package which solves the above-mentioned drawbacks of the conventional semiconductor carrier and plastic semiconductor package material.

【0007】[0007]

【課題が解決するための手段】すなわち、本発明は、全
芳香族液晶ポリエステル不織布にシアネート樹脂組成物
を含浸、硬化した電気絶縁層を用いることで、耐熱性、
耐湿性、絶縁性、低誘電率、耐薬品性に優れた半導体キ
ャリアーおよびプラスチック半導体パッケージが得ら
れ、加えて、スルーホールそして/または、ブラインド
スルーホールの形成も、レーザー光を照射し、加工でき
ることにより超小径孔も高密度に形成できる事で、問題
を解決するものである。
Means for Solving the Problems That is, according to the present invention, a wholly aromatic liquid crystal polyester non-woven fabric is impregnated with a cyanate resin composition, and an electrically insulating layer obtained by curing is used to obtain a
A semiconductor carrier and a plastic semiconductor package with excellent moisture resistance, insulation, low dielectric constant, and chemical resistance can be obtained, and in addition, through holes and / or blind through holes can be formed by laser irradiation. The problem can be solved by forming ultra-small diameter holes with high density.

【0008】本発明における、熱硬化性樹脂とは、シア
ネート樹脂を樹脂全体の30wt%以上で、他に多価マレイ
ミド、エポキシ樹脂、不飽和ポリエステル樹脂、フェノ
ール樹脂、ジアリルフタレート樹脂、ポリアミン−ビス
マレイミド樹脂、ポリマレイミド−イソシアネート樹
脂、その他の熱硬化性樹脂類;これらを適宜二種以上配
合してなる組成物をポリビニルブチラール、アクリロニ
トリル−ブタジエンゴム、多官能性アクリレート化合
物、ポリフェニレンエーテル等の熱可塑性樹脂、その他
の公知の樹脂、添加剤で変性したものが例示される。
The thermosetting resin in the present invention means a cyanate resin in an amount of 30 wt% or more of the whole resin, and also polyvalent maleimide, epoxy resin, unsaturated polyester resin, phenol resin, diallyl phthalate resin, polyamine-bismaleimide. Resins, polymaleimide-isocyanate resins, other thermosetting resins; thermoplastic resins such as polyvinyl butyral, acrylonitrile-butadiene rubber, polyfunctional acrylate compounds, polyphenylene ether, etc., containing a composition prepared by appropriately mixing two or more of these. , Other known resins, and those modified with additives are exemplified.

【0009】液晶ポリエステル不織布とは、液晶ポリエ
ステル系樹脂を紡糸することによって得られた液晶ポリ
エステル系繊維を用いた不織布である。また、液晶ポリ
エステル系樹脂とは、異方性溶融相を形成することので
きるポリマーである。液晶ポリエステル系繊維は、特に
限定されるものではないが、全芳香族ポリエステル(す
なわち、主鎖が芳香族環の繰り返し単位から構成される
ポリエステル)樹脂からなるものが好ましい。従って、
芳香族ジオール、芳香族ジカルボン酸、及び/又は、芳
香族ヒドロキシカルボン酸を適宜組み合わせて得られる
樹脂から成る。これらの中でも、p-ヒドロキシ安息香酸
と2-ヒドロキシナフタレン−6-カルボン酸とのポリエス
テル共重合体は紡糸性および耐熱性のバランスに優れて
いるので、好適に使用することができ、p−ヒドロキシ
安息香酸とテレフタル酸と4,4'−ヒドロキシフェニルと
のポリエステル共重合体は耐熱性に優れているために、
好適に使用できる。また、上記の液晶ポリエステル不織
布を、プラズマ処理や、カレンダー処理されたものや、
スパンコールのものを適宜使用しうる。
The liquid crystal polyester non-woven fabric is a non-woven fabric using a liquid crystal polyester fiber obtained by spinning a liquid crystal polyester resin. Further, the liquid crystal polyester resin is a polymer capable of forming an anisotropic molten phase. The liquid crystal polyester fiber is not particularly limited, but a fiber made of wholly aromatic polyester (that is, polyester whose main chain is composed of repeating units of aromatic rings) resin is preferable. Therefore,
A resin obtained by appropriately combining an aromatic diol, an aromatic dicarboxylic acid, and / or an aromatic hydroxycarboxylic acid. Among these, the polyester copolymer of p-hydroxybenzoic acid and 2-hydroxynaphthalene-6-carboxylic acid has excellent balance of spinnability and heat resistance, and therefore can be preferably used, and p-hydroxy Because the polyester copolymer of benzoic acid, terephthalic acid, and 4,4′-hydroxyphenyl has excellent heat resistance,
It can be preferably used. Further, the above liquid crystal polyester non-woven fabric, plasma-treated or calendered,
Sequins may be used as appropriate.

【0010】液晶ポリエステル不織布への上記の熱硬化
性樹脂組成物の溶液または、液状無溶剤状のものを公知
の方法で含浸、乾燥しうる。この時の樹脂量は、40〜70
wt%、成形厚は、0.03〜0.25mmが好適である。
The liquid crystal polyester nonwoven fabric may be impregnated with a solution of the above-mentioned thermosetting resin composition or a liquid solventless one by a known method and dried. The amount of resin at this time is 40 to 70
The wt% and the molding thickness are preferably 0.03 to 0.25 mm.

【0011】レーザー光での孔あけは、レーザーは、炭
酸ガスレーザー、エキシマレーザーが使用しうるが、好
適には、炭酸ガスレーザーである。炭酸ガスレーザーの
照射条件は、レーザー光の照射フルエンス(エネルギー
密度)を表す、M値(縮小率)は、5〜20、好適には、
8〜14である。また、パルス数は、除去する電気絶縁層
の厚さと照射フルエンスにより一意に決められる。
For the laser-drilling, a carbon dioxide gas laser or an excimer laser can be used as the laser, but a carbon dioxide gas laser is preferred. The carbon dioxide gas laser irradiation conditions represent the irradiation fluence (energy density) of the laser light, and the M value (reduction ratio) is 5 to 20, preferably,
8-14. The number of pulses is uniquely determined by the thickness of the electrical insulating layer to be removed and the irradiation fluence.

【0012】本発明により、最外電気絶縁層にレーザー
光により超小径孔あけが可能であるために、ブラインド
ビアホールを高密度に配置でき、高耐熱、高耐湿、高絶
縁性、低誘電率、耐薬品性に優れたプラスチック半導体
パッケージを供するものである。また、必要に応じ、ド
リル孔あけによるスルーホール孔を形成する事も可能で
ある。
According to the present invention, since the outermost electric insulating layer can be drilled with a laser beam having a very small diameter, blind via holes can be arranged at a high density, and high heat resistance, high humidity resistance, high insulation property, low dielectric constant, A plastic semiconductor package having excellent chemical resistance is provided. In addition, it is possible to form a through hole by drilling a hole, if necessary.

【0013】[0013]

【実施例】本発明の具体的な内容を以下に説明するが、
これらは本発明の範囲を限定するものではない。尚、実
施例の「部」は特に断らない限り重量基準である。 実施例1 熱硬化性樹脂として、2,2−ビス(4−シアネートフ
ェニル)プロパン540部とビス(4−マレイミドフェニ
ル)メタン60部とを150 ℃、130 分間予備反応させ、こ
れをメチルエチルケトンとN,N−ジメチルホルムアミ
ドとの混合溶剤に溶解した。これに、ビスフェノールA
型エポキシ樹脂(商品名;エピコート1001、油化シェル
エポキシ株式会社製、エポキシ等量450 〜500 )600 部
とオクチル酸亜鉛0.1 部とを溶解してワニスを得た。
EXAMPLES The concrete contents of the present invention will be described below.
They do not limit the scope of the invention. The "parts" in the examples are by weight unless otherwise specified. Example 1 As a thermosetting resin, 540 parts of 2,2-bis (4-cyanatephenyl) propane and 60 parts of bis (4-maleimidophenyl) methane were pre-reacted at 150 ° C. for 130 minutes, and this was reacted with methyl ethyl ketone and N 2. , N-dimethylformamide was dissolved in a mixed solvent. Bisphenol A
A varnish was obtained by dissolving 600 parts of a type epoxy resin (trade name; Epicoat 1001, manufactured by Yuka Shell Epoxy Co., Ltd., epoxy equivalent: 450 to 500) and 0.1 part of zinc octylate.

【0014】厚み0.1mm の液晶ポリエステル不織布(p
−ヒドロキシ安息香酸と2−ヒドロキシナフタレン−6
−カルボン酸とからなる)に上記ワニスを含浸、乾燥し
てプリプレグを得た。上記で得たプリプレグの両面に18
μmの電解銅箔を重ねた構成として、圧力 20kgf/cm2
温度 180℃、2時間の条件で積層成形し、絶縁層厚み0.
1mm の両面銅張積層板を得た。
Liquid crystal polyester non-woven fabric with a thickness of 0.1 mm (p
-Hydroxybenzoic acid and 2-hydroxynaphthalene-6
-Comprising carboxylic acid) was impregnated with the above varnish and dried to obtain a prepreg. 18 on both sides of the prepreg obtained above
Pressure of 20kgf / cm 2 ,
Insulation layer thickness 0.
A 1 mm double-sided copper clad laminate was obtained.

【0015】得られた両面銅張積層板の片面をレーザー
超小径(100 μm)孔あけ用の位置の銅箔を除去した。
炭酸ガスレーザーをもちいて未貫通孔を加工した。得ら
れた銅張積層板をメッキして、表裏導通した後、導体回
路およびソルダーボール用パッドを形成し、プリント板
化した。プリント板上に、エポキシ系Agペースト(Ab
lestick 社製 965−1L)を用いてシリコンチップ(10mm
×10mm)を接着後、金線ワイヤボンディングにより半導
体端子と回路導体を接続し、エポキシ系封止コンパウン
ドで封止し、疑似パッケージを作製した。該疑似パッケ
ージを40℃、85%RH、48時間で吸湿処理後、260 ℃、
5秒間はんだに浸漬した。
On one side of the obtained double-sided copper-clad laminate, the copper foil at the position for laser ultra-small diameter (100 μm) drilling was removed.
The unpenetrated holes were processed using a carbon dioxide laser. The obtained copper-clad laminate was plated to conduct electricity on the front and back sides, and then a conductor circuit and pads for solder balls were formed into printed boards. Epoxy Ag paste (Ab
Silicon chip (10mm) using lestick 965-1L
After bonding 10 mm), the semiconductor terminal and the circuit conductor were connected by gold wire wire bonding and sealed with an epoxy-based encapsulation compound to produce a pseudo package. After the moisture absorption treatment of the pseudo package at 40 ° C, 85% RH for 48 hours, 260 ° C,
Immersed in solder for 5 seconds.

【0016】実施例2 実施例1において、4層銅張積層板を用い、最外電気絶
縁層の両面に、炭酸ガスレーザーを用いて、未貫通孔を
加工した以外は、同様とした。
Example 2 The same procedure as in Example 1 was carried out except that a 4-layer copper clad laminate was used and carbon dioxide gas lasers were used on both sides of the outermost electrical insulating layer to form unpenetrated holes.

【0017】比較例1 実施例1において、アラミド繊維(商品名:テクノー
ラ;帝人社製)を用いる以外は同様とした。
Comparative Example 1 The same procedure as in Example 1 was carried out except that aramid fiber (trade name: Technora; manufactured by Teijin Ltd.) was used.

【0018】比較例2 実施例2において、アラミド繊維(商品名:テクノー
ラ;帝人社製)を用いる以外は同様とした。以上の結果
を表1に示した。
Comparative Example 2 The same procedure as in Example 2 was carried out except that aramid fiber (trade name: Technora; manufactured by Teijin Ltd.) was used. The above results are shown in Table 1.

【0019】[0019]

【表1】 使用基材の 熱ショック時の 種類 クラック発生数/テスト数 実施例1 液晶ポリエステル不織布 0/10 実施例2 同上 0/10 比較例1 アラミド繊維 8/10比較例2 同上 8/10 Table 1 Types of base materials used during heat shock Number of cracks / number of tests Example 1 Liquid crystal polyester non-woven fabric 0/10 Example 2 Same as above 0/10 Comparative example 1 Aramid fiber 8/10 Comparative example 2 Same as above 8/10

【0020】[0020]

【発明の効果】以上、発明の詳細な説明、実施例、比較
例からも明らかなように、本発明の半導体キャリアーお
よびプラスチック半導体パッケージによれば、全芳香族
液晶ポリエステル不織布にシアネート樹脂組成物を含
浸、硬化した電気絶縁層を用いる事により、耐熱性、耐
湿性、絶縁性、低誘電率、耐薬品性に優れ、最外電気絶
縁層にレーザー光による超小径孔加工ができることよ
り、高密度化が可能な、半導体キャリアーおよび、プラ
スチック半導体パッケージの製造が可能であり、その意
義は極めて高いものである。
As is apparent from the detailed description of the invention, Examples and Comparative Examples, according to the semiconductor carrier and the plastic semiconductor package of the present invention, the wholly aromatic liquid crystal polyester nonwoven fabric is provided with the cyanate resin composition. By using the impregnated and hardened electrical insulation layer, it has excellent heat resistance, moisture resistance, insulation, low dielectric constant and chemical resistance, and the outermost electrical insulation layer can be processed with ultra-small diameter holes by laser light, resulting in high density. It is possible to manufacture a semiconductor carrier and a plastic semiconductor package that can be realized, and the significance thereof is extremely high.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体キャリアーを模式的に示した断
面図である。
FIG. 1 is a sectional view schematically showing a semiconductor carrier of the present invention.

【図2】図1を上側からみた様子を示した模式図であ
る。
FIG. 2 is a schematic diagram showing a state where FIG. 1 is viewed from above.

【図3】図1を下側からみた様子を示した模式図であ
る。
FIG. 3 is a schematic diagram showing a state where FIG. 1 is viewed from the lower side.

【図4】本発明の3層銅張積層板半導体キャリアーを模
式的に示した断面図である。
FIG. 4 is a sectional view schematically showing a three-layer copper-clad laminate semiconductor carrier of the present invention.

【図5】図4を上側(第1層)からみた様子を示した模
式図である。
FIG. 5 is a schematic diagram showing a state of FIG. 4 viewed from the upper side (first layer).

【図6】図4の第2層を示した模式図である。FIG. 6 is a schematic view showing a second layer of FIG.

【図7】図4を下側(第3層)からみた様子を示した模
式図である。
FIG. 7 is a schematic diagram showing a state where FIG. 4 is viewed from the lower side (third layer).

【符号の説明】[Explanation of symbols]

1 封止コンパウンド 2 ワイヤー 3 シリコンチップ 4 スルーホール 5 ソルダーボール用パッド 6 ソルダーボール 7 ブラインドビアホール 1 Sealing compound 2 Wire 3 Silicon chip 4 Through hole 5 Solder ball pad 6 Solder ball 7 Blind via hole

───────────────────────────────────────────────────── フロントページの続き (72)発明者 岳 杜夫 東京都千代田区丸の内二丁目5番2号 三 菱瓦斯化学株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Morio Gaku 2-5-2 Marunouchi, Chiyoda-ku, Tokyo Sanryo Gas Chemical Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 銅張積層板に導体回路を形成し、片面に
半導体チップを搭載し、反対面に孔のあいていない銅箔
で作ったパッド部にはんだ球を設けてなり、半導体チッ
プ端子と該パッド銅箔が導通してなる半導体キャリアー
であって、導体回路および銅箔が、全芳香族液晶ポリエ
ステル不織布にシアネート樹脂組成物の熱硬化性樹脂を
含浸、硬化した電気絶縁層に接着してなる半導体キャリ
アー。
1. A semiconductor chip terminal comprising a conductor circuit formed on a copper clad laminate, a semiconductor chip mounted on one surface, and a solder ball provided on a pad portion made of copper foil having no holes on the opposite surface. A semiconductor carrier in which the pad copper foil and the copper foil are electrically connected to each other, wherein the conductor circuit and the copper foil impregnate a wholly aromatic liquid crystal polyester nonwoven fabric with a thermosetting resin of a cyanate resin composition, and adhere the cured electrical insulating layer. A semiconductor carrier.
【請求項2】 請求項1における銅張積層板が3層以上
の多層銅張積層板であって、少なくとも多層銅張積層板
の最外層の片面が全芳香族液晶ポリエステル不織布にシ
アネート樹脂組成物の熱硬化性樹脂を含浸、硬化した電
気絶縁層を有するプラスチック半導体キャリアー。
2. The copper-clad laminate according to claim 1, wherein the copper-clad laminate has three or more layers, and at least one outermost layer of the multilayer copper-clad laminate is a wholly aromatic liquid crystal polyester non-woven fabric and a cyanate resin composition. A plastic semiconductor carrier having an electric insulating layer which is impregnated with and cured by the thermosetting resin.
【請求項3】 請求項1、2における最外層電気絶縁層
をレーザー光で除去した小径孔に銅メッキにより、電気
絶縁層と反対面に形成された導体回路と接続されている
ことを特徴とする半導体キャリアー。
3. The small-diameter hole formed by removing the outermost electrical insulation layer with a laser beam in claim 1, is connected to a conductor circuit formed on the surface opposite to the electrical insulation layer by copper plating. Semiconductor carrier to do.
JP7101938A 1995-04-26 1995-04-26 Semiconductor carrier Pending JPH08298298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7101938A JPH08298298A (en) 1995-04-26 1995-04-26 Semiconductor carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7101938A JPH08298298A (en) 1995-04-26 1995-04-26 Semiconductor carrier

Publications (1)

Publication Number Publication Date
JPH08298298A true JPH08298298A (en) 1996-11-12

Family

ID=14313854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7101938A Pending JPH08298298A (en) 1995-04-26 1995-04-26 Semiconductor carrier

Country Status (1)

Country Link
JP (1) JPH08298298A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998040914A1 (en) * 1997-03-13 1998-09-17 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
EP1659841A2 (en) * 1998-07-08 2006-05-24 Ibiden Co., Ltd. Printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998040914A1 (en) * 1997-03-13 1998-09-17 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7339118B1 (en) 1997-03-13 2008-03-04 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7612295B2 (en) 1997-03-13 2009-11-03 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
EP1659841A2 (en) * 1998-07-08 2006-05-24 Ibiden Co., Ltd. Printed circuit board
EP1659841A3 (en) * 1998-07-08 2009-02-25 Ibiden Co., Ltd. Printed circuit board

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