JPH08274358A - Iii-v compound semiconductor solar cell - Google Patents

Abstract

PURPOSE: To prevent a drop in the shunt resistance of a p-n junction diode by a method wherein a mesa etched part is formed so as to reach a first compound semiconductor layer and a second compound semiconductor layer from the main surface on one side of a III-V compound semiconductor solar cell and an antireflection coating layer is not formed on the mesa etched part. CONSTITUTION: A mesa etching operation 28 is executed to the p-n junction part on the surface end part of a solar cell, and an antireflection coating layer composed of a ZnS film 9 and an MgF2 film 10 is formed in a part where the mesa etched part 28 and an upper-part ohmic electrode layer 7 are not formed. Since the antireflection coating film layer composed of the ZnS film and the like is not formed in the part where the mesa etching operation has been executed in the p-n junction part between an emitter and a base, it is possible to prevent a drop in the resistance value of the parasitic resistance of a p-n junction diode or to prevent the generation of a leakage current via the ZnS film 9, and a curve factor as a parameter to decide the characteristic of the solar cell is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a solar cell, which is a semiconductor element for converting solar energy into electric energy, and particularly to a III-V intergroup compound semiconductor mixture devised to enhance conversion efficiency. It relates to the structure of solar cells using crystals.

[0002]

2. Description of the Related Art III--comprising Group III and V elements
Various solar cells using inter-group V compound semiconductors (hereinafter referred to as III-V group compound semiconductors) have been developed.
Here, as an example of those conventional techniques, a GaAs solar cell having a configuration as shown in FIG. 3 will be described. In FIG. 3, a p-type GaAs base layer 2, an n-type GaAs emitter layer 3, an n-type InGaP window layer 4, and a GaAs contact layer 5 are sequentially formed on a p-type GaAs substrate 1 to form a p-type Ga layer.
Ohmic electrodes 6 and ohmic electrodes 7 are formed for As and n-type GaAs, respectively. Further, the pn junction on the side surface of the solar cell is subjected to etching treatment to form a so-called mesa etching portion 28, and the ZnS film 9 and MgF ₂ which are antireflection films are formed on the entire surface.
The film 10 is formed.

In a pn junction compound semiconductor solar cell composed of an n-type GaAs emitter layer 3 and a p-type GaAs base layer 2 as shown in FIG. 3, the n-type GaAs emitter layer 3 is on the light incident side, and the p-type layer below it is the p-type. GaAs base layer 2
The photons absorbed at generate a pair of holes-electrons, of which electrons, which are minority carriers, move by diffusion and reach the depletion layer at the pn junction interface. It flows into 3 and becomes a photocurrent.

[0004]

However, in the structure as shown in FIG. 3, that is, in the portion where the mesa etching is performed, Zn is formed.
In the structure in which the S film is formed, the insulation property of the ZnS film is not perfect, so that the parallel resistance (shunt resistance) of the pn junction diode between the p-type GaAs base layer 2 and the n-type GaAs emitter layer 3 decreases, and the solar cell There is a problem that the fill factor (fill factor; called FF), which is a parameter that determines the characteristics of, decreases.

The present invention eliminates the above-mentioned drawbacks and prevents a decrease in the shunt resistance (parallel resistance) of a pn junction diode, which is the main operating region of a solar cell, and makes it possible to achieve high conversion efficiency in a III-V group solar cell. Aim to get.

[0006]

In order to solve the above-mentioned problems, according to the present invention, as shown in FIG. 1, a first compound semiconductor layer 2 serving as a first conductivity type base layer and a compound semiconductor layer 2 in contact with the first compound semiconductor layer 2 are provided. And a second ohmic electrode 7 formed on the compound semiconductor layer 3 and a second compound semiconductor layer 3 serving as a second conductivity type emitter layer formed on the upper surface of the compound semiconductor layer 3 and a lower portion of the compound semiconductor layer 2. The second ohmic electrode 6 and the antireflection film layers 9 and 10 formed on the compound semiconductor layer 3.
A group III-V compound semiconductor solar cell comprising at least one of the first and second compound semiconductor layers 2, 3 from one main surface of the group III-V compound semiconductor solar cell.
Is formed, and the antireflection film layers 9 and 10 are not formed on the surface of the mesa etched portion 28. The first ohmic electrode does not have to be formed in contact with the compound semiconductor layer 3, and another second conductivity type semiconductor layer may be inserted therebetween. More specifically, according to the present invention, as shown in FIG. 1, a first conductive type compound semiconductor substrate 1 and a base layer 2 formed on the compound semiconductor substrate 1 and formed of a first conductive type compound semiconductor layer.
An emitter layer 3 made of a second conductivity type compound semiconductor layer formed on the base layer 2, and a window layer 4 made of a second conductivity type compound semiconductor layer formed on the emitter layer 3.
A contact layer 5 formed of a second conductivity type compound semiconductor layer on the window layer 4, a first ohmic electrode 7 formed on the contact layer 5, and a contact layer 5 formed on the bottom of the compound semiconductor substrate 1. The formed second ohmic electrode 6, the mesa-etched portion 28 formed on at least the window layer 4, the emitter layer 3 and the base layer 2 so as to be continuous with these layers 4, 3, 2 and the upper portion of the window layer 4. A III-V compound semiconductor solar cell comprising at least an antireflection film formed only on a predetermined portion.

Preferably, these compound semiconductor layers 1,
2, ..., 5 are semiconductor layers of compounds made of any one of binary, ternary, and quaternary III-V group compound semiconductors. InGaP is a typical ternary III-V compound semiconductor, and AlInGaP is a typical quaternary III-V compound semiconductor.

Preferably, the antireflection film is the ZnS layer 9
It is to include. More preferably, the antireflection film is ZnS
That is, the layer 9 and the MgF ₂ layer 10 formed on the layer 9.

[0009]

With the above structure, the pn between the emitter and the base is obtained.
Since the antireflection film such as the ZnS film is not formed on the mesa-etched portion of the junction, the resistance value of the parasitic resistance (parallel resistance) of the pn junction diode decreases or the ZnS
The generation of leakage current through the film is prevented, and the fill factor, which is a parameter that determines the characteristics of the solar cell, is improved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the (10
0) surface with an impurity density of 1 × 10 ¹⁹ cm ^{−3 on} a Zn-doped p ⁺ GaAs substrate 1 having a thickness of 1.0 to 2.5 μm,
P-type GaAs base layer 2 having an impurity density of 2 to 3 × 10 ¹⁷ cm ⁻³ ; n having an thickness of 50 nm and an impurity density of 3 × 10 ¹⁸ cm ^−3
+ GaAs emitter layer 3; thickness 30 nm, impurity density 2
An n ⁺ In _0.5 Ga _0.5 P window layer 4 of × 10 ¹⁸ cm ^-3 is formed in this order. n ⁺ In _0.5 Ga _0.5 P Window layer 4 has a thickness of 0.3 μ for ohmic contact on a part of its upper portion.
m, n ⁺ GaAs layer 5 and an Au-Ge / Ni / Au layer having an impurity density of 5 × 10 ¹⁸ cm ^-3 and a thickness of 1 μm thereon.
An upper ohmic electrode layer 7 made of an Au plated layer of m is formed.

In FIG. 1, the surface end (side surface) of the solar cell is shown.
The mesa etching 28 is applied to the pn junction of the above, and the antireflection film formed of the ZnS film 9 having a thickness of 55 nm and the MgF ₂ film 10 having a thickness of 95 nm is formed on the mesa etched portion 28 and the portion where the upper ohmic electrode layer 7 is not formed. A film layer is formed. A lower ohmic electrode layer 6 made of an Au plated layer having a thickness of 1 μm is formed on the back surface of the p ⁺ GaAs substrate 1. Zn is a typical dopant for the p-type GaAs base layer, and n ⁺ GaAs emitter layer 3, n ⁺ In _0.5 Ga _0.5 P window layer 4, and n ⁺ GaAs are used.
The dopant for layer 5 is typically Si, but other dopants may be used.

Although not shown in FIG. 1, an oxide film (SiO ₂ ) and a nitride film (Si) are formed on the surface of the mesa etching portion 28.
₃ N ₄ ) or a passivation film such as a polyimide film may be formed. The formation of the passivation film protects the pn junction and enables more stable operation with respect to humidity (water).

Table 1 shows an open-circuit voltage v of the solar cell according to the embodiment of the present invention shown in FIG.
voltage) V _oc , short-circuit current (short-circ)
The unit current I _sc , fill factor FF, and conversion efficiency E _ff are compared with the solar cell in which the antireflection coating layers 9 and 10 are formed in the mesa etching portion 28 in the related art as shown in FIG. It has been shown. The conventional solar cell in Table 1 has the same structure as that of the embodiment of the present invention except for the antireflection film of the mesa etching portion 28.

[0014]

[Table 1] It can be seen from Table 1 that according to the present invention, higher fill factor FF and higher efficiency E _ff can be obtained as compared with the conventional technique.

The solar cell shown in the embodiment of the present invention can be manufactured by the manufacturing method shown in FIG.

(A) First, as shown in FIG. 2 (a), metal organic chemical vapor deposition (MOCVD), CBE (Chemi)
cal beam epitaxy method, MBE (Mo
regular Beam Epitaxy) method, AL
E (Atomic Layer Epitaxy) method or MLE (Molecular Layer Ep)
p) on the p ⁺ GaAs substrate 1 by using the
Type GaAs base layer 2, n ⁺ GaAs emitter layer 3, n
⁺ In _0.5 Ga _0.5 P window layer 4 and n ⁺ GaAs contact layer 5 are continuously epitaxially grown in multiple layers.

For example, MOCVD can be performed by either atmospheric pressure MOCVD or reduced pressure MOCVD, but it is preferable that the reduced pressure MOCVD is maintained at, for example, 6.7 to 10 kPa.
Method, more preferably vertical decompression MOCVD method. As a group III source gas, triethylgallium (TEG), trimethylindium (TMI), etc.
Phosphine (PH ₃ ), arsine (AsH ₃ ) or the like is used as the group source gas. Or tertiary butyl phosphine ((C ₄ H ₉ ) PH ₂ ; TBP),
Tertiary butyl arsine ((C ₄ H ₉ ) AsH
₂ ; TBA) or the like may be used. As the n-type dopant gas, monosilane (SiH ₄ ) or disilane (Si
₂ H ₆ ), diethyl selenium (DESe), diethyl tellurium (DETe) or the like may be used, but monosilane is preferable. Diethyl zinc (DEZn) or trimethylgallium (TM) is used as the p-type dopant gas.
G) may be used. The raw material gas and the dopant gas are 6.7 kP by using a mass flow controller or the like.
It is introduced into a reaction tube controlled to a reduced pressure of a to 10 kPa. The ratio of the group V source gas to the group III source gas, the so-called V / III ratio, may be about 120 to 170, for example. The substrate temperature during growth is, for example, 650 ° C. to 700 ° C.
In order to obtain a high FF value as shown in Table 1, the substrate temperature for continuous epitaxial growth of the P-type GaAs base layer 2, n ⁺ GaAs emitter layer 3, etc. is 70.
0 ° C is preferred.

(B) Next, the wafer having a multilayer structure thus continuously epitaxially grown is taken out from the reaction tube, a photoresist for lift-off is applied, a predetermined pattern is formed by photolithography, and Au-- Vacuum deposition of Ge / Ni / Au. For example, 10
0 nm Au-Ge (12 wt%), 20 nm Ni,
A 70 nm Au film is formed using the EB vapor deposition method or the like. Then, if the photoresist is removed, the upper ohmic electrode layer 7 having a comb-like stripe shape as shown in FIG.
1 is formed. Although a similar pattern can be obtained by etching with an etchant such as a KI / I ₂ solution by ordinary photolithography without using the lift-off method, the lift-off method is simpler. Then, the electrode is sintered at 360 to 450 ° C. in an H ₂ atmosphere or an inert gas atmosphere such as N ₂ . Sintering at 360 ° C. for about 2 seconds is preferable.

(C) Next, the surface of the epitaxial growth layer is covered with a photoresist or the like, and the back surface of the p ⁺ GaAs substrate 1 is etched by about 6 μm with an NH ₄ OH + H ₂ O ₂ + H ₂ O (1: 1: 10) solution or the like. Au plating of the lower ohmic electrode layer 6 of about 1 μm is performed on the surface. Subsequently, the Au-Ge / Ni / Au film 71 on the surface of the epitaxial growth layer 71
A window is opened only by using photolithography, the other part is covered with a photoresist and an Au film 72 of about 1 μm is plated, and the upper ohmic electrode layer 7 having the shape shown in FIG. 2C is formed.
Get. If the electroplating method is used, this photolithography can be omitted. The step of forming the upper metal electrode layer 71 shown in FIG. 2B may be performed after the step of forming the lower ohmic electrode layer 6.

(D) Next, a desired area, for example, 10 mm
The main area and the back surface of the device including the light receiving surface of × 20 mm and the upper ohmic electrode layer 7 are covered with a photoresist, and a predetermined portion of the epitaxial growth layer is formed with a width of about 30 μm to 50 μm as shown in FIG. The mesa 28 is formed by etching. Eventually, a large number of 10 mm × 20 mm islands will be surrounded by the mesa region. For mesa etching, an HCl-based etchant and ammonia / hydrogen peroxide (H ₂ O ₂ ) may be used. It may be a sulfuric acid type etchant, or a tartaric acid type or a bromine type.

Then, using the pattern of the upper metal electrode layer 7 as a mask, n ⁺ GaA under the upper ohmic electrode layer 7 is formed.
Only the s layer 5 is left, and the other parts of the n ⁺ GaAs layer 5 are removed. This etching is NH ₄ OH + H ₂ O ₂ + H ₂
Selective etching of GaAs may be performed with O (1: 1: 10) for about 30 seconds.

(E) Next, using the lift-off method again, Z
The antireflection film 6 including the nS film 61 and the MgF ₂ film 62 is formed. That is, the upper ohmic electrode layer 7 and the mesa etching portion 28 are covered with photoresist by photolithography, and then the ZnS film 9 is deposited to about 55 to 65 nm by vacuum deposition or sputtering, and then the MgF ₂ film 10 is deposited to 95 to 120 nm by vacuum deposition. By forming and then removing the photoresist, the shape shown in FIG.

(F) Next, although not shown, the width is 30 μm.
A scribe line is drawn in the center of the mesa line of m to 50 μm, and a cell of 10 × 20 mm is cut out by cleavage to complete. Instead of cleaving, it may be directly cut out by dicing or the like. If the p ⁺ GaAs substrate 1 is a 2-inch wafer, 6 cells of 10 mm × 20 mm can be cut out. The cell size is an example, and may be set as needed.
For example, if InGaP is grown on a Si substrate, a large-area solar cell having a diameter of 4 inches to 8 inches can be obtained at a low price.

In the above embodiments, p-type GaA is used.
Although the solar cell having the pn junction of the s layer 2 and the n ⁺ GaAs emitter layer 3 has been described, p-type In _0.5 Ga _0.5 P
III-V compound semiconductor solar cell of three elements having a base layer and an n ⁺ In _0.5 Ga _0.5 P emitter layer, or A
III-V of 4 elements using _0.06 Ga _0.45 In _0.49 P, etc.
Of course, it can be applied to group compound semiconductor solar cells. Also, 2-3 solar cells as shown in FIG. 1,
Even if it is applied to a stacked type solar cell connected in series (tandem), the conversion efficiency can be improved. Further, if a back surface field layer (BSF layer) is formed between the p-type GaAs base layer and the p ⁺ GaAs substrate in the structure of FIG. B
As the SF layer, 1) a III-V group compound semiconductor that is made of the same material as the base layer and has a high doping concentration to serve as a barrier against minority carriers, or 2) another semiconductor material that is higher than the base layer material A large forbidden band and also a barrier to minority carriers II
An I-V group compound semiconductor may be used.

[0025]

As described above, the resistance value of the parallel resistance (shunt resistance) of the pn junction which constitutes the solar cell according to the present invention is prevented from lowering, and the good fill factor (FF) is obtained.
And a III-V group compound semiconductor solar cell with high conversion efficiency can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a cross section of a GaAs solar cell according to an example of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a GaAs solar cell according to an example of the present invention.

FIG. 3 is a cross-sectional view of a conventional GaAs solar cell.

[Explanation of symbols]

1 p ⁺ GaAs substrate 2 p-type GaAs base layer 3 n ⁺ GaAs emitter layer 4 n ⁺ InGaP window layer 5 n ⁺ GaAs contact layer 6 lower ohmic electrode 7 upper ohmic electrode 9 ZnS film 10 MgF ₂ film 28 mesa etching part

Claims (5)

[Claims] 1. A first compound semiconductor layer serving as a first conductivity type base layer, and a second compound serving as a second conductivity type emitter layer formed on and in contact with the first compound semiconductor layer. A semiconductor layer; a first ohmic electrode formed on the second compound semiconductor layer; a second ohmic electrode formed on the lower side of the first compound semiconductor layer; and a first compound semiconductor A III-V compound semiconductor solar cell comprising at least an antireflection film layer formed on the upper part of the layer, wherein the first and second compounds are formed from one main surface of the III-V compound semiconductor solar cell. A mesa-etched portion reaching the semiconductor layer is formed, and an antireflection film layer is not formed on the surface of the mesa-etched portion III
-Group V compound semiconductor solar cell. 2. A first-conductivity-type compound semiconductor substrate, a base layer formed of a first-conductivity-type compound semiconductor layer on the compound semiconductor substrate, and a first layer formed on the base layer. An emitter layer made of a two-conductivity type compound semiconductor layer, a window layer made of a second-conductivity type compound semiconductor layer formed on the emitter layer, and a second-conductivity type compound semiconductor layer formed on the window layer. And a first ohmic electrode formed on the contact layer, a second ohmic electrode formed on the lower portion of the compound semiconductor substrate, and at least the window layer, the emitter layer and the base layer. A III-V group compound semiconductor solar cell comprising at least a formed mesa etching portion and an antireflection film formed only on a predetermined portion above the window layer. 3. The compound semiconductor layer according to claim 1, wherein the compound semiconductor layer is any compound semiconductor layer selected from binary, ternary, and quaternary III-V group compound semiconductors. III-V compound semiconductor solar cell of. 4. The III-V compound semiconductor solar cell according to claim 1, wherein the antireflection film includes a ZnS layer. 5. The III-V compound semiconductor solar cell according to claim 4, wherein the antireflection film is a ZnS layer and MgF ₂ formed on the ZnS layer.