JPH08265156A - Semiconductor integrated circuit device and control system - Google Patents

Abstract

PURPOSE: To improve the processing capability by storing A/D conversion result to a 1st data register of plural data registers, transferring the stored data to a 2nd data register and incorporating the result of A/D conversion. CONSTITUTION: A control logic conducts data input-output with control registers ADCSR, ADCR and data registers ADDRA-ADDRH via a bus interface. As soon as the result of A/D conversion is stored in the register ADDRA, the conversion result having been stored previously is transferred to other data register according to the data stored in the register ADCR. That is, any of two-stage operations as AINO→ADDRA→ADDRB and two-sets of two-stage operations as AINO→ADDRA→ADDRC and AINI→ADDRB→ADDRD and one-set of 4-stage operations as AINO→ADDRA→ADDRB→ADDRC→ADDRD is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a control system, and more particularly to a technique effective for use in a single-chip microcomputer incorporating an analog / digital conversion circuit and a control system using the same. is there.

[0002]

2. Description of the Related Art A single-chip microcomputer mainly includes a central processing unit (CPU) as described in "LSI Handbook", pages 540 to 541, issued by Ohmsha on November 30, 1984. On a semiconductor substrate, functional blocks such as a ROM (read only memory) for holding programs, a RAM (random access memory) for holding data, and an input / output circuit for inputting / outputting data It is formed in. Such an input / output circuit also includes an A / D (analog / digital) conversion circuit. An example of a single-chip microcomputer incorporating an A / D conversion circuit is "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993.

As examples of high-speed A / D conversion circuits, there are JP-A-60-124125 and JP-A-2-126726.
There is a plurality of sampling and holding circuits, and a common A / D conversion circuit and a pipeline (conversion of the result of the previous sampling and the next sampling are performed at the same time, in other words, the sampling circuits operate alternately. )
By doing so, speeding up is realized. As an A / D conversion method of the sub-range method, there is, for example, Japanese Patent Laid-Open No. 4-176215, and partial flash conversion is performed to realize high speed operation without increasing the circuit scale.

[0004]

The plurality of analog input channels provided in the A / D conversion circuit incorporated in the single-chip microcomputer differ depending on the system in which they are used. For example, when controlling a motor, a value obtained by converting the motor drive current into a voltage is input. If the control of the motor is three-phase, the analog input is 3 to 6 channels. If the current value can be detected in only two phases, two channels can be used. In the above system, it is necessary to input the ambient temperature and the temperature of the motor in analog form. If the motor is driven by a built-in timer output, it is desirable to measure the drive current in a short time from the desired timing of the timer. When the current value of the third phase is obtained by calculation, it is desirable that the current values of the two phases to be measured be analog values at the same time, that is, simultaneous sampling be performed. By accelerating A / D conversion operation and obtaining multiple analog inputs at the same time,
A more accurate current value can be obtained, which in turn can improve the accuracy of motor drive control. On the other hand, the detection frequency of the ambient temperature and the temperature of the motor may be low, and the timing may be independent of the drive timing of the motor.

The required resolution is often different depending on the input analog value. For example, the motor drive current described above requires 10-bit resolution, but the ambient temperature is 8
Bit resolution is often sufficient. A / D above
In the example of the single-chip microcomputer having the built-in conversion circuit, the conversion result is in the upper order, so that only the upper byte needs to be read in order to obtain 8-bit resolution. If 10-bit resolution is required, 2 bytes may be read. However, when processing the result of 10-bit A / D conversion with other data of 10 bits, for example, either of them must be shifted by 6 bits. If such data bit shift processing is performed by software, the burden is not always negligible.

It is convenient to be able to select activation by software or activation by an external trigger terminal as the activation factor of the A / D conversion operation. Also, in order to have versatility, it becomes convenient to start even with a timer compare match. For example, when the motor is controlled by the waveform output by the compare match of the timer, it is effective when the drive current of the motor is simultaneously monitored by using the compare match. The conversion mode may be a mode in which conversion is performed only once, a mode in which conversion is repeated, a mode in which conversion is performed in one channel, or a mode in which a plurality of channels are continuously converted.

In the case of having a plurality of input channels, activation factors, and conversion modes, in a system using a microcomputer, these input channels, activation factors, and conversion modes are related to each other. Become. For example, in the above-mentioned example of the motor, the channel value to which the value obtained by converting the motor drive current into the voltage is input is activated by the compare match of the timer, and the input analog signals supplied to each of the plurality of channels are A / D converted. . It is inconvenient to convert a single drive current for determination or to convert it with another activation factor. On the other hand, the channels for inputting the ambient temperature, the temperature of the motor, and the like are subjected to A / D conversion of the input analog signal independently by, for example, software at a timing independent of the driving timing of the motor.

Further, an interrupt is generated at the end of the A / D conversion, so-called data transfer controller DTC.
The conversion result is a memory (Random Access Memory;
RAM). However, in so-called scan mode, A / D of multiple channels
When the conversion is repeated, when the conversion of all the designated channels is completed, an A / D conversion end interrupt is generated and the DTC is activated. On the other hand, the A / D conversion circuit starts conversion from the first channel again. The time from the activation of the DTC to the actual data transfer varies depending on other operating conditions, but in the example of the single chip microcomputer described above, 35 states are required for data transfer. Although the A / D conversion time per channel of the A / D conversion circuit in the single chip microcomputer is 135 states, the data transfer time of the single chip microcomputer remains 35 states and the A / D conversion time is If the data transfer time of the single-chip microcomputer is made faster (more than 35 states), the next conversion operation may end before the conversion result is read by the DTC. For example, the first conversion result of the plurality of channels may be the second conversion result and the other conversion results may be the first conversion result, and the first conversion result of the first channel may be lost.

The high-speed A / D conversion circuit is not considered to be built in a single-chip microcomputer. Its purpose is to convert a single address input continuously and at high speed, and even if there are multiple analog inputs that convert continuously and at high speed, it is not considered to judge many different analog inputs. . Further, in an application field where continuous and high-speed A / D conversion is not required, even if there are a plurality of sampling circuits, this cannot be effectively used. For analog inputs such as single-chip microcomputers, the required resolution differs for each analog input, there are some that require continuous conversion, or only a single conversion is necessary and the pipeline operation becomes meaningless. , Not only can not speed up,
There are various cases such as when the sample and hold circuit is wasted and when the relative values of a plurality of analog inputs are important.

The conversion result by the A / D conversion circuit is the CPU
Must process this and read the conversion result by the data transfer value for temporary saving of the conversion result. Depending on the operating state of the DTC, these CPUs may not always be able to read or process the conversion result. CPU is A /
When reading the conversion result of the D conversion circuit, the single chip microcomputer requires 6 states for instruction execution, and if the conversion operation of the A / D conversion circuit is speeded up, it takes the same time as the read operation of the CPU. Ended up, C
The PU cannot perform any other processing. After that, desired data processing is performed based on the read result. In order to increase the overall speed of the single-chip microcomputer, it is necessary to reduce the load required for these leads and processing. Further, it is desirable that the A / D conversion circuit built in the semiconductor integrated circuit device has low current consumption.

An object of the present invention is to provide a semiconductor integrated circuit device and a control system having a built-in A / D converter which has a simple structure and is suitable for various purposes. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device having a built-in A / D converter, a plurality of data registers for storing the conversion result in the A / D converter are provided, and the plurality of data registers store the A / D conversion result as the first data register. An operation mode for fetching the A / D conversion result after the data held in the first data register is transferred to the second data register when the data is stored in the first data register is provided.
Alternatively, an operation mode is provided in which the first A / D conversion result is stored in the first data register and the second A / D conversion result is stored in the second data register. When the data register is saturated by the A / D conversion result in the above operation mode, the operation of the A / D converter is stopped. Then, when the reading of the data register is completed in the operation mode, the operation of the A / D converter is restarted.

[0013]

According to the above-mentioned means, the conversion results continuously input can be collectively processed without being taken out by the central processing unit or the data transfer unit one by one, so that the substantial processing capability can be improved. Therefore, the processing can be performed while maintaining the mutual relationship. Further, the A / D conversion operation can be performed in accordance with the data processing.

[0014]

1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied. Each circuit block shown in FIG. 1 is made of single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
It is formed on each semiconductor substrate.

The single-chip microcomputer of this embodiment includes a central processing unit CPU, a clock generation circuit CPG, a data transfer controller (data transfer device) DTC, an interrupt controller INT, a read-only memory ROM storing programs and the like. Random access memory RA used for memory, temporary storage, etc.
M, timer A and timer B (ITU), serial communication interface SCI, A / D converter, and input / output ports IOP1 to IOP9 including first to ninth
It is composed of each functional block or functional module of.
Such functional blocks or functional modules are interconnected by an internal bus. The internal bus is the address bus,
In addition to the data bus, it includes a control bus for transmitting a read signal and a write signal, and may further include a bus size signal (WORD) or a system clock. The above-mentioned functional block or functional module is provided with a central processing unit CPU or a data transfer controller DT via an internal bus.
Read / write by C. Although not particularly limited, the bus width of the internal bus consists of 16 bits.

In the single-chip microcomputer of this embodiment, the ground potential Vss, power supply voltage Vcc, analog ground potential AVss, and analog power supply voltage AV are used as power supply terminals.
cc, analog reference voltage Vref, other dedicated control terminals such as reset RES, styby STBY, mode control M
D0, MD1, clock inputs EXTAL, XTAL, etc. are provided.

Each input / output port is also used as an input / output terminal of an address bus, a data bus, a bus control signal or a timer, a serial communication interface SCI, and an A / D converter. That is, the timer, the serial communication interface SCI, and the A / D converter each have an input / output signal and are input / output to / from the outside through a terminal which is also used as an input / output port. For example, the fifth port IOP5, the sixth port IOP6, and the seventh port IOP7 are input / output terminals of the timers A and B (timer B
Output signals include U, V, W and U #, V #, W #, and input signals include TCLKA, TCLKB. ), And the eighth port IOP8 is also used as an input / output terminal of the serial communication interface SCI. The terminals of analog data input AIN0 to AIN7 are
It is also used as port IOP9. External trigger signal AD
TRG and busy signal BUSY are the 8th port IOP
It is also used as 8.

The compare match signal, overflow signal and underflow signal of timer A and timer B are A /
It is given to the A / D converter as a D conversion start trigger. The interrupt signal is output from the A / D converter, timer A, timer B, and serial communication interface SCI, and the interrupt controller INT receives it,
Based on the designation of a predetermined register or the like, the central processing unit C
It controls whether an interrupt request signal is given to the PU or a start request signal is given to the data transfer controller DTC. Such switching is performed by the DTE bit. That is, when an interrupt factor occurs while the DTE bit is set to "1", a start request signal to the data transfer controller DTC is generated, and when the data transfer is performed, the interrupt request is automatically cleared. It On the other hand, when an interrupt factor occurs while the DTE bit is cleared to "0", a start request signal to the central processing unit CPU is generated, the central processing unit CPU performs desired data processing, and desired data processing. Clear the bit indicating the post interrupt factor.

When a predetermined condition is satisfied during data transfer by the data transfer controller DTC, for example, when the transfer counter becomes 0, the corresponding DTE bit is set to "0" without clearing the bit indicating the interrupt factor. It is cleared to generate an interrupt request to the central processing unit CPU. An independent DTE bit and an independent vector are assigned to each interrupt factor.

As the data transfer device, in addition to the data transfer controller DTC as described above, a device such as a direct memory access control device DMAC may be used. As an example of the data transfer controller DTC as described above, one described in "H8 / 532 Hardware Manual" issued by Hitachi, Ltd. in December 1988 can be used. As an example of the direct memory access control device DMAC, one described in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993 can be used.

These data transfer devices (DTC / DMA
C) is "H8 / 3003 Hardware Manual"
Alternatively, as described in Japanese Patent Application No. 4-137954, it is possible to transfer a plurality of units of data by one activation, that is, a so-called block transfer mode. These are a source address register SAR, a destination address register DAR, a block size counter TCRH, a block size holding register TCRL,
It has a block transfer counter BTCR so that data can be transferred in block units.

Timer B (ITU; Integrated Timer Uni)
t) is a timer counter and a compare register (GRA to G
RD) and has timer counters 0 to GRA (register G
Up / down counting is performed with the set value of RA). An underflow signal is generated when the count value becomes 0 by the down count, and a compare match A is generated when the count value matches the set value of the GRA. Further, when the values match the values set in the compare registers GRB to GRD during this, the timer output is changed. Each timer output has a positive phase / negative phase output. Thereby, for example, complementary three-phase PWM (pulse width modulation) outputs can be formed. The complementary 3-phase PWM output is described in the above "H8 / 3003 Hardware Manual".
pp. 374-381, etc. Normal phase /
A counter for setting a non-overlap time between outputs of opposite phases may be added.

FIG. 2 is a block diagram showing an embodiment of an A / D converter mounted on a single chip microcomputer to which the present invention is applied. The A / D converter includes a control logic, a bus interface, a control register ADCSR, ADCR, a data register AD.
DRA to ADDRH, resistance voltage dividing circuit (D / A conversion) for performing 2-bit voltage dividing, 6-bit voltage dividing and 2-bit voltage dividing, analog multiplexer, sample hold / level shift circuits A and B, comparator array (differential amplifier) ) A,
B, a successive approximation register.

Inputs from the outside of the single chip microcomputer include power supplies (Vcc, Vss, AVcc, A
Vss, Vref), analog inputs AIN0 to AIN7, and an external trigger signal ADTRG are supplied to the A / D converter.
As the internal signals of the single-chip microcomputer, a start signal from the timers A and B, an address signal from the address bus, a read signal, a write signal, a bus size signal, and a factor clear signal are given, and internal data is sent via the bus interface. Data is input to and output from the bus. It also outputs an interrupt signal ADI. The interrupt signal ADI is given to the interrupt controller INT and used as an activation signal of the data transfer controller DTC or an interrupt request of the central processing unit CPU.

The control logic is the central processing unit C.
Address signal from the address bus given from PU,
The control register AD is connected to the internal data bus via the bus interface based on the read signal and the write signal.
CSR, ADCR, data registers ADDRA to ADD
Input and output of data with RH. The control logic includes an external trigger signal ADTRG and timers A and B.
The start signal from is input. The control logic controls the analog input operation based on the contents of the control registers ADCSR and ADCR. Then, the control logic outputs the interrupt signal ADI.

The control registers ADCSR and ADCR are read / written from the central processing unit CPU via the internal data bus and the bus interface to instruct the operation of the control logic and display the state of the analog input. That is, the data stored in the control registers ADCSR and ADCR indicate the selection of the analog input terminal (hereinafter referred to as the input channel), the selection of the conversion mode of the A / D converter, and the like. The A / D conversion mode includes a select mode for converting one channel and a group mode for converting a plurality of channels, as will be described later. In addition to this, a single mode for performing one conversion is repeatedly performed for conversion. There is a scan mode to do.

The control register ADCSR is an A / D control / status register, which is a register capable of 8-bit read R or write W, and performs A / D conversion operation control and status display. This register AD
The CRS is initialized to H'00 (initial value) at reset, and its bit configuration is shown in Table 1 below.

[0028]

[Table 1]

ADF of bit 7 is a status flag indicating the end of A / D conversion, and the clear condition is ADF =
After reading the ADF flag in the state of "1", the ADF is
When writing "0" to the flag or in response to an interrupt by the interrupt signal ADI, the data transfer device DTC
Or when the DMAC is activated. The set condition is
In the single mode, the A / D conversion of all the specified channels is completed, and the A / D conversion is completed, and in the scan mode, all the specified channels are converted in one cycle. .

The bit 6 ADIE selects enable or disable of an interrupt (ADI) request due to the end of A / D conversion. If ADIE = "0", the interrupt (ADI) request due to the end of A / D conversion is prohibited, and if ADIE = "1", A
Enable the interrupt (ADI) request due to the completion of / D conversion.

ADST of bit 5 selects start or stop of A / D conversion. Holds "1" during A / D conversion. ADST is set to "1" by the external trigger signal ADTRG supplied from the A / D external trigger input terminal or the trigger signal of the timer. When ADST = "0", A / D conversion is stopped. When ADST = "1", A / D conversion is started in single mode, and when conversion of the specified channel is completed, it is automatically cleared to "0". To be done. A / D in scan mode when ADST = "1"
Start conversion and continue conversion until it is cleared to "0" by software.

CKS of bit 4 is a clock generation circuit C
Clock signal generated from PG (φ or φ / 2)
Is a clock select signal for selecting the cycle of
Set the A / D conversion time. The conversion time is switched while the conversion is stopped. When CKS = “0”, the conversion time becomes 20 states (select the reference clock φ), and C
When KS = “1”, the conversion time is 40 states (reference clock φ / 2 is selected).

GRP of bit 3 is a group mode signal and specifies the selection of the A / D conversion channel to the select mode or the group mode. The setting of the GRP bit is performed while the A / D conversion is stopped. When GRP = "0", the select mode is set, and when GRP = "1", the group mode is set.

Bits 2 to 0 are channel select signals and select an analog input channel together with the GRP bit. The setting of the input channel is performed while the A / D conversion is stopped. When GRP = "0", in the select mode, any one of AIN0 to AIN7 is selected by the combination of the above 3 bits CH2 to CH0. When GRP = "1" and the group mode is 3 bits CH2 to CH0 are H'000, AIN is set.
Only 0 is selected, otherwise AIN0 and bit C above
AIN1 to AIN7 are selected at the same time as AIN0 depending on the combination of H1 and CH2.

The control register ADCR is an A / D control register and is an 8-bit read R or write W.
Is a register capable of performing A / D conversion operation control. This register ADCR is initialized to H'00 (initial value) at reset, and its bit configuration is shown in Table 2 below.

[0036]

[Table 2]

INF of bit 7 is an interval bit and specifies an interval operation. In interval operation, when the BUSY signal is active, a new A / D
Do not start conversion operation. By clearing the ADF flag to "0", the BUSY signal can be activated and a new A / D conversion operation can be started. INF =
“0” is the normal operation, and INF = “1” is the interval operation.

PWR of bit 6 is a power supply bit,
Set the conversion start mode. The conversion start mode includes a high speed conversion mode and a low power consumption mode, which will be described in detail later.

TRGS1, TRGS0 of bits 5-4
Is a timer trigger select bit, and selects permission or prohibition of A / D conversion start by a trigger signal. TRG
The settings of S1 and TRGS0 are set while the A / D conversion is stopped. The following four ways can be selected from the combination of the 2-bit TRGS1 and TRGS0. (1) Only start A / D conversion by software is permitted. (2) Permit start of A / D conversion by timer trigger (timer B). (3) Permit start of A / D conversion by timer trigger (timer A). (4) A / D by external trigger terminal
Allow conversion to start.

The SCAN of bit 3 is in the scan mode and selects the single mode or the scan mode as the A / D conversion operation mode. Details of the single mode and the scan mode will be described later. SCAN =
If "0", the single mode is set, and if SCAN = "1," the scan mode is set.

The DSMP of bit 2 is a simultaneous sampling mode and enables or prohibits the simultaneous sampling operation of two channels. The details of this simultaneous sampling operation will be described later. DSMP = “0” normal sampling operation, and DSMP = “1” simultaneous sampling operation.

BUFE1 and BUFFE0 of bits 1 and 0 are buffer enable, and data register ADDRA
~ Select whether or not to use ADDRD as a buffer register. This buffer operation will be described later.

Data registers ADDRA to ADDRH
Can be read / written from the central processing unit CPU via an internal data bus and a bus interface,
The analog input data, in other words, the A / D conversion result is stored. Although not particularly limited, each of these data registers ADDRA to ADDRH consists of 16 bits, and when the A / D converted data is 10 bits as described later, the lower 8 bits are the lower byte (bits 7 to 0). 2), the upper 2 bits are transferred and held in the upper byte (bits 9 and 8). Bit 1 of upper byte
Although 5 to 10 are not used, "0" is always read when read. In this embodiment, the reading of data is enabled by byte or word selection. That is, the 10-bit resolution A / D conversion output is read in the word mode, and the 8-bit resolution A / D conversion output is in the high-order 8 bits (bit 9 to 9) as the byte mode.
2) is read.

The analog multiplexer includes bits 0 to 2 (CH0 to CH2) of the control register ADCSR and GRP.
Analog inputs AIN0 to AIN0 according to the selection signal output from the control logic based on the data indicated by and
AIN7 is selected and an analog signal corresponding to it is taken in. This analog multiplexer is shown in FIG.
It may be included in the input / output port IOP9.

The sample hold / level shift circuit is
Based on the sampling signal output from the control logic, the analog input signal selected by the analog multiplexer is sampled and held (accumulated). In this embodiment, two sample hold circuits A and B are provided, and independent sampling signals A and B are given to them. Therefore, the sampling signals A and B can be sampled at independent timings or simultaneously.

The level shift circuits A and B level shift the held input signal by the level shift signals A and B. This level shift operation is the first A /
It is performed based on the D conversion result. For example, as will be described later, in the voltage range obtained by dividing the analog input range corresponding to the reference voltage Vref into four equal parts, the held input signal is shifted within the subrange region of Vref / 4 to Vref / 2.

Each of the comparator arrays A and B is composed of five differential amplifier circuits. These comparator arrays A and B compare the input signals held by the sample hold circuits A and B with a plurality of reference voltages (5 lines) formed by the local resistance voltage dividing circuit, and output the comparison result. . That is, the comparison for 2 bits can be performed at the same time. The comparison result of each of the comparator arrays A and B is converted into a binary signal by the control logic and stored in the successive approximation register.

In the first comparison, the top two resistors of the resistance voltage dividing circuit are
Compare with bit. Based on the comparison result, level shift signals A and B are formed respectively, and the level shift circuits A and B shift the input signal held in the sub-range area as described above. The conversion operation after the second time is 1 / 64th by the local voltage dividing circuit (6 bits voltage dividing).
Of the two divided bits are selected through the selector, and the voltage divided by the two divided voltages between the selected divided voltages is supplied to the comparator array A or B. It is done by By repeating such an operation, the conversion operation up to the least significant bit is performed. At the end of the A / D conversion operation, the conversion data held in the control logic (successive approximation register) is transferred to any of the data registers ADDRA to ADDRH.

The resistance voltage dividing circuit (D / A conversion) is, for example, 1
When the 0-bit resolution is used, it is necessary to form a divided voltage divided by 1024 resistors between the reference voltage Vref and the analog ground voltage AVss. If this is done, the number of resistors will increase. Therefore, in this embodiment, the resistors are divided into three voltage dividing circuits of the upper 2 bit voltage division, the 6 bit voltage division and the lower 2 bit voltage division as described above. The number is greatly reduced. In other words, the voltage dividing resistor circuit of this embodiment is composed of the higher-order 2-bit voltage dividing circuit and the 6-bit and 2-bit local voltage dividing circuit. The high-order 2 bit voltage dividing circuit is Vref, 3Vref / 4, Vref
/ 2, Vref / 4 and 0V are formed and supplied to the register shift circuit and the comparator array.

The 6-bit local voltage dividing circuit has the above Vref / 4.
The divided voltage is divided into 1/64 to form 64 divided voltages, and the selector is controlled based on the designation by the contents of the successive approximation register to correspond to 2 bits in order from the higher order. The divided voltage is output. The divided output is further divided by the lower 2 bits to be supplied to the comparator array and used for the A / D conversion operation. The analog voltages AVcc and AVss are used as a power source for the analog section (multiplexer, sample hold circuit, comparator array, etc.).

FIG. 3 shows a basic timing chart for explaining the operation of the A / D converter. The A / D converter according to this embodiment uses one of the internal clock signals φ and φ / 2 selected by the clock generation circuit CPG according to the data stored in bit 4 (CKS) of the control register ADCSR. It operates in synchronization with CLK.
During the period of T1 to T10 of the clock signal CLK, the sampling signal becomes high level and the analog input signal selected by the analog multiplexer is stored in the capacitor of the sample hold circuit. This accumulated input signal is supplied to the comparator array.

The high-order conversion signal output from the control logic becomes high level in synchronization with the period T10 of the clock signal CLK, and the comparison operation with the high-order 2 bits is performed. The comparison result is output in synchronization with the next period T11 of the clock signal CLK. Based on the comparison result of the upper 2 bits, a level shift signal is generated in synchronization with the period T12 of the clock signal CLK and transmitted to the level shift circuit. As a result, the input signal becomes Vref / 4.
The level shift operation is performed so as to enter the sub-range region of -Vref / 2. In addition, the period T of the clock signal CLK
From 12 above, the subrange areas Vref / 4 to Vref / 2 are resistance-divided by the lower 2 bits D / A, and five levels (0, 1/4, 1/2, 3/4,
The reference voltage of 1) is generated.

During the period T13 of the clock signal CLK, the lower conversion signal becomes high level, and the comparison operation of the third and fourth bits is performed. This result is output from the period T13. Based on this result, the select signal is changed to change the output of the local D / A to change the voltage across the lower 2 bits D / A. For example, if the comparison result is 5 Vref / 1
In the range of 6 to 6Vref / 16, 5Vref / 16 to
A voltage of 6Vref / 16 is applied to both ends of the voltage division (D / A) of the lower 2 bits, and a 5 level reference voltage required to divide this into 4 is generated. Period T15 of clock signal CLK
In, the lower conversion signal goes high and the fifth and sixth bits are compared. This result is output from the period T15.

The above operation is repeated, the latch signal becomes high level during the period T20 of the clock signal CLK, and the conversion result shows the data registers ADDRA to ADD.
It is stored in a predetermined register in RH. The conversion end flag ADF is set to "1" according to a predetermined condition.

FIG. 4 shows a voltage distribution diagram for explaining the voltage conversion system of the sub-range of the A / D converter. The analog input range is 0 to Vref, while the subrange region is a region of 1/4 of the analog input range such as Vref / 4 to Vref / 2. In the subrange, the A / D conversion operation with higher resolution is performed. That is, according to the result of the first A / D conversion, if the input signal AIN is in the range of 3Vref / 4 to Vref, the level shift circuit shifts the level to V.
Shift to the region of ref / 4 to Vref / 2. Specifically, the level is shifted so as to be Vref / 2 minutes (subtraction). After that, as shown in the timing chart of FIG. 3, the conversion operation for the remaining 8 bits in the range of this subrange is performed by dividing the conversion by 2 bits in order from the higher order four times.

FIG. 6 shows a circuit diagram of an embodiment of the sample hold / level shift circuit A. The sample-hold / level-shift circuit A is composed of a combination of a CMOS switch such as a P-channel MOSFET Q1 and an N-channel MOSFET Q2, and a capacitor C.

During the sampling operation, the sampling signal A becomes high level, and the switch MOSFE is turned on.
TQ1 and Q2 are turned on, and the input signal Ain is applied to one electrode of the capacitor C. At this time, the capacitor C
The control signal 2 included in the level shift A output from the control logic is set to the high level on the other electrode of the P-channel type MOSFET Q7 and the N-channel type MOSFET Q8 to be turned on.
The voltage of f / 2 is supplied. That is, the capacitor C
The signal charge stored in the
It is assumed to correspond to a voltage obtained by subtracting Vref / 2 from in.

When the upper / lower conversion signal is activated to a high level, the P-channel type MOSFET Q3 and the N-channel type MOSFET Q4 are turned on, and the input voltage Vin is transmitted to the comparator array as a sample hold / level shift circuit output. Vref / 4, 3Vref / which is the divided voltage (D / A output) of the upper 2 bits.
4, Vref / 2, Vref / 4, 0V (AVss) are compared. As a result of this comparison, for example, if Vref> Vin (AIN)> 3Vref / 4 as shown in FIG. 4, the control signal 2 is deactivated to the low level, the control signal 0 is activated to the high level, and the switch MOSFETs Q11 and Q1 are activated.
2 is turned on, and the capacitor C has 0 V (AVss)
Is given. As a result, the input signal Vin is -Vre
The level is shifted by f / 2 so as to be in the above sub-range region.

Assuming that Vref / 4> Vin (AIN)> 0V
With such a low voltage, the control signal 2 is deactivated to the low level, the control signal 3 is activated to the high level, the switch MOSFETs Q5 and Q6 are turned on, and 3Vref / 4 is given to the capacitor C. Therefore, the input signal Vin is level-shifted by + Vref / 4,
It is made to be in the sub-range area.

3Vref / 4> Vin (AIN)> V
If ref / 2, the control signal 2 is deactivated to the low level, the control signal 1 is activated to the high level, and the switch M
The OSFETs Q9 and Q10 are turned on, and Vref / 4 is given to the capacitor C. Therefore, the input signal Vin is level-shifted by -Vref / 4 so as to be in the sub-range region. And Vref / 2>
Needless to say, the level shift operation is not performed as it is in the sub-range region such as Vin (AIN)> Vref / 4. Although the sample-hold / level-shift circuit A has been described with reference to FIG. 6, the circuit configuration and operation of the sample-hold / level-shift circuit B are similar to those described above, and therefore the description of the sample-hold / level-shift circuit B is omitted. .

FIG. 5 shows a schematic block diagram of the comparator array. The comparator array is composed of a selection circuit and five differential amplification circuits. The selection circuit uses the upper bit D / A outputs (Vref, 3Vref / 4, Vref).
ref / 2, Vref / 4, AVss) or the lower bit D / A output is selected. However, the comparison result output corresponding to Vref and AVss is ignored. That is, 3Vref
From the three comparison output results of / 4, Vref / 2, and Vref / 4, the upper 2 bits (9 bits and 8 bits) conversion output and the level shift control signal corresponding thereto are formed.

For the lower bit D / A conversion output, at the first time, five kinds of voltages obtained by dividing the sub-range area into 1 to 0 are selected. As a result, the determination result of 6 areas including the outside of the range can be obtained. If it is out of the range, the converted upper bits are corrected. The number of differential amplifier circuits is not particularly limited, but may be eight without providing a selection circuit. If no correction is performed, the number can be 3 to 6. 3V
An operational amplifier circuit is provided in a buffer that supplies ref / 4, Vref / 2, Vref / 4.

FIG. 7 shows A / D by simultaneous sampling.
The flowchart figure for demonstrating a typical example of conversion operation is shown. DS of the control register ADCR
The MP bit is set to "1" and each bit of the control register is set to a predetermined value. Then control register A
The ADST bit of DCR is set to "1" to start the A / D conversion operation. With the start of this A / D conversion operation,
The sampling operation is performed on the designated two channels at the same time. The first channel conversion operation is performed, and the conversion result is stored in the data register (eg, ADDRA). Next, the conversion operation of the simultaneously sampled second channel is performed, and the conversion result is stored in another data register (for example, ADDRB). The ADST bit is cleared to "0" and A / D conversion is stopped.

When the ADF bit of the control register ADCR is set to "1" to indicate the end of the conversion operation,
The interrupt signal ADI is generated from the control logic. The interrupt controller INT which has received the interrupt signal ADI issues a start request to the data transfer device DTC, and the data transfer device DTC reads the data registers ADDRA and B. The ADF bit is
It is cleared by the central processing unit CPU executing a bit clear instruction (BCLR) or automatically by the data transfer unit DTC. Central processing unit C
The converted data is processed by the PU or the like.

FIG. 8 shows an A / D based on normal sampling.
The flowchart figure for demonstrating a typical example of conversion operation is shown. DS of the control register ADCR
The MP bit is set to "0" and each bit of the control register is set to a predetermined value. Then the control register ADC
The ADST bit of SR is set to "1" to start the A / D conversion operation. By the start of this A / D conversion operation, the sampling operation of the designated first channel is performed. The first channel conversion operation is performed, and the conversion result is stored in the data register ADDR.
The channel sampling operation is performed. Next, the conversion operation of the sampled second channel is performed, and the conversion result is stored in another data register ADDR.

When the ADF bit of the control register ADCSR is set to "1" to indicate the end of the conversion operation,
The interrupt signal ADI is output to the interrupt controller INT, the data register ADDR is read, the ADST bit is cleared to "0", and the A / D conversion is stopped. The converted data processing is performed by the central processing unit CPU or the like.

The outline of the above A / D converter is as follows. The A / D converter has a resolution of 10 bits. As the operation mode, a buffer operation and a simultaneous sampling operation can be set in combination with four modes of select or group and single or scan. Select mode selects one channel and group mode selects multiple channels. In the single mode, conversion is performed once for all the selected channels, and in the scan mode, once the conversion is started, the conversion operation is repeated until it is stopped by software.

The buffer operation saves the previous conversion result in the buffer register at the end of conversion of the channel.
In the simultaneous sampling mode, two channels simultaneously sample the analog input voltage and sequentially convert it. Two operation modes, a high speed start mode and a low power consumption mode, can be selected by setting the PWR bit. When switching the operation mode or the input channel, with the ADST bit cleared to "0", the control register ADCSR,
Rewrite ADCR. Control register ADCSR,
When the ADST bit is set to "1" after rewriting the ADCR, the A / D conversion is started again. A / D conversion can be stopped by clearing the ADST bit to "0".

FIG. 9 shows a timing chart for explaining the select / single mode. In the figure,
0 to 2 bits of control register ADCSR (CH0 to CH
The case where channel 1 is selected by 2) is shown. Select single mode (GRP = 0, SCA
N = 0) is selected when performing A / D conversion for only one channel. When the ADST bit is set to "1" under the conversion start condition in which a predetermined value is set in TRGS1,0, A / D conversion is started. The ADST bit is
It holds "1" during A / D conversion and is automatically cleared to "0" when the conversion is completed. When the conversion is finished,
The ADF flag is set to "1". At this time, AD
When the IE bit is set to "1", an interrupt is generated by the interrupt signal ADI. ADF Fugu is
It is cleared by reading "0" after reading the control register ADCSR. Also, bit clear (BCL
It can also be cleared by the R) command.

In FIG. 9, when ADST is set to "1", the period T1 of the clock signal CLK as shown in FIG.
The channel 1 (AIN1) is selected by the selection signal 1A output from the control logic during the period from to T10, the sampling signal A is generated and taken in, and the conversion operation of the upper 2 bits is performed in the last period T10. Done. As a result of this conversion, the level shift signal A is generated as described above, and then the lower conversion signal A is generated to perform the A / D conversion operation divided into four by two bits. A latch signal is generated from the control logic in synchronization with the last T20 of the clock signal CLK, and the conversion result is captured in the data register ADDRB. The ADF flag is set to "1" by the end of the A / D conversion as described above.

FIG. 10 shows a timing chart for explaining the select / scan mode. In the figure, 0 to 2 bits (CH0 to 0) of the control register ADCSR are shown.
The case where channel 1 is selected by CH2) is shown. Select scan mode (GRP = 0, S
CAN = 1) is selected when A / D conversion of one channel is repeatedly performed. The ADST bit is "1" depending on the conversion start condition in which a predetermined value is set in TRGS0,1.
When set to, A / D conversion is started. The ADST bit holds "1" during A / D conversion, and holds "1" until it is cleared to "0" by software, during which A / D conversion of the selected input channel is performed. repeat. When the first A / D conversion is completed, AD
The F flag is set to "1". At this time, ADIE
If the bit is set to "1", interrupt signal A
An interrupt by DI occurs. The ADF Fukugu is cleared by reading "0" after reading the control register ADCSR. In addition, bit clear (B
It can also be cleared by the (CLR) command.

In FIG. 10, when ADST is set to "1", channel 1 (AIN1) is selected by the selection signal 1A in the same manner as described above, the sampling signal A is generated, and the sampling signal A is fetched. The conversion operation of the upper 2 bits is performed at the timing. As a result of this conversion, the level shift signal A is generated as described above, and then the lower conversion signal A is generated and divided into 4 by 2 bits.
The / D conversion operation is performed. A latch signal is generated in synchronization with the end of the conversion operation and the conversion result is stored in the data register ADD.
Captured by RB. The ADF flag is set to "1" by the end of the first A / D conversion. Simultaneously with the first A / D conversion 1 as described above, the second sampling 2 is performed.

When the ADST holds "1",
A / D of the input signal captured by the above sampling 2
Conversion 2 is performed, and at the same time, the third sampling operation is performed. In this way, the sampling operation and the A / D conversion operation are performed by the pipeline method. The conversion results are successively taken into the data register ADDRB. That is, the previous conversion result is replaced with the subsequent conversion result.

FIG. 11 is a timing diagram for explaining the group / single mode. In the figure, 0 to 2 bits (CH0 to 0) of the control register ADCSR are shown.
The case where channels 0 to 2 are selected by CH2) is shown. Group single mode (GRP =
1, SCAN = 0) is selected when A / D conversion of a plurality of channels is performed. When the ADST bit is set to "1" according to the conversion start condition in which a predetermined value is set in TRGS0,1, A / D conversion is started. ADS
The T bit holds "1" during the A / D conversion, and is automatically cleared to "0" when the conversion of all the designated input channels is completed. Further, when all the conversions of the designated input channel are completed, the ADF flag is set to "1". At this time, if the ADIE bit is set to "1", an interrupt by the interrupt signal ADI occurs. The ADF Fukugu is cleared by reading "0" after reading the control register ADCSR. Also, bit clear (BCLR) as above
It can also be cleared by an instruction.

In FIG. 11, when ADST is set to "1", channel 0 (AIN0) is selected by the selection signal 0A output from the control logic in the same manner as described above, the sampling signal A is generated, and its fetching is performed. Then, the conversion operation of the upper 2 bits is performed at the end. As a result of this conversion, the level shift signal A is generated as described above, and then the lower conversion signal A is generated, and the operation of A / D conversion 1 divided into four by two bits is performed. At the end of the conversion operation, the latch signal A is generated and the conversion result 1
Are taken into the data register ADDRA. A /
In parallel with the operation of the D conversion 1, the channel 1 (AIN1) is selected by the selection signal 1B and the sampling signal B is generated and taken in.

A / D of lower 8 bits of channel 1
In parallel with the operation of the conversion 2, the selection signal 2A is generated and the channel 2 (AIN2) is selected, and the sampling signal A is generated and taken in. The A / D conversion result 2 of the channel 1 is taken into the data register ADDRB and the channel 2 (AIN2)
The operation of A / D conversion 3 is performed. The ADF flag is set to "1" by the end of the A / D conversion operation of the last channel. In this way, sampling on a plurality of channels and its conversion operation are performed by a pipeline method.

FIG. 12 is a timing chart for explaining the group scan mode. In the figure, 0 to 2 bits (CH0 to 0) of the control register ADCSR are shown.
The case where channels 0 to 2 are selected by CH2) is shown. Group scan mode (GRP =
1, SCAN = 1) is selected when A / D conversion of a plurality of channels is repeatedly performed. When the ADST bit is set to "1" according to the conversion start condition in which a predetermined value is set in TRGS1,0, A / D conversion is started. A
The DST bit holds "1" during A / D conversion, and holds "1" until it is cleared to "0" by software. The ADF flag is set to "1" when all the first conversions of the designated input channel are completed. At this time, if the ADIE bit is set to "1", an interrupt by the interrupt signal ADI occurs. The ADF Fukugu is cleared by reading "0" after reading the control register ADCSR. It can also be cleared by a bit clear (BCLR) instruction as in the above.

In FIG. 12, when ADST is set to "1", channel 0 (AIN0) is selected by the selection signal 0A in the same manner as described above, the sampling signal A is generated, and its sampling (sampler 1) is performed. Finally, the conversion operation of the upper 2 bits is performed. As a result of this conversion, the level shift signal A is generated as described above, and then the lower conversion signal A is generated, and the operation of A / D conversion 1 divided into four by two bits is performed. At the end of the conversion operation, the latch signal A is generated from the control logic and the conversion result 1 is taken into the data register ADDRA. In parallel with the operation of the A / D conversion 1, the channel 1 (AIN1) is selected by the selection signal 1B, and the sampling signal B is generated and taken in (sampling 2).

A / D of lower 8 bits of channel 1
In parallel with the operation of the conversion 2, the selection signal 2A is generated and the channel 2 (AIN2) is selected, and the sampling signal A is generated and taken in (sampling 3). The A / D conversion result 2 of the channel 1 is taken into the data register ADDRB, and the operation of the A / D conversion 3 of the channel 2 (AIN2) is performed.
In parallel with the operation of the A / D conversion 3, the selection signal 0B is generated to select the channel 0 (AIN0), and the sampling signal B captures it (sampling 4). The ADF flag is set to "1" by the end of the A / D conversion operation of the last channel. In this way, sampling on a plurality of channels and its conversion operation are repeatedly performed by a pipeline method, and when ADST is cleared to "0" by software, the conversion operation is stopped.

FIG. 13 is a timing diagram for explaining the buffer operation. In the figure, select
The case of the scan mode (GRP = 0, SCAN = 1) is shown as an example. In the buffer operation, when the conversion of the channel is completed, the conversion result is stored in the data register A.
At the same time as storing in DDRA, the conversion result stored before is transferred to another data register. For the buffer operation, bits 0, 1 (BUF) of the control register ADCR are used.
According to the data stored in E0, BUFE1),
AIN0 → ADDRA → ADDRB two-stage operation, and
IN0 → ADDRA → ADDRC, AIN1 → ADDR
B → ADDRD two-stage / two-set operation and AIN0 → ADD
It is possible to select any one of the operations of four stages of RA → ADDRB → ADDRC → ADDRD. Even in this case, the channels 4 to 7 can execute the normal A / D conversion operation. Further, when the conversion result is stored in the buffer register and the registers are saturated (when the A / D converted data is written in all the previously designated registers), the ADF flag is set to "1". At this time, if the ADIE bit is set to "1", the interrupt signal ADI
Causes an interrupt. The ADF Fukugu is cleared by reading "0" after reading the control register ADCSR. In addition, bit clear (BCL
It can also be cleared by the R) command.

FIG. 13 shows AIN0 → ADDRA → ADD.
The case of a two-stage RB operation is shown. According to the select / scan mode (GRP = 0, SCAN = 1), the conversion result 1 is the data register AD according to the latch signal A.
When the conversion result 2 is stored in the DRA and the conversion result 2 is formed, the conversion result 1 is stored in the data register ADDR according to the latch signal B.
The data is transferred to B and the conversion result 2 is stored in the data register ADDRA according to the latch signal A. Thus, when the conversion result is stored in the buffer register and the register is saturated, the ADF flag is set to "1". When ADST is cleared to "0" by software after the third A / D conversion 3 operation is completed, the conversion operation is stopped and the conversion result 3 is stored in the data register ADDRA as A
The conversion result 2 is stored in DDRB.

FIG. 14 shows AIN0 → ADDRA → ADD.
The operation case of two sets of two stages of RC, AIN1 → ADDRB → ADDRD is shown. The conversion result 1 is stored in the data register ADDRA according to the latch signal A and the conversion result 2 is stored in the data register ADDRB according to the latch signal B in the group scan mode (GRP = 1, SCAN = 1). When the conversion result 3 is formed, the conversion result 1 is transferred to the data register ADDRC according to the latch signal C, and the data register ADDR is transferred.
The conversion result 3 is stored in A according to the latch signal A. Similarly, when the conversion result 4 is formed, the conversion result 2 is obtained.
Is transferred to the data register ADDRD according to the latch signal D, and the conversion result 4 is stored in the data register ADDRB.
Are stored according to the latch signal B. Thus, when the conversion result is stored in the buffer register and the register is saturated, the ADF flag is set to "1".

In the simultaneous sampling operation, the input voltages of the two channels are simultaneously sampled and continuous conversion is performed.
If the simultaneous sampling operation (DSMP = 1) is specified,
Conversion is performed for every two channels by specifying the CH2 and CH1 bits of the control register ADCSR. Table 3 below shows how to select channels in the simultaneous sampling operation. The CH0 bit is invalid.

[0084]

[Table 3]

FIG. 15 is a timing diagram for explaining the simultaneous sampling operation. In the figure, the case of the group / single mode is shown as an example. In the figure, when DSMP is set to "1" and ADST is set to "1", channels 0 and 1 (AI) are selected by the selection signals A and B output from the control logic.
N0 and AIN1) are selected and sampling signals A and B are selected.
Is generated and the acquisition is performed at the same time, and finally, the conversion operation of the upper 2 bits is performed on the channel 0 side.
As a result of this conversion, the level shift signal A is generated as described above, then the lower conversion signal A is generated from the control logic of the channel 0, and the operation of the A / D conversion 1 divided into four by 2 bits is performed. . At the end of the conversion operation, the latch signal A is generated from the control logic,
The conversion result 1 is taken into the data register ADDRA. After the end of the operation of the A / D conversion 1, the A / D conversion operation of the channel 1 is performed, and the conversion result 2 is taken into the data register ADDRB. When the operation of the A / D conversion 2 is completed, the ADF flag is set to "1".

FIG. 16 shows a timing diagram for explaining the simultaneous sampling operation. In the figure, the case of the group scan mode is shown as an example.
In the figure, (DSMP = 1, GRP = 1, SCAN =
1) When ADST is set to "1", the selection signal 1
Channels 0 and 1 (AIN0 and AIN by A and 1B)
1) is selected, sampling signals 1A and 1B are generated and taken in at the same time, and finally the conversion operation of the upper 2 bits is performed on the channel 0 side. As a result of this conversion, the level shift signal A is generated from the control logic as described above, then the lower conversion signal A of channel 0 is generated, and the A / D divided into 4 times by 2 bits.
The operation of conversion 1 is performed. At the end of the conversion operation, the control logic generates the latch signal A and the conversion result 1
Are taken into the data register ADDRA. A /
After the end of the D conversion 1 operation, the channel 1 A / D
The conversion operation is performed, and the conversion result 2 is the data register A.
It is taken into DDRB. Upon completion of the operation of the first A / D conversion 2, the ADF flag is set to "1".

When the operation of the above A / D conversion 2 is completed,
Then, the selection signals 1A and 1B are generated and the channel 0
And 1 (AIN0 and AIN1) are selected again, sampling signals 1A and 1B are generated, and the sampling signals are simultaneously captured. After that, when ADST is cleared to "0" by the software, the changing operation is stopped and the conversion standby state is set.

FIG. 17 shows a timing chart for explaining the interval operation. Control register AD
When the INT bit of CR is set to "1", the following interval operation is performed. For example, the group scan mode is set, and C of the control register ADCSR is set.
Input signal AIN by setting 010 by H2-CH0
A case where 0 to AIN2 is selected will be described as an example.

The first sampling / conversion of AIN0 to AIN2 is sequentially performed by the pipeline method as described above. The BUSY signal becomes active when AIN2 is sampled. After that, no new conversion is started. A
After the conversion of IN2 is completed, the ADF Fuku is set to "1", and the interrupt is requested by the interrupt signal ADI. Central processing unit CPU or data transfer unit DTC
However, in response to the interrupt, the conversion result is read and the ADF flag is cleared to "0".

In particular, the ADF by the data transfer device DTC
The flag is cleared after all the designated data transfers are completed. When the central processing unit CPU clears the ADF flag to "0", bit clear (BCL
R) It is done by an instruction. This operation reads bit 7 in the control register ADCSR
Only the bits are cleared to "0", other bits are retained and written in byte units. The above-mentioned instruction is executed by the CPU in the "H8 / 3003 Hardware Manual".
Is the same as When the ADF flag is cleared to "0", the BUSY signal becomes inactive. Since the ADST bit is held at "1", a new conversion is started.

FIG. 18 is a schematic flow chart diagram for explaining the operation of the A / D converter according to the present invention. The general operation of the above A / D converter will be summarized and described below.

The system waits until ADST is set to "1". In the interval operation in which INF is set to "1", the standby state is set until the ADF flag is cleared to "0". The number n of data to be converted is selected by the control registers ADCSR and ADCR. For example, the buffer operation is performed in the select mode, and n = 1 except for simultaneous sampling. In the 4-stage buffer operation in the select mode, n = 4.

The sampling of the first channel is performed. n
If> 1, the sampled data is converted and the next sampling operation is performed. Decrement n. If n = 1, that is, if the last data conversion, BUSY is set to "1". In the single mode, conversion is performed, the ADF flag is set to "1", the ADST bit is cleared to "0", and the operation returns to the standby state.

If the scan mode is not the interval operation, the sampled data is converted and the next sampling is performed. Reset n (recover the initial value). The ADF flag is set to "1" and the operation is continued. If it is an interval operation in scan mode, the sampled data is converted. Reset n (recover the initial value). Set the ADF flag to "1" and set ADF
It is in a standby state until the flag is cleared to "0". In case of simultaneous sampling operation, CHS0 bit is "1"
Except that it is regarded as, and sampling of 2 channels is performed once for conversion of 2 channels at the same time.

The PWR bit selects the conversion start mode of the A / D converter. When the PWR bit is cleared to "0", the analog circuit (A / D converter, more specifically, analog multiplexer, sample hold / level shift circuit A / B, comparator array A / B, 2-bit voltage division, 6-bit voltage division Pressure) becomes inactive except for the conversion operation. When the PWR bit is set to "1", the fast start mode is set, and the analog circuit is always set to the active state.

In the low power consumption mode in which the PWR bit is "0", ADST is set to "1" and the analog circuit is turned on at the same time, and the control register ADCSR is turned on.
When 200 cycles of the reference clock selected by the CKS bit of 1 have passed, the analog circuit shifts to a convertible state and starts the first A / D conversion. When the conversion is continuously performed, the second and subsequent A / D conversion operations are performed in 10 cycles. When the designated A / D conversion operation is completed, the analog circuit is automatically turned off and the power consumption is reduced.

The bus interface is an interface between the data registers ADDRA to ADDRD and the bus master (internal data bus), and the internal data bus has a 16-bit width. Data registers ADDRA to AD from the bus master via this bus interface
The DRD can be read in word units or byte units. When reading the data register ADDR in word units, the contents of the data register ADDR are transferred to the bus master in a batch of 16 bits. In addition, when reading in byte units, converted data (AD9 to AD0)
The contents of the upper bits (AD9 to AD2) of the are transferred to the bus master. The lower 8 bits cannot be read in byte units.

FIG. 19 is a block diagram of the main part of the read control circuit including the bus interface. The data register ADDR, the in-module data bus MDB, and the bus interface BIF have a 10-bit configuration. In the figure, the 10-bit data is divided into three, that is, bit 9-8, bit 7-2, and bit 1-0. The A / D conversion result is stored so that the most significant bit of the data register ADDR corresponds to bit 9.

Central processing unit CPU or data transfer unit D
For reading from TC, the decode result (decode signal) of the address signal and the read signal R are read through the internal data bus.
The data is read out under the control of the D and word signals (WORD). At the time of reading, the decode signal and the read signal RD are output via the AND gate, and the data registers ADDRA to ADDRH or the control signal ADC are output.
Either R or ADCSR is selected. That is, one of the output buffers corresponding to each register is activated by the decode signal, the data of the selected one is output to the intra-module bus MD9-0, and the bus is transmitted via the intra-module bus MD9-0. It is transferred to the interface BIF9-0.

The data taken into the bus interface BIF9-0 is output via the output buffers of two systems. On the other hand, 10-bit data divided into the above three divisions is directly used as the internal data buses DB9-DB0.
Is output in correspondence with. The other is the upper bit BIF9-
8 bits of 2 are output corresponding to the internal data bus DB7-0. The above 10-bit read is performed by the read signal R
When D and the word signal WORD are in the activated state, the buffer circuit for outputting the above 10-bit data through the AND gate circuit is activated. At this time, 1
Of the 6-bit wide internal bus, "0" is output to DB15-10. For reading 1 byte, the buffer circuit corresponding to the above 8 bits is activated through the AND gate circuit when the read signal RD and the word signal WORD are inactive. In such a byte size read, of the A / D conversion results with 10-bit resolution,
The upper 8 bits are valid, in other words, shifted downward by 2 bits and output to the internal data bus.

With this configuration, the resolution of the A / D converter can be designated by the central processing unit CPU or the data transfer unit DTC designating the word signal WORD at any time.
For example, when the central processing unit CPU desires to obtain a conversion result with 10-bit resolution, the word signal WORD may be activated and read. For example, transfer instructions MOV, W
Use @ADDR, R0, etc. On the other hand, when the central processing unit CPU desires to obtain a conversion result with 8-bit resolution, the word signal WORD may be inactivated and read. For example, transfer instructions MOV, W @ADDR, R0H
And so on. By performing the data alignment in the bus interface in this way, it is possible to suppress the increase in the logic scale by making the alignment circuit common, and to eliminate the need for shift processing as compared with the case of using software. Then, the load on the central processing unit CPU can be significantly reduced.

In addition to designation by bus size as described above,
You may arrange | position so that an address may differ. For example, as shown in the address map diagram of FIG. 20, an address from which a conversion result with 10-bit resolution can be read and an address from which a conversion result with 8-bit resolution can be read may be provided independently. Data registers ADDRA to ADDRH that can read conversion results with 10-bit resolution
It is convenient to sequentially arrange the addresses in units of words (16 bits) and the addresses of the data registers ADDRA to ADDRH that can read the conversion result of 8-bit resolution in units of bytes (8 bits). In particular, when the data transfer device DTC reads a conversion result with 8-bit resolution, a useless read cycle does not occur.

FIG. 20 shows relative addresses. ADDRA to H have both an address (0-F) as a 16-bit register and an address (10 to 17) as an 8-bit register. When word data starting from relative address 0 is read, the conversion result stored in ADDRA is read with 10-bit resolution. When byte data of relative address 10 is read, ADD
The conversion result stored in RA is read with 8-bit resolution (lower-order data shifted right by 2 bits).

FIG. 21 shows an example of a control circuit corresponding to the above address system. The data register gives a logical sum signal of the decode signals to two addresses and reads it. For example, the ADDRA is supplied with the detection signal of the address 0 as the decode signal W and the detection signal of the address 10 as the decode signal B. The bus interface BIF receives a signal indicating that any one of the addresses 0 to F is applied to the bus interface BIF.
A signal for activating the buffer circuit corresponding to a total of 16 bits including F9-0 is formed and the conversion result of 10-bit resolution is read. According to a signal that detects that any of the addresses 10 to 17 is applied, the buffer circuit corresponding to the bus interface BIF9-2 is activated corresponding to the lower byte of the internal data bus and the conversion result of 8-bit resolution is read. To be done.

FIG. 22 is a bit arrangement diagram for explaining the reading of word data and byte data as described above. 16-bit data register AD
In the DR, a conversion result of 10 bits is stored in 9-0, and "0" is stored in 15-10. When this is read as word data (10-bit resolution), the data stored in bits 0 to 15 of the data register ADDR is output to the internal 16-bit data bus. On the other hand, byte data (8-bit resolution)
When read as, the data stored in bits 2 to 9 of the data register ADDR is output to the internal 8-bit data bus.

FIG. 23 shows the data registers ADDRA.about.
A mutual circuit block diagram of ADDRD is shown. This circuit is compatible with the buffer operation. Data from the successive approximation register can be input to each of the registers ADDRA to ADDRD via a buffer circuit.
When each of the selection signals a to d is in the active state and the latch signal at the end of conversion is in the active state, the contents of the successive approximation register are stored in any one of the data signals corresponding to the active state among the selection signals a to d. It is captured. Each register ADDRA to D has a so-called master-slave configuration.

In the Huffer operation, when the BUFE1,0 bit is 01, the buffer operation 1 signal becomes active. When the BUFE1,0 bit is 10, the buffer operation 2 signal is activated. BUFE 1,0 bit is 11
At this time, the buffer operation 3 signal is activated. Each of the buffer operation 2-3 signals is controlled by the control register ADCR.
Is output from the control logic based on the data set in BOFE1,0 of the.

When the select signal a and the latch signal are generated while the buffer operation 1 signal is active, the old data in the data register ADDRA is transferred to the data register ADDRB via the buffer circuit, and the output of the successive approximation register is changed to the data. It is taken into the register ADDRA.

When the selection signal a and the latch signal are generated while the buffer operation 2 signal is active, the old data in the data register ADDRA is transferred to the data register ADDRC via the buffer circuit, and the output of the successive approximation register is changed to the data. It is taken into the register ADDRA. When the selection signal b and the latch signal are generated, the data register A
The old data of DDRB is transferred to the data register ADDRD via the buffer circuit, and the output of the successive approximation register is captured in the data register ADDRB.

When the buffer operation 3 signal is active, the buffer circuit controlled by the buffer operation 3 signal causes the data register ADDRA.fwdarw.ADDRB.fwdarw.ADDRC.fwdarw.ADD.
The data is transferred in the order of RD in synchronization with the acquisition of the A / D conversion result.

FIG. 24 shows a block diagram of an embodiment of the analog multiplexer. Analog input AI
N0 to AIN7 consist of N channel type MOSFET and P channel type MOSFET in total 16 CMOS
It is taken in as first and second inputs corresponding to the sample and hold / level shift circuits A and B via the switch circuit. Select signals 0A and 0B that are switch control signals
7A and 7B are given from the control logic. For example, when the analog inputs AIN4 and AIN5 are A / D converted in the group mode by simultaneous sampling, first, the selection signals 4A and 5B are activated, and the input level from the analog input AIN4 is sampled and held. The level shift circuit A samples and the input level from the analog input AIN5 is sampled by the sample hold level shift circuit B. After that, the results of the simultaneous sampling are sequentially A / D converted.

A circuit diagram of another embodiment of the analog multiplexer is shown in FIG. Similar to the above, the function as an input port and the protection circuit are omitted. Analog inputs AIN0 to AIN7 are N-channel type MOS
CMOS consisting of FET and P-channel MOSFET
It is fetched as the first input and the second input similar to the above through the switch circuit. In this embodiment, one analog input is selected by the two-stage switch circuit.

The selection signals 01, 23, 45, 67 and the selection signals EA, OA, EB, OB are given from the control logic. The selection signals 01, 23, 45 and 67 select two adjacent analog inputs for each two channels. The select signals 01, 23, 45 and 67 are generated by decoding 1 bit of CHS2 in the select mode. In the group mode, it is generated according to the status signal in the control logic. Selection signal 01
Is the OR signal of the selection signals 0A, 0B, 1A, 1B in the above example. Similarly, the selection signal 23 is the selection signals 2A, 2
OR signal of B, 3A, 3B, selection signal 45 is selection signal 4
The OR signals of A, 4B, 5A and 5B and the selection signal 67 are OR signals of the selection signals 6A, 6B, 7A and 7B. The selection signal OA is an OR signal of the selection signals 1A, 3A, 5A and 7A. The selection signal EA is the selection signals 0A, 2A,
It is an OR signal of 4A and 6A. The selection signal EB is an OR signal of the selection signals 0B, 2B, 4B, 6B. The selection signal OB is an OR signal of the selection signals 1B, 3B, 5B and 7B. Simultaneous sampling is performed by performing odd-numbered sampling in the group mode at the same time as immediately preceding odd-numbered sampling. With this configuration, the number of switches can be reduced to 12.

FIG. 26 shows a circuit diagram of an embodiment of the BUSY output control circuit included in the eighth port IOP8. The BUSY output is also used as a port for inputting / outputting data. The BUSY output control circuit includes a terminal, an output buffer, a data direction register DDR, a data register DR, an input buffer, and a selector.

The data direction register DDR is
It consists of flip-flops. A write control signal is given by a write signal and an address decode signal (not shown), and the contents of the data bus are written. DD
When R is set to "1", the terminal enters the output state (the output buffer is enabled), and the output of the output buffer is output to the terminal. The control signal of the selector is a signal indicating that the A / D converter has selected the external trigger by ADTRG with TRGS1 and 0 bits. When the external trigger is selected, the BUSY signal of the A / D converter is selected. When the external trigger is not selected, the output of the data register DR is selected. The data register DR is composed of a flip-flop. A write control signal is given by a write signal and an address decode signal (not shown), and the data on the data bus is written in the data register DR. Further, a read control signal is given by a read signal and an address decode signal (not shown), and the data supplied to the terminal is read out to the data bus.

When outputting the BUSY signal to the outside,
Select external trigger by ADTRG and set DDR to "1"
Set to. When a conversion start other than ADTRG is selected, it is advisable to output the same level as the BUSY state as the port output in a state in which ADTRG is not selected.

The BUSY signal is activated when there is only one free space in the data buffer when sampling is started by ADTRG. When the ADF flag is set to "1", the BUSY signal is activated. After that, when the ADF flag is cleared to "0", the BUSY signal becomes inactive. For example, ADF
When the operation is started by the ADTRG signal in the select mode with the flag cleared to "0", the BUSY signal becomes active at the start of sampling. When the conversion is completed, the ADF flag is set to "1". After that, the central processing unit CPU or the data transfer unit DTC
When the ADF flag is cleared to "0" by
The USY signal becomes inactive.

When the operation is started by the ADTRG signal in the group mode with the ADF flag cleared to "0", the BUSY signal becomes active at the start of sampling the last channel. When the buffer operation of the 1-input 2-register is designated, the BUSY signal becomes active at the time of the second sampling. When the buffer operation of the 1-input 4-register is designated, the BUSY signal becomes active at the time of the fourth sampling. If the 2-input 4-register buffer operation is specified, the second second
The BUSY signal becomes active when the channel is sampled.

FIG. 27 is a timing chart for explaining the operation of the A / D converter based on the PWR bit. In the conversion standby state, the PWR bit is cleared to "0". The analog circuit is inactive and reduces current consumption. In this state, when the ADST bit is set to "1" by software, an external trigger or a timer trigger, the flag IPWR in the control logic is set to "1". Although the analog circuit is activated, the analog circuit operates stably (MOS of the operational amplifier).
200 clock period, A / D until FET charge etc.)
The transducer goes into standby. After that, the PON signal output from the control logic becomes "1", and the first A / D conversion operation is performed. Subsequent operations are the same as above.
After the designated A / D conversion operation is completed, the IPWR flag is cleared to "0", and the analog circuit becomes inactive. The control logic has a counter that counts the 200 clocks.

If the PWR bit is set to "1" by software in advance, the internal IPWR flag is set to "1", and the analog circuit becomes active at this point, and the analog circuit is activated for a predetermined time (equivalent to 200 clocks, for example, 10 clocks).
After the elapse of μs), the A / D converter is ready for conversion. After that, when the ADST bit is set to "1" by software, an external trigger or a timer trigger, the internal PON becomes "1" and A / D conversion is immediately started. The internal IPWR bit is retained. The counter that counts 200 clocks is disabled.

When used for periodical external input monitoring or the like, for example, when converting an input signal sufficiently slower than 200 clocks, the PWR bit is cleared to "0" and A / D converted. If possible, set the ADST bit to “1” to start conversion and clear the PWR bit to “0” in the A / D conversion end interrupt routine.
The conversion result may be processed. The software does not need to measure 200 clocks (waiting for an interrupt), and there is no load on the software. In addition, since the period when the analog circuit is active can be minimized,
It is possible to reduce current consumption.

When it is necessary to immediately start A / D conversion at a desired timing, the PWR bit may be set to "1" by software in advance, for example, in a reset processing routine. After the time equivalent to 200 clocks or more has elapsed, ADS is set by software at the desired time.
The T bit is set to "1" and A / D conversion is started. Bits other than the PWR bit and ADST bit can be set arbitrarily.

Initialization processing of the system or the single-chip microcomputer itself often requires 200 clocks or more, so that in actual use, A / D conversion is always possible. After that, by setting the ADST bit to "1" by software, an external trigger or a timer trigger, the A / D conversion is immediately started, so that the processing accuracy and the real-time property can be improved. it can.

FIG. 28 is a block diagram showing an embodiment of a control system using the single chip microcomputer according to the present invention. The single chip microcomputer MCU shown in FIG. 1 uses the single chip microcomputer shown in FIG. The control system in the figure is directed to motor control of an AC induction motor, a brushless DC motor, or the like, using the single-chip microcomputer.

The complementary three-phase PWM output (U, U #, V, V #, W, W #) from the timer B is used to drive the inverter motor M through the inverter circuit. Such complementary three-phase PWM output is, for example, the above-mentioned “H8 / 300”.
3 Hardware Manual ”pp. 374-381. As described above, if no overlap can be set between the positive-phase / negative-phase outputs, it is possible to prevent the transistors connected in series that form the inverter circuit from being turned on at the same time, and prevent a large through current from flowing through the transistors.

The output of the inverter circuit drives the motor. For example, the output of the inverter circuit is applied to a so-called Y connection (or star connection) or a Δ-connected stator winding inside the motor, although not particularly limited thereto. The PWM output cycle (carrier wave cycle) is, for example, 40
00 state (20 μs = 5 KHz).

A two-phase inverter drive current is detected, and A
Input to analog inputs AIN4, 5 of the / D converter. As described above, since the output of the inverter circuit is Y-connected (or star-connected) or Δ-connected, the total value of the three-phase currents becomes zero. The current of the third phase can be obtained by detecting the current of the second phase. These A /
The D conversion is activated by the compare match A and underflow of the timer B, and performs conversion in the group / single mode.

That is, the control register can measure the motor current in synchronization with the timer output. Since the A / D converter can be activated by hardware, the time from the predetermined timing of the timer until the motor drive current is measured can be shortened, and the detection accuracy can be improved. Sampling is performed in 20 states (1 μs), and 80 states (4
The conversion result can be obtained in μs). By sampling the currents of two phases at the same time, the current detection accuracy can be improved and reflected in the timer output, and the control accuracy can be improved.

These require precision, and the central processing unit CPU reads in word size to obtain 10-bit resolution. Since the data is left-justified, it can be directly calculated with other parameters. The processing speed of the central processing unit CPU can be increased. For example, the PWM duty is changed so that the measurement result of the current matches the intended current value. By using the A / D converter according to the present invention, it is possible to improve the measurement accuracy, reduce the load on software, and improve the processing performance of the entire system.

Further, the output of the sensor circuit for detecting the ambient temperature and the voltage is compared with the analog input AIN0 of the A / D converter,
Input in 1, 4-7. For example, a timer A compare match or overflow interrupt is generated about every 100 ms. By such interrupt processing,
The central processing unit CPU sets a control register so that the analog inputs AIN0, 1, 4 to 7 sample sensor information at a constant time interval, for example, in the group / single mode.

The resolution of the ambient temperature and the power supply voltage is not required so much, and the central processing unit CPU
Can be read to obtain 8-bit resolution data. The central processing unit CPU determines these contents, changes various parameters, and performs other input / output processing. For example, the PWM duty of the timer B is changed. The other outputs of the timer A and the timer B drive another DC motor or a stepping motor through another driver circuit. I / O port IOP
1-3 control various switches and relays.

FIG. 29 shows a timing chart for explaining an example of the operation of the timer B and the A / D converter. Timer B has two up / down counters TCN
Up / down counting operation is performed between T3 and TCNT4 between 0 and the cycle setting register. These counters TCN
The timer outputs U and U # are output by a compare match between T3 and T4 and the compare register U. U and U # are PWM outputs having a complementary no-overlap relationship with each other. Similarly, timer outputs V, V # and W, W are generated by a compare match with a compare register V, W (not shown).
Output #.

The central processing unit CPU activates the A / D converter at both the compare match with the cycle setting register of the channel 3 of the timer B and the underflow of the channel 4. The central processing unit CPU sets the control register for the input channels AIN2, 3 and keeps the activation by the timer B selected. The A / D converter is in a standby state when the above-mentioned activation factor does not occur.

A logical sum signal of compare match A3 of channel 3 and underflow of channel 4 is given from the timer to the A / D converter as a start signal of the A / D converter. When the selected start signal is generated, the analog multiplexer control signals 4A and 5B are activated at the same time, and the input signals of AIN2 and AIN3 are simultaneously stored in the sample hold level shift circuits A and B, respectively. After that, A / D conversion operations A and B are sequentially performed,
The A / D conversion result of the input signals AIN2 and AIN3 is stored in the data register. Thereby, the drive current of the motor can be measured. Since these are sampled at the same time, the relative current value can be accurately measured. Further, this also makes the calculation result of the current value of the third phase accurate.

FIG. 30 shows a timing chart for explaining another example of the operation of the timer B and the A / D converter. Similarly to the above, the timer B performs the up / down counting operation between the two up / down counters TCNT3 and TCNT4 being 0 and the period setting register GRA in the timer B. Similar to the above, these counters TCNT3,
By a compare match between 4 and the compare register U,
The timer outputs U and U # are output. U and U # are PWM outputs having a complementary no-overlap relationship with each other.
Similarly, timer outputs V, V # and W, W # are output by a compare match with a compare register V, W (not shown).

Similarly to the above, the A / D converter activates the A / D converter by both the compare match with the cycle setting register of the channel 3 of the timer B and the underflow of the channel 4. The A / D converter sets the control register to the input channels AIN2 and AIN3 and keeps the activation by the timer B selected. The A / D converter is in a standby state when the above-mentioned activation factor does not occur.

A logical sum signal of compare match A3 of channel 3 and underflow of channel 4 is given from the timer to the A / D converter as a start signal of the A / D converter. When the selected start signal is generated, the A / D conversion result of the input signals AIN2 and AIN3 is stored in the data register in the same manner as described above. Thereby, the drive current of the motor can be measured.

In addition, when it is desired to convert other input analog signals of the A / D converter at regular time intervals by a timer A compare match or the like, the central processing unit CPU is interrupted by the timer A compare match interrupt. Let the process take place. By this interrupt processing, the central processing unit CPU can reset the control register of the A / D converter and convert a desired analog input to input other sensor information and the like. The central processing unit CPU performs the desired processing as parameter information, for example, and reflects the result in the subsequent setting of the timer output value. After the completion of the A / D conversion process, the control register is activated by both the compare match with the cycle setting register of the channel 3 of the timer B and the underflow of the channel 4. ,
It is possible to obtain an A / D conversion result corresponding to the motor drive current from the input signals AIN2 and AIN3. In this way, one A / D converter can perform measurement of the motor current synchronized with the PWM output and conversion of other analog inputs.

FIG. 31 is a flow chart for explaining the operation of the above single chip microcomputer. When the reset is released in (A), the microcomputer is initialized. This initialization includes initialization of the timer ITU, A / D converter, data transfer device DTC, I / O port and the like. The A / D converter is set to convert the input channels AIN2 and AIN3 according to the trigger of the timer ITU. The timer A starts operating as an interval timer.

When the above initialization is completed, a motor start request waiting state is entered. The request for starting the motor is given from, for example, the host CPU CPU via the input / output port. When a start request is generated, a compare value is calculated according to a desired process, and the compare value is arranged in the first area on the RAM.

Start the timer ITU. Timer output is performed, and the state is waiting for an interrupt. The IMIA3 interrupt corresponding to the compare match signal of FIG. 29 (mountain; cycle T0,
T2) or UVI4 corresponding to underflow signal
When an interrupt (valley; cycle T1) occurs, a start signal is given to the A / D converter, and A / D conversion of the input channels 2 and 3 is performed automatically or according to the initial setting by hardware. Further, the data transfer device DTC is activated by the IMIA3 interrupt (peak) or the UVI4 interrupt (valley), and the buffer register (TGB, DRG) of the timer ITU is started from a predetermined address on the RAM.
The compare value is transferred to (C, TRGD) and the PWM duty is changed.

By the interrupt processing routine of the central processing unit CPU, the conversion result of the A / D converter is read and 2
Obtain the motor drive current for each phase. Also, based on this, 3
The motor drive current of the phase is calculated. In addition, R in advance
The input value of the sensor circuit held in the second area on the AM is read. Although not shown in the above and not shown, a new compare value is calculated by performing desired processing with reference to the speed command, the position / speed of the motor, the motor drive current, and other input values of the sensor. This is arranged in the first area on the RAM.

As shown in (B), when the interval interrupt of the timer A occurs, the setting value of the A / D converter is changed and the input value of the sensor other than the motor drive current is changed to A / D by starting the software. Convert. The converted result is held in the second area on the RAM. The setting of the A / D converter is returned to the original state and the process returns.

FIG. 33 is a block diagram showing another embodiment of the control system using the single chip microcomputer according to the present invention. The single chip microcomputer MCU shown in FIG. 1 uses the single chip microcomputer shown in FIG. The control system in the figure is directed to automatic focus control of the lens portion of the camera by using the single chip microcomputer.

The input light obtained through the lens and the half mirror is CCD (charge transfer device) or BAS.
It is converted into an electric signal by a photoelectric conversion element such as IS. The output of the photoelectric conversion element is an analog input through an interface circuit including an amplifier, a buffer, etc.
Input to IN0. Further, the trigger signal ADTRG output from the interface circuit is input through the external trigger terminal. The BUSY signal from the microcomputer is given to the logic gate circuit in the interface circuit, and the photoelectrically converted data (AIN0) is supplied to the single-chip microcomputer MCU when the A / D conversion result is not processed. Instruct to suspend. The interface circuit controls conversion and reading of the photoelectric conversion element. For example, the secondary phase difference detection method is used to detect whether or not the focal points match.

Microcomputer MCU of this embodiment
Outputs a command to the lens microcomputer L-MCU to drive the lens AF motor. The above-mentioned command to the L-MCU may be issued by the serial communication interface SCI, a two-phase encoder pulse, or any other digital output. Also, the encoder input of the AF motor is the clock input of the timer B (TCLKA, TCLKB)
To detect the speed / position of the AF motor. The AF motor is driven while monitoring these.

Through the serial communication interface SCI and the input / output port, the main microcomputer M-MCU, the lens microcomputer L-MCU, and further the EEPROM (electrically erasable & programmable read only
Memory). The EEPROM stores various control information. For example, the EEPROM stores data for correcting the light receiving sensitivity of each photoelectric conversion element. AF accuracy can be improved by such correction. From the main microcomputer M-MCU, input operation mode command and focus detection start command,
Notifies the completion of focus detection. In addition, the output of the port drives an LED (light emitting diode), lights a lamp such as auxiliary light at the time of focus detection, and inputs various switches.

The A / D converter selects select / single mode, buffer operation, and conversion start by an external trigger. By the conversion end interrupt, the data transfer device D
The TC is activated and the conversion result is saved in the RAM. FIG.
As shown in FIG. 2 (A), when a predetermined signal is generated in the external trigger ADTRG, AD is synchronized with the internal clock φ.
The ST set signal is generated and delayed by the latter half clock A
The DST bit is set to "1" and the A / D conversion operation starts.

On the other hand, in the case of driving the motor as described above, a compare match signal or an underflow signal is generated in synchronization with the internal clock φ as shown in FIG. The ADST set signal is generated by the clock of the
The bit is set to "1" and the A / D conversion operation is started.

When the A / D conversion operation is completed, the conversion result is stored in the data register ADDRA, and the ADS
The T bit is cleared to "0", and the change standby state is entered. When the next external trigger signal ADTRG is generated, the ADST bit is set to "1" and AIN0
Input is A / D converted. When the conversion is completed, the data register ADDRA is processed by the buffer operation as described above.
Is transferred to ADDRB and the conversion result is ADD
Stored in RA. Similarly, when the A / D conversion operation is performed four times by the external trigger signal ADTRG four times and the conversion result is stored in the data registers ADDRA to ADDRD, the ADF bit is set to “1” and the conversion is performed. An end interrupt is generated (an interrupt signal ADI is output from the control logic).

When the data transfer device DTC is activated by the conversion end interrupt, the conversion results for four times in the block transfer mode are saved in the RAM. When this is repeated a desired number of times (the number of times set in the DTC counter), the central processing unit CPU collectively processes these pieces of information. When the data alignment of the A / D conversion result is read out by hardware,
When calculating the D conversion result and the correction data, it is not necessary to perform alignment by software, and the burden on the software can be reduced and the speed can be increased. The defocus amount obtained by the above processing is converted into a moving amount (continuous amount) of the AF motor based on the lens information obtained by communication with the lens microcomputer L-MCU or the like. For example, if the amount of data input by the A / D converter is 200, the number of times of transfer by the data transfer device DTC will be 50 times.

Since the data transfer device DTC stores the transfer information in the RAM, it is possible to increase the number of channels, but it is necessary to read the transfer information from the RAM prior to the data transfer. By using buffer operation and block transfer mode, such RAM
It is possible to reduce the overhead such as reading the transfer information from the device and improve the overall processing speed of the single-chip microcomputer. For example, in the case of performing a moving object predictive control of the focus, the photoelectric conversion element and A
Of the focus by the D / D converter and the data transfer device DTC, and the central processing unit CPU based on the previous detection result
When the calculation of the focus is performed in an overlapping manner, it is possible to reduce the frequency of the DTC and the CPU competing for the bus right, restricting each other, and improving the overall processing performance.

The interface circuit has a timing circuit and the like inside and instructs the photoelectric conversion element to transfer the conversion result. When the BUSY signal is active, the transfer instruction is blocked.

FIG. 34 is an address map diagram for reading the A / D converter in the block transfer mode of the data transfer device. The data transfer device DTC includes a data register ADDR in the source address register SAR.
The address of A is set in the destination address register DAR as the start address of the RAM for storing the conversion result. Then, the block transfer mode in which the source side is the block area is designated. The address counter specifies increment. The word size is specified as the data size to obtain 10-bit resolution. Block counter is 4
Set. The transfer counter specifies a predetermined number (N), for example, 50 in the above example.

The A / D conversion interrupt is enabled, the DTE bit is set to "1", and the data transfer device DTC is activated. The A / D converter causes the AIN0 input to be converted using buffering. When the A / D conversion operation is performed four times, the data transfer device DTC is activated by the A / D conversion operation end interrupt, and the data register ADDRA to the first address of the RAM and the data register ADDRB to the second address of the RAM. Data is continuously transferred to the address, from the data register ADDRC to the third address of the RAM, and from the data register ADDRD to the fourth address of the RAM. After that, the interrupt factor flag is automatically cleared to "0". When this is repeated a specified number of times (N), the interrupt factor Fuku is not finally cleared to "0", the DTE bit is cleared to "0", and the central processing unit CPU is requested to issue an A / D conversion end interrupt. The central processing unit CPU can collectively process all the conversion results.

The A / D conversion end interrupt interval can be set to 80 states (20 states × 4) or more. It is possible to relax the activation frequency and the activation interval of the data transfer device DTC to eliminate overhead (read / write register information on the RAM), and to relax constraints during competition with other bus masters. Even when the central processing unit CPU reads the conversion result by interrupt processing or the like without using the data transfer device DTC, overhead such as exception processing and return instruction can be reduced, and the throughput of the entire system is improved. You can

FIG. 35 shows a timing chart of reading of the A / D converter in the block transfer mode of the data transfer device. When the sampling operation of A / D conversion in which the buffer becomes full (all the data registers ADDRA-H store the A / D converted data),
The BUSY signal is activated. When the data transfer device DTC or the central processing unit CPU reads the conversion result and clears ADF Fukugu to “0”, BU
The SY signal becomes inactive.

For example, an external interface circuit monitors this signal, and when the BUSY signal is active, the photoelectric conversion circuit can be stopped or the trigger by the ADTRG signal can be suppressed. by this,
Never lose the analog input conversion. Further, when the A / D converter is in the operable state, the analog input is continuously supplied, and when the A / D converter is in the operation standby state, the analog input is not supplied so that the analog input is not supplied. Can be optimized. In other words, there is no need to tune to the slower one.

The operational effects obtained from the above embodiments are as follows. (1) A / D conversion by 2-bit flash conversion
The conversion speed can be increased, and the reference voltage generation circuit is divided by the D / A converters (voltage divider circuits) of the upper, middle, and circuit to reduce the number of resistors and reduce the physical scale. The effect that it can be achieved is obtained.

(2) By performing flash conversion for every 2 bits to speed up the conversion operation and make it equivalent to the sampling time, the effect that the pipeline operation can be effectively utilized is obtained. That is, the sampling time cannot be shortened below a certain time in order not to lower the sampling accuracy, and the pipeline effect is less effective even if the conversion time is made faster than this.

(3) The A / D converter has a plurality of sets of sample and hold circuits and comparators, the first step performs the first sampling, and the second step performs the first sampling.
Conversion using the sample-and-hold circuit and the comparator and the second sampling are performed. In the third step, the conversion is performed using the second sample-and-hold circuit and the comparator, and the first sampling of the third channel is performed. By performing the sampling, it is possible to reduce the time from the start of the A / D conversion operation to the end of the conversion of all the designated channels. As a result, it is possible to improve the measurement accuracy of a plurality of analog inputs having a high frequency of signal change.

(4) Since the operation of the A / D converter can be detected externally by outputting the BUSY signal when the contents of the data register for storing the conversion result are not read out, the A / D conversion is performed. It is said that the analog input can be sequentially performed when the device is in the operable state, and the analog input can be made to wait when the A / D converter is in the inoperable state (the data register is full), and optimal operation can be performed. The effect is obtained. As a result, the overall processing performance is not deteriorated due to the margin.

(5) The central processing unit CPU and the data transfer unit DTC determine the data size (byte or word) when reading the data register, automatically select the read resolution, and align the read data. By setting the lower bit to the least significant bit of the data bus or the register of the CPU), the effect of reducing the load on software can be obtained. This eliminates the need for the CPU to perform shift processing or overflow detection.
The processing performance of the entire single-chip microcomputer can be improved.

(6) At the time of starting conversion (low speed start) with PWR = "0", the conversion is automatically started after the waiting time, so that the current consumption can be reduced without burdening the software. Further, by returning to the state of low power consumption after the conversion is completed, it is possible to further reduce power consumption.

(7) At the time of starting conversion (high speed start) when PWR = “1”, the time from the conversion start instruction to the completion of sampling can be shortened and the measurement accuracy can be improved. Further, it is possible to shorten the time until the end of conversion to improve the processing performance and improve the real-time property. Since the waiting time can be set by software, the waiting time can be optimized according to the absolute time.

(8) By making it possible to switch between the high-speed start and the low-speed start, it is possible to deal with various usages and improve the usability.

(9) By providing two A / D converters, the reference voltage generation circuit and the control logic can be made common, the physical scale can be reduced, and the current consumption can be reduced accordingly. The effect of being able to be obtained is obtained.

(10) The A / D conversion can be executed in a conversion time equivalent to the number of instruction execution states of the central processing unit, the conversion result can be easily read and processed, and the processing performance of the entire system can be improved. The effect of being able to be obtained is obtained.

(11) As an A / D converter built in a single-chip microcomputer, various effects can be obtained, and various conversions and readings can be performed for each input channel. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the number of analog input channels is not limited to 8 and may be 16 or the like. The number of data registers can be arbitrary. Various changes can be made to the operation mode and the configuration of the control register.

For example, it is not necessary to provide a plurality of sample hold circuits. The read data width is not limited to 8/16 bits, and any bit width may be set. However, it is necessary to determine the data output format and output conditions for an arbitrary bit width. Since the control logic performs only one A / D conversion operation at a time as described above, the comparator array in FIG. 2 may be commonly provided for a plurality of sample hold / level shift circuits. That is, the output of the sample hold / level shift circuit may be time-divisionally transmitted to the common comparator array via the switch.

In order to improve the accuracy of the A / D conversion operation, it is desirable to provide a comparator array in a one-to-one correspondence with the sample hold / level shift circuit as in the above embodiment. Because the input signal is held in the capacitor having a relatively small capacitance value formed in the semiconductor integrated circuit, when the capacitance value of the parasitic capacitance between the capacitor and the comparator array becomes large, This is because the level of the input signal to be compared changes due to the charge dispersion. When the capacitance value of the capacitor is increased, the occupied area increases correspondingly, and it takes time to capture an input signal, which hinders high-speed sampling operation. Further, the A / D converter has two or more sample hold circuits as described above, and simultaneous sampling is not required. That is, A /
It may be anything as long as it has a data register for sequentially storing the D conversion result.

There are no restrictions on other functional blocks of the single-chip microcomputer. The configuration of the timer and the configuration of the data transfer device can be variously changed according to the application system. It goes without saying that the application system is not limited to motor control or automatic focus detection of the camera.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer which is a field of application which is the background of the invention has been described, but the invention is not limited to this and other semiconductors are used. The present invention is also applicable to an integrated circuit device or a data processing device, and the present invention can be widely applied to a semiconductor integrated circuit device including at least a data processing device such as a CPU and an A / D converter and a control system using the same. Is.

[0175]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device having a built-in A / D converter, a plurality of data registers for storing the conversion result in the A / D converter are provided, and the plurality of data registers store the A / D conversion result as the first data register. An operation mode for fetching the A / D conversion result after the data held in the first data register is transferred to the second data register when the data is stored in the first data register is provided.
Alternatively, a mode is provided in which the first A / D conversion result is stored in the second data register and the second A / D conversion result is stored in the second data register. When the data register is saturated by the A / D conversion result in the above operation mode, the operation of the A / D converter is stopped. Then, by restarting the operation of the A / D converter when the reading of the data register is completed in the operation mode,
The conversion results input continuously are not taken out by the central processing unit or data transfer unit one by one, but they can be processed in a batch, which makes it possible to substantially improve the processing capability and to maintain the relationship between them. Can be processed. Also,
The A / D conversion operation can be performed in accordance with these data processes.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of an A / D converter mounted on a single-chip microcomputer to which the present invention is applied.

FIG. 3 is a basic timing diagram for explaining the operation of the A / D converter.

FIG. 4 is a voltage distribution diagram for explaining a subrange voltage conversion method of the A / D converter.

5 is a schematic block diagram of a comparator array in FIG.

FIG. 6 is a circuit diagram showing an embodiment of a sample hold / level shift circuit in FIG.

FIG. 7: A / D by simultaneous sampling according to the present invention
It is a flowchart figure for demonstrating a typical example of conversion operation.

FIG. 8: A / D by normal sampling according to the present invention
It is a flowchart figure for demonstrating a typical example of conversion operation.

FIG. 9 is a timing chart for explaining a select / single mode according to the present invention.

FIG. 10 is a timing chart for explaining a select / scan mode according to the present invention.

FIG. 11 is a timing diagram for explaining a group / single mode according to the present invention.

FIG. 12 is a timing diagram for explaining a group scan mode according to the present invention.

FIG. 13 is a timing chart for explaining an example of a buffer operation according to the present invention.

FIG. 14 is a timing chart for explaining another example of the buffer operation.

FIG. 15 is a timing chart for explaining an example of the simultaneous sampling operation according to the present invention.

FIG. 16 is a timing chart for explaining another example of the simultaneous sampling operation according to the present invention.

FIG. 17 is a timing chart for explaining an interval operation according to the present invention.

FIG. 18 is a schematic flowchart for explaining the operation of the A / D converter according to the present invention.

19 is a block diagram of a main part of a read control circuit including the bus interface of FIG.

20 is a relative address map diagram of the data register of FIG. 2;

FIG. 21 is a circuit diagram of a control circuit when the read control including the bus interface of FIG. 2 is an address method.

FIG. 22 is a bit arrangement diagram for explaining reading of word data and byte data according to the present invention.

FIG. 23 is a diagram showing the data registers ADDRA to ADDR of FIG. 2;
It is a circuit block diagram which shows the mutual relationship of D.

FIG. 24 is a block diagram showing an embodiment of the analog multiplexer of FIG.

FIG. 25 is a block diagram showing another embodiment of the analog multiplexer of FIG.

FIG. 26 is a circuit diagram showing one embodiment of a BUSY output control circuit according to the present invention.

FIG. 27 is a timing chart for explaining the operation of the A / D converter according to the present invention.

FIG. 28 is a block diagram showing an embodiment of a control system using the single-chip microcomputer according to the present invention.

FIG. 29 is a timing chart for explaining an example of operations of the timer B and the A / D converter according to the present invention.

FIG. 30 is a timing chart for explaining another example of the operations of the timer B and the A / D converter according to the present invention.

FIG. 31 is a flow chart diagram for explaining the operation of the single-chip microcomputer according to the present invention.

FIG. 32 is a timing chart for explaining an external input of the A / D converter according to the present invention and a starting operation by a timer.

FIG. 33 is a block diagram showing another embodiment of the control system using the single-chip microcomputer according to the present invention.

FIG. 34 is a read address map diagram of the A / D converter in the block transfer mode of the data transfer device according to the present invention.

FIG. 35 is a timing chart of reading of the A / D converter in the block transfer mode of the data transfer device according to the present invention.

[Explanation of symbols]

CPU: Central processing unit, RAM: Random access
Memory, ROM ... Read-only memory, SCI ...
Serial communication interface, ITU
... Timer, DTC ... Data transfer device (data transfer controller), CPG ... Clock generation circuit, IOP
1-8 Input / output port, ADDRA-ADDRH ... Data register, ADCR, ADCSR ... Control register, B
IF ... Buffer circuit, MDB ... Module bus, DB
... internal data bus, DDR ... data direction register, DR ... data register, MCU ... single-chip microcomputer, L-MCU ... lens microcomputer, M-MCU ... main microcomputer.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hiroyuki Kobayashi 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Business Division, Hitachi, Ltd. (72) Hiroshi Saito 5 Sanmizumoto-cho, Kodaira-shi, Tokyo Hitachi Co., Ltd. Semiconductor Division, 20-201-1 (72) Inventor Mitsumasa Sato 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hiritsuru LSI Engineering Co., Ltd.

Claims (7)

[Claims] 1. A sample hold circuit for taking in a plurality of analog input signals consisting of a part or all of analog signals inputted from a plurality of analog input terminals, and a control logic for instructing the sample hold circuit to perform a sampling operation. An A / D converter having an A / D conversion unit for converting an analog signal taken into the sample hold circuit into a digital signal; and a plurality of data registers for holding the A / D conversion result, An A / D conversion circuit and a central processing unit connected via an internal bus are provided, and when the A / D conversion result is stored in the first data register, the plurality of data registers are connected to the first data register. An operation mode is provided in which the data held in the first data register is transferred to the second data register and then the A / D conversion result is fetched. The semiconductor integrated circuit device characterized by comprising Te. 2. The plurality of data registers also have a signal input system for respectively storing the A / D conversion result independently by setting a predetermined operation mode. 1. A semiconductor integrated circuit device. 3. At least two sample-hold circuits are provided, and the first input signal taken into the first sample-hold circuit by the first operation by the control logic is converted into a digital signal by the A / D converter. The second operation in which the second sampling and holding circuit performs sampling operation on the second input signal in parallel with the operation of converting, and the second input signal taken into the second sample and holding circuit by the second operation In parallel with the operation of converting into a digital signal in the A / D converter, the first input signal is applied to the third input signal.
Third operation in which the sampling and holding circuit performs a sampling operation, and a fourth operation in which the A / D conversion unit converts the third input signal taken into the first sample and hold circuit by the third operation into a digital signal. And the first and third conversion results are stored in one of the first data register and the second data register by the operation mode setting, and the second and fourth conversion results are stored in the other first data register. 3. The semiconductor integrated circuit device according to claim 2, wherein the data is sequentially stored in the first data register and the second data register. 4. The operation of the A / D converter is stopped when the A / D conversion result is stored in all of the plurality of data registers in the operation mode. The semiconductor integrated circuit device according to claim 2 or claim 3. 5. When an A / D conversion result is stored in all of the plurality of data registers in the operation mode, an interrupt signal for instructing reading of the A / D conversion result stored in the data register is generated, When the reading of the data register is completed by such interrupt processing, the above A
The semiconductor integrated circuit device according to claim 4, wherein the operation of the / D converter is restarted. 6. A sample hold circuit for selectively capturing analog signals input from a plurality of analog input terminals, an A / D conversion unit for converting the analog signal captured by the sample hold circuit into a digital signal, and a converted signal. A / D converter having a plurality of data registers for storing digital signals, a central processing unit, a data transfer device, a buffer memory, the A / D converter and the central processing unit, a data transfer device, and A semiconductor integrated circuit device having an internal bus for connecting buffer memories to each other, a sensor controlled by a control signal from the semiconductor integrated circuit device to form an analog signal, and a control signal from the semiconductor integrated circuit device And an interface circuit controlled by the above-mentioned to supply the analog signal to the A / D converter, The semiconductor integrated circuit device stores the A / D conversion result of one or more analog signals in a data register,
When the conversion result is stored in the specified data register,
The data transfer device is activated to save the conversion result stored in the data register in the buffer memory, and when the designated number of times of data transfer is activated, a process of requesting an interrupt to the central processing unit is performed. A control system characterized by the above. 7. The semiconductor integrated circuit device supplies a signal indicating that there is no space in a data register for storing an A / D conversion result to the interface circuit, and stops the operation of the sensor based on the signal. 7. The control system according to claim 6, wherein: