JPH08251143A - Block code decoder - Google Patents

Abstract

PURPOSE: To minimize errors in decoded data and to reduce processing time by receiving error-correcting-block-coded data. CONSTITUTION: Each error correcting block decoding part 7 consists of plural error correcting block decoding parts 71 and 72 correcting errors in mutually different ways. Then based on the detecting result detected by an error detection part 9, a selection part switch-selects each error block decoding part 7 until the error detection part 9 no longer detects an error concerning all the combinations. On the other hand, in the case of using a CRC code as an error detection code, the contribution of an error correction pattern to the CRC remainder of an error correction pattern is previously calculated by each error correction pattern of each block based on selection information from the selection part. Then the selection part is controlled to execute normal CRC remainder execution at the time of first CRC inspection and, after then, to use a decoding part different from an old combination when the selection part changes the combination of each decoding part to a new one.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block code decoding device, and more particularly to a block code decoding device having a function of correcting a transmission error in a transmission device used in the field of PDC (Personal Digital Celler).

[0001]

2. Description of the Related Art FIG. 6 shows an entire transmission apparatus including a conventional block code decoding apparatus (1). On the transmission side of this transmission apparatus, error detection coding section 1 performs error detection coding. The divided data (referred to as frame data) is divided into blocks by the division unit 2 into block data as shown in FIG.

These block data are respectively sent to the corresponding error correction coding units 3 and subjected to error correction block coding, and the data thus coded are combined by the combining unit 4 and output to the transmission line 5. .

On the receiving side receiving such data,
Similar to the transmitting side, the data is divided by the dividing unit 6, each corresponding block data is corrected by the error correction block decoding unit 7, and the decoded data of each block is combined by the combining unit 8 and output as frame decoded data. .

The frame decoded data thus obtained is sent to the error detection section 9, where the error is detected and the detection result is output.

Although the above-mentioned error correction coding / decoding method is publicly known, it will be briefly described by taking BCH (15,11) as an example.

First, on the encoding side, as shown in FIG. 8A, redundant bits are added by BCH (15,11). Since this processing is a regular conversion of 11-bit data into 15-bit data, for example, an input is a ROM address and an output is R
If ROM is prepared in advance as OM data, ROM
Can be realized by reading

By the way, since the redundant bits to be added are uniquely determined by the encoding rule, the input 11 bits and the output 15 bits are 2 11 powers. Originally output 15
If all the bits are used as information bits, 2 @ 15 powers of information can be represented, but redundancy is provided for 4 bits so that correction can be performed when an error is added.

In BCH (15,11), if two different codewords from the 11th power of "2" are selected, the Hamming distance between codewords is always "3" or more as shown in FIG. .

Due to such a property, even if an error of up to 1 bit is added to the code word on the decoding side, the error can be corrected without fail by setting the code word closest to the code word.

That is, for example, in FIG.
B having a 1-bit error added thereto can be corrected to the nearest codeword A. Further, C having a 2-bit error added to the code word A is corrected to the nearest code word D, but this is not a correct decoded value (errors exceeding the correction capability are erroneously corrected).

FIG. 9 shows a configuration example of each block of the error correction block decoding unit 7 shown in FIG. 6. In the operation of the error correction block decoding unit 7, the code word table 11 is shown in FIG. ), The code word number is used as an address and the code word is used as data.

Then, the distance calculation unit 12 calculates the exclusive OR of the input data and the code word from the table 11 as the distance, and as a result, as shown in FIG. Is added (steps S21 to S21 in FIG. 11).
25).

When the distance from the distance calculation unit 12 is given to the storage unit (RAM) 13, the storage unit 13 stores the distance as data using the code word number from the table 11 as an address (step S26).

The search unit 1 finds such distance and code word number.
4, the one having the smallest value is found from the stored distances and the corresponding code word number is output (step S
27, S23, 28, S29).

By giving the codeword number searched in this way to the codeword table 11, the codeword is read out from this table 11 and given to the information bit extracting section 15, and this information bit extracting section 15 is read. At 15, the information bits are taken out as they are and output as shown in FIG. 10 (3) (steps S30 and S31).

In this way, as shown in FIG.
Bits of decoded data are obtained.

FIG. 13 shows an example of the configuration of the error detection unit 9 shown in FIG. 6. In the operation of this error detection unit 9, the same codeword table 31 as the codeword table 11 shown in FIG. 9 is used. Prepare, read the next code word, and compare unit 32
At step S41 to S46 of FIG. 14, read all codewords until they match (steps S43 to S47), and when they match, an error indicating "no error detection" is made. The detection result is output (step S48), and when they do not match, the error detection result indicating "error detected" is output (step S49).

For example, when the minimum distance between codewords is 3 as shown in FIG. 8 (2), B having 1-bit error added to codeword A is not a codeword, so it can be seen that there is an error. . (Error detection).

The same applies to C in which a 2-bit error is added to codeword A. Since D having a 3-bit error added to codeword A is a codeword, no error can be detected.

FIG. 15 shows a conventional block code decoding apparatus (2), in which data sent from a transmission line is divided into block data by a dividing unit 6 in the same manner as in FIG. Is corrected by the error correction block decoding unit 7 and the decoded data of each block is combined by the combining unit 8 and output as decoded data. In this conventional example, in particular,
CRC (error detection code) remainder calculation unit 10
By this, an error is detected by CRC remainder calculation, and the detection result is output.

[0021]

In the above-mentioned conventional example (1), even if an error exceeding the correction capability of the error correction block decoding unit occurs in the block data, the error correction is performed and the information bit is converted. May cause errors,
As a result, the error in the decoded data increases.

Further, no error has occurred in the information bit required as the decoded output, and if the information bit is taken out as the decoded data as it is, there is no error in the decoded data and no error is detected by the error detection unit 2. Even in such a case, an error may be added to the decoded data by the error correction, and the error may be detected by the error detection unit.

The handling of the decoded data when an error is detected differs depending on the application (application), but since the decoded data cannot be trusted, the decoded data is invalid regardless of the error level (number) of the decoded data. In some cases, masking is performed to prevent abnormal noise (in the case of voice), and in any case, an error is detected, which causes a problem that the quality is further deteriorated.

Also, the minimum distance for error correction block coding is
If coding of d = 2t + 2 (t is the number of correctable errors) is used and a block has t + 1 errors, the distance t + 1
There is a problem that it is not possible to determine which codeword should be corrected because there are a plurality of codewords.

Furthermore, in the conventional example (2), the frame data is generated by the polynomial Gcrc (X) for the CRC remainder calculation.
The remainder is obtained by dividing by. FB (x) / Gcrc (X) ・ ・ ・ Equation (1)

Further, since the error detection is judged by comparing the remainder of division with 0, three calculation operations such as feedback calculation, 1-bit shift, and feedback addition are performed to calculate this remainder. Since it is required for each bit, 3 × 88 = 26 in the total of 88 bits in one frame.
There is a problem that the calculation operation is required four times, and the processing takes a long time.

Therefore, according to the present invention, each block data divided from the error detection coded frame data is subjected to error correction block coding by a plurality of block coding units, and the combined data is received to obtain a plurality of data corresponding to each block encoder. In the decoding device of the block code in which the error correction block decoding unit performs error correction decoding, combines and outputs the decoded data, and the error detection unit detects the error from the decoded data, the error in the decoded data is minimized and the processing time is reduced. The purpose is to shorten.

[0028]

Means for Solving the Problems (1) In order to achieve the above object, in a block code decoding device according to the present invention, each error correction block decoding unit has a plurality of errors different in error correction method from each other. A correction block decoding unit is provided, and a selection unit is provided for switching and selecting each error correction block decoding unit for all combinations based on the detection result detected by the error detection unit until the error detection unit no longer detects an error. It is characterized by.

In this case, one of the error correction block decoding units is set as a decoding unit which does not perform error correction, and the selection unit does not perform the error correction for the blocks in which the error detection unit does not detect the error. The error correction block decoding unit can be selected.

Alternatively, each error correction block decoding unit may be a decoding unit that performs error correction decoding on codewords equidistant from each other.

(2) In the invention of the above (1),
When a CRC code is used as the error detection code, a CRC remainder calculation unit and a CRC remainder successive update unit are used in place of the error detection unit, and further, on the basis of the selection information from the selection unit, for each error correction pattern of each block in advance. A CRC contribution storage unit for calculating and storing the contribution of the error correction pattern to the CRC remainder is provided, and in the case of the first CRC check, the CRC remainder calculation unit performs the CRC remainder calculation, and thereafter, the selection unit The selecting unit may be controlled so that when the combination of the decoding units is changed to a new combination, the CRC remainder successive update unit uses a decoding unit different from the old combination.

In this case, when the combination of each block decoding unit is changed to the next combination, the selecting unit determines the combination having the smallest number of blocks different from the current combination from the unused combinations as the next combination. You can choose.

Alternatively, the selection unit selects a combination candidate whose decoding unit differs from the combination candidate of the preceding decoding unit by one block, and when the selected combination candidate is an unused combination, the combination candidate is selected. It is also possible to select a candidate as the next candidate.

[0034]

[Action]

(1) In the present invention, a plurality of error correction block decoding units are provided, the selecting unit selects the decoding unit of each block, and each decoding unit selected in each block decodes each block data.

The error detector detects an error in temporary frame data (a group of decoded data of each block), and outputs it as decoded data when no error is detected.

Further, the error detecting section detects an error in the input decoded data and notifies the selecting section of the result.

In this error detection, when no error is detected, it is estimated that the decoding is correctly performed, and the change of the selection in the selection unit is ended.

Therefore, there exists an erroneous correction decoding unit and a decoding unit that can correctly decode a certain block. In this case, if the latter decoding unit is selected, this block can be decoded correctly, and another block can be decoded. If the frame data can be correctly decoded, the entire frame data can be correctly decoded and the frame data is correct, so that the error detection accuracy is also improved.

Further, the error correction block decoding units can be set in a complementary relationship with each other. That is, when there are, for example, two codewords that are equidistant t + 1 in error correction, the error correction block decoding unit decodes and outputs one of these codewords, and the error correction block decoding unit The other codewords can complement each other as codeword output.

As a result, when an error occurs in a certain block, it can be correctly decoded by any of the decoding units. If the correct part is selected, this block can be correctly decoded, and if other blocks can also be correctly decoded, the entire frame data can be correctly decoded.

As a result, all the code words that are equidistant are used as the candidates of the decoded data of the block, the error detection unit detects the error of the temporary frame data (a group of the decoded data of each block), and if not detected, the decoded data is detected. Will be output as.

Also, even when the equidistant codewords are "3" or more, the number of complementary error correction block decoding units may be used.

(2) In the present invention, for each error correction pattern of each block based on the selection information from the selection unit,
In advance, the contribution of the error correction pattern to the CRC remainder is
It is calculated and stored in the surplus contribution storage unit.

Then, in the case of the first CRC detection, the CRC remainder calculation is performed by the normal CRC remainder part, and thereafter, when the combination of the block decoding parts used for decoding each block is changed to a new (unused) combination. Calculates a new CRC by using the contribution to the CRC remainder and the old CRC remainder brought about by the error correction pattern of the block in which the CRC remainder successive update unit uses a decoding unit different from the old combination.

[0045]

1 shows an embodiment of a block code decoding apparatus (1) according to the present invention. In this embodiment, FIG.
Each error correction block decoding unit 7 in the conventional example (1) shown in FIG.
1 and 72, and switches SW1 and SW2 are inserted between the error correction block decoding units 71 and 72 and the division unit 6, respectively, and these switches SW1 and SW2 are selected together with the selector SEL. The selector SEL switches the switches SW1 and SW2 in all the error correction block decoding units 7 in response to the error detection result output from the error detection unit 9.

In the same way as above, BCH (15,11) can correct all 1-bit errors in each block.
In the conventional example (1), when an error of 2 bits or more occurs in the check bit, the information bit may be erroneously corrected, but in this embodiment, the error correction block decoding units 71 and 72 are On the other hand, for example, if the error correction block decoding unit 71 is the same as the conventional example (1-bit error correction) and the error correction block decoding unit 72 takes out the information bits as they are (in this case, the error correction block decoding unit). If the information bit before decoding is not correctly detected by the error detection unit 9, the decoding unit 72 is selected and used. It is possible to reduce the number of errors in the decoded data.

FIG. 2 is a flow chart showing the operation of the above embodiment (1) of the present invention. When the selector SEL newly selects a decoding section (step S1), the decoding section 71 is the decoding section. Error correction block decoding is performed depending on whether there is a decoding unit 72 or not, and the decoding is output (steps S2 to S).
9).

Then, the error detection unit 9 detects an error in the input decoded data and outputs the result to the selector S.
The EL is notified (steps S10 and S11).

In this error detection, if no error is detected, it is presumed that the decoding was correctly performed and the selector SEL ends the change of selection, so that the processing time is shortened.
Low power consumption is possible.

Further, the error correction block decoding units 71 and 72 can be set to have a complementary relationship with each other.

That is, when there are, for example, two code words that are equidistant t + 1 in error correction, the error correction block decoding unit 71 decodes and outputs one of these code words, and the error correction is performed. The block decoding unit 72 can be configured to complement each other by outputting the other codeword as a codeword.

As a result, all the code words that are equidistant are used as candidates for the decoded data of the block, and the error detection unit 9 performs error detection on the tentative frame data (collection of the decoded data of each block) and decodes them if they are not detected. It will be output as data.

Also, even when the equidistant codewords are "3" or more, the number of complementary error correction block decoding units may be used.

FIG. 3 shows an embodiment of a block code decoding device (2) according to the present invention. In this embodiment, the CRC residue calculation unit 1 in the conventional example (2) shown in FIG. 15 is used.
Instead of 0, a CRC remainder calculation unit 101, a CRC remainder contribution storage unit 102, and a CRC remainder sequential update unit 103 are used.

That is, in the CRC remainder calculation unit 10, FIG.
And, as shown in FIG. 14, the frame data (composed of decoded data of each block) is CRC for each frame.
The CRC calculated by the remainder calculation and the CRC included in the frame data are compared by the CRC comparison unit, and if a mismatch occurs, it is determined that there is an error.

In the embodiment of the present invention, since the CRC remainder successive update unit 103 is used in the CRC remainder calculation, the processing time is shortened and the power consumption is reduced. This will be explained through the data structure shown in FIG. To do.

In the present embodiment, since the selector SEL can select two kinds of decoding units in each block, the selection combination is "2" to the 8th power.

The selection in block i is s
_Let us denote it by _i .

If the selection in the block i for the n-th selection combination is represented by Sn _i , the n-th selection is selection information (vector) Sn = (s ₁ , s ₂ ,, s) by the selector SEL.
₃ , s ₄ , s ₅ , s ₆ .s ₇ , s ₈ ) (n = 1 to 256)

When the frame data decoded by the selection vector Sn is FD (Sn, X), FD (Sn, X) = FR (x) + _{i = 1} Σ ⁸ Ei (sn _i X) (3) FR (x): Frame data without correction sn _i: i-th component of selection vector Sn (i = 1 to 8) Ei (sn _i , X): Block i when decoding with selection vector Sn Correction pattern used for error correction in (Ei (0, X) = 0)

At this time, the CRC remainder calculation unit 1 of FD (Sn, X)
The CRC remainder at 01 is calculated by the following equation. RES (Sn, X) = FD (Sn, X) / Gcrc (X) ・ ・ ・ Equation (4)

In this case, if it is not divisible, an error is detected as in the following equation. RES (Sn, X) = FR (x) / Gcrc (X) + [E ₁ (Sn ₁ , X) + E ₂ (Sn ₂ , X) + ... + E ₈ (Sn ₈ , X)] / Gcrc (X) ・ ・ ・ Equation (5)

On the other hand, the error correction block decoding unit 71 selected by controlling the switches SW1 and SW2 in each error correction block decoding unit 7 by the selection vector Sm.
Alternatively, the CRC remainder of the frame data FD (Sm, X) decoded in 72 is obtained by the following equation by the equation (5). RES (Sm, X) = FR (x) / Gcrc (X) + [E ₁ (Sm ₁ , X) + E ₂ (Sm ₂ , X) + ... + E ₈ (Sm ₈ , X)] / Gcrc (X) ・ ・ ・ Equation (6)

Therefore, from the equations (5) and (6), the following equation is obtained. RES (Sm, X) = RES (Sn, X) + [(E ₁ (Sm ₁ , X) -E ₁ (Sn ₁ , X)) + (E ₂ (Sm ₂ , X) -E ₂ (Sn ₂ , X)) + ... + (E ₈ (Sm ₈ , X) -E ₈ (Sn ₈ , X))] / Gcrc (X) = RES (Sn, X) + [ _{i = 1} Σ ⁸ (Ei (sm _i , X) -Ei (sn _i , X))] / Gcrc (X) ・ ・ ・ Equation (7)

Here, the above error correction block decoding unit 7
If 2 is a decoding unit that does not perform error correction, Ei (0,
Since it is an example of the case of x) = 0 and the case of binary, the following equation (8) is established, paying attention to the point that addition and subtraction are equivalent.

By using the equation (8) in the equation (7), the following equation is obtained. RES (Sm, X) = RES (Sn, X) + _{i = 1} Σ ⁸ (Ei (1, X) / Gcrc (X)) ・ ・ ・ Equation (9)

However, the Σ part of the second term on the right side of the equation (9) is i =
From 1 to 8, it means that Ei (1, X) / Gcrc (X) is added for all _i where sm _i does not match sn _i .

Here, Ei (1, X) is an error pattern used when the block i is decoded by the error correction block decoding unit 71, and is one of 12 types of error patterns shown in Table 1 below ( (Determined by the data of block i) is used.

[0069]

[Table 1]

Therefore, in this embodiment, since the error correction block decoding unit 71 corrects a 1-bit error, there are 11 error patterns for correcting information bits (11 bits), and each block i The contribution Ei (1, X) / Gcrc (X) of all the error patterns j to the CRC remainder is obtained in advance by the following equation with the data of other blocks as all 0s.

This is stored in the CRC remainder contribution storage unit 102, and is stored in the CRC remainder contribution storage unit 102 in the known remainder RES (Sn, X) from the CRC remainder calculation unit 101 by the CRC remainder sequential update unit 103. Added contribution (1-
The error detection result RES (Sm, X) can be calculated by adding 8 times.

By using the equation (10) in the equation (9), the following equation is obtained. RES (Sm, X) = RES (Sn, X) + _{i = 1} Σ ⁸ (cont (i, Ei (1, x), X)) ・ ・ ・ Equation (11)

However, the Σ part of the second term on the right side of the equation (11) is i
= 1 to 8 means adding for all i where Smi and Sni do not match. Since the first term on the right side of this equation (11) is a known value and each term in Σ has already been calculated,
Only the addition is required for the calculation of this formula (11).

FIG. 4 shows an embodiment (1) of the selector SEL used in the embodiments shown in FIGS. 1 and 3.
In this embodiment, the storage unit 21 is used when selecting the next combination.
The selection vector of an unused combination is stored in the storage unit 22, and the selection vector of the current combination is stored in the storage unit 22.

Then, the unused selection vector in the storage unit 21 and the current selection vector in the storage unit 22 are given to the Hamming distance calculation unit 23 to calculate the Hamming distance of the unused selection vector with respect to the current selection vector. It is given to the next combination selection unit 24.

In the next combination selection unit 24, when the error detection result from the error detection unit 9 or the remainder sequential calculation unit 103 indicates “error detection”, the unused selection vector with the smallest Hamming distance from the calculation unit 23. Is output as the next selection information (next selection vector), and the switches SW1 and SW2 in each error correction block decoding unit 7 are controlled.

The next selected vector at this time is updated as the currently selected vector in the storage unit 22 and is deleted from the storage unit 21.

FIG. 5 shows an embodiment (2) of the selector SEL used in the embodiments shown in FIGS. 1 and 3.
In this embodiment, a next combination candidate generation unit 25 is provided, and the generation unit 25 generates a next selection vector by changing only one block from the previous candidate.

When this next selection vector candidate is sent to the next combination selection unit 26, the next combination selection unit 26 finds this next selection vector candidate in the unused selection vector stored in the unused combination storage unit 21. For example, the next combination selection unit 26 outputs this candidate as the next selection vector and deletes it from the storage unit 21, and if this selection vector is not in the unused combination, the next combination candidate generation unit 25 creates a new next selection vector candidate. To occur.

As a result, the next combination selected by the selector SEL has a small number of blocks which are unused and differ from the current combination in the block decoding section, and the number of additions of the equation (11) can be suppressed to a small value, and further processing is performed. Time can be shortened and power consumption can be reduced.

In addition to the above embodiment, the selector SEL
An upper limit may be set for the calculation time by setting a predetermined number of times of changing the selection performed by the above as an upper limit.

Further, it is possible to secure real time by having a timer for notifying when a predetermined time has elapsed from the start of the decoding process and canceling the process by the notification from the timer even during the decoding process. It is possible.

[0083]

As described above, in the block code decoding device according to the present invention, each error correction block decoding unit is composed of a plurality of error correction block decoding units having different error correction methods, Based on the detection result detected by the error detection unit, the selection unit switches and selects each error correction block decoding unit for all combinations until the error detection unit no longer detects an error, so a decoding unit that can correctly decode is selected If you do, you can decrypt this block correctly,
The entire frame data can be correctly decoded, and the frame data is correct, so the error detection also passes.

In the present invention, C is used as the error detecting code.
When the RC code is used, the contribution of the error correction pattern to the CRC residue is calculated and stored in advance for each error correction pattern of each block based on the selection information from the selection unit, and in the case of the first CRC check, Since the normal CRC remainder calculation is performed, and thereafter, when the selection unit changes the combination of each decoding unit to a new combination, the selection unit is controlled to use a decoding unit different from the old combination. It is possible to shorten the time and reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a block code decoding device (1) according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the block code decoding device (1) according to the present invention.

FIG. 3 is a block diagram showing a configuration of a block code decoding device (2) according to the present invention.

FIG. 4 is a block diagram showing an embodiment (1) of a selector used in the block code decoding apparatus according to the present invention.

FIG. 5 is a block diagram showing an embodiment (2) of a selector used in the block code decoding device according to the present invention.

FIG. 6 is a block diagram showing an overall configuration of a transmission device including a conventional block code decoding device (1).

[Fig. 7] Fig. 7 is a diagram illustrating a configuration example of a coded frame that is made into blocks.

FIG. 8 is a diagram for explaining block coding.

FIG. 9 is a block diagram showing a configuration example of an error correction block decoding unit.

FIG. 10 is a diagram for explaining the operation of the error correction block decoding unit.

FIG. 11 is a flowchart diagram for explaining the operation of the error correction block decoding unit.

FIG. 12 is a diagram showing a configuration example of block decoded data.

FIG. 13 is a block diagram showing a configuration example of an error detection unit.

FIG. 14 is a flowchart diagram for explaining the operation of the error detection unit.

FIG. 15 is a block diagram showing a configuration example of a conventional block code decoding device (2).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 error detection coding part 2, 6 division part 3 error correction block coding part 4, 8 coupling part 7, 71, 72 error correction block decoding part 9 error detection part SEL selector SW1, SW2 switch 101 CRC remainder calculation part 102 CRC Residual contribution storage unit 103 CRC residual updating unit In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (6)

[Claims] 1. A plurality of error corrections corresponding to each block encoder by receiving error correction block coding of each block data divided from error detection coded frame data by a plurality of block coding units and receiving combined data. In a block code decoding device in which a block decoding unit performs error correction decoding, combines and outputs decoded data, and the error detection unit detects an error from the decoded data, each error correction block decoding unit has a different error correction method. A plurality of error correction block decoding units, and based on the detection result detected by the error detection unit, each error correction block decoding unit is switched and selected for all combinations until the error detection unit no longer detects an error. A block code decoding device comprising a selection unit. 2. An error in which one of the error correction block decoding units is set to a decoding unit that does not perform error correction, and for a block that the error detection unit does not detect, the selection unit does not perform the error correction. The block code decoding apparatus according to claim 1, wherein a correction block decoding unit is selected. 3. The block code decoding apparatus according to claim 1, wherein each error correction block decoding unit is a decoding unit that performs error correction decoding on code words that are equidistant from each other. 4. When a CRC code is used as the error detection code, a CRC remainder calculation unit and a CRC remainder sequential update unit are used in place of the error detection unit, and further, each block of each block is based on the selection information from the selection unit. For each error correction pattern, a CRC contribution storage unit for calculating and storing the contribution of the error correction pattern to the CRC remainder in advance is provided, and in the case of the first CRC check, the CRC remainder calculation unit performs the CRC remainder calculation, and thereafter, 2. The control unit controls the selection unit so that when the selection unit changes the combination of the decoding units to a new combination, the CRC remainder sequential update unit uses a decoding unit different from the old combination. 4. The block code decoding device according to any one of 3 above. 5. When the selection unit changes the combination of each block decoding unit to the next combination, a combination having the smallest number of blocks different from the current combination is selected from the unused combinations as the next combination. The block code decoding device according to any one of claims 1 to 4, wherein: 6. The selection unit selects a combination candidate of which the decoding unit differs from the combination candidate of the preceding decoding unit by one block, and when the selected combination candidate is an unused combination, the combination candidate is selected. 6. The block code decoding device according to claim 1, wherein a candidate is selected as a next candidate.