JPH08255152A - Moving mean circuit and frequency division ratio equalizing circuit - Google Patents

Abstract

PURPOSE: To provide a moving mean circuit which may consist of a small number of adders and can naturally recover without the continuation of the effect of a disturbance and also to provide a frequency division ratio equalizing circuit which generates a control signal for equally controlling a dual modulus frequency dividing circuit from a given control value. CONSTITUTION: In the moving mean circuit, a selector 88 selects input data at the time of update of latch circuits 80, 82, 84, and 86 and the output of the latch circuit 86 at the time of cumulation. At the time of the cumulation, an adder 90 and a latch circuit 92 cumulates values outputted sequentially from the latch circuit 86. In the frequency division ratio equalizing circuit, on the other hand, a calculating circuit calculates quotients a0 , a1 ,...am when a control value is expressed as 1/(a0 +1/(a1 +...+1/am ) and a reference clock has its frequency divided through the cascade connection of programmable frequency dividers where the calculated values are set as frequency division ratios to generate the control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving average circuit for calculating a moving average of consecutively input numerical values and a dual modulus type divider operating at a dividing ratio selected from two dividing ratios. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency division ratio equalizing circuit for uniformly controlling a frequency divider, and more particularly to a moving average circuit and a frequency division ratio equalizing circuit suitable for providing a high performance and small phase locked oscillator.

[0002]

2. Description of the Related Art SDH (Synchronous Digital Hierarchy), SONET (Synchronous Opti)
In a synchronous multiplex transmission system such as cal NETwork), a highly stable clock that serves as a reference for network synchronization is transmitted from a master station to a slave station, and from there to a next slave station.
Each subordinate station receives a clock signal from the main station or another subordinate station on the side of the main station, generates a clock signal in phase with the clock signal, and propagates the clock signal to the next subordinate station.

Here, the phase-locking characteristic that the phase-locked oscillator of each subordinate station must have is a clock stable enough for the next subordinate station by suppressing the jitter and wander of the clock input from the transmission line. Must be supplied. Generally, phase fluctuations whose frequency is 10 Hz or higher are defined as wander and those whose frequency is 10 Hz or lower are defined as jitter.

As an example, in the case of the NTT synchronous network, since the network is configured so that it can be synchronized with a signal in a narrow frequency range by using a long and highly accurate network synchronizer, a loop band using a microprocessor or the like is used. A narrow phase-locked oscillator is used. On the other hand, in North America etc., the clock is not always supplied from a highly accurate clock supply source, so it is necessary to supply a stable output clock according to the standard while ensuring a wide pull-in frequency range. Since there is no clock supply device, there is a demand for a small phase-locked oscillator that can be mounted in a transmission device.

The phase-locked oscillator targeted by the inventor of the present application is a phase-locked oscillator applicable to the latter. Specifically, the frequency pull-in range is ± 20 ppm, the short-term stability is 5 × 10 ^-9 , that is, the ratio of the wander amplitude of the output clock to the wander amplitude of the input clock is 5 × 10 ^-9 or less, and the jitter Proof strength 1.5UI, 10-150Hz,
That is, the phase variation of the output clock is less than or equal to a required value when a jitter whose amplitude is 1.5 times the clock cycle is input in the frequency range of 10 to 150 Hz, and the size is small.

One of the inventors of the present application has already filed Japanese Patent Application No. 6-343.
In No. 24, a phase-locked oscillator that can satisfy the above requirements was proposed. In the proposed phase locked oscillator, the moving average value of the frequency of the input clock and the moving average value of the phase difference between the input clock and the output clock are calculated in order to obtain the control value for controlling the output clock signal. Two moving average circuits are needed. Further, the control value is the number of times that one of the frequency division ratios should be selected in a predetermined number of times of control in a dual-modulus type frequency division circuit that can select one of the two frequency division ratios, that is, a constant is the denominator. Since it is given in the form of a fraction, a clock signal without jitter / wander is output from the dual modulus frequency divider circuit based on this, so that the division ratio is controlled to be uniform on the time axis. A ratio equalizing circuit is required.

As a moving average circuit, a configuration in which a required number of latch circuits are connected in series and the values latched by the respective latch circuits are added by an adder can be considered first (if the required number is 2 ⁿ , There is no need for a divider.) However, in this configuration, as the number of stages of the latch circuit increases, the number of addition circuits required also increases. For example, if the latch circuit has n stages and the number of bits is 20 bits, (n-1) circuits of 20-bit parallel adders are required.

Japanese Patent Publication No. 57-169874 discloses that an input value is accumulated endlessly, and an input value delayed by a predetermined number of samples by a shift register is subtracted from the accumulated value to subtract one adder from another. A configuration has been proposed in which one unit achieves a predetermined number of additions.

[0009]

However, according to this configuration, if the accumulated value is rewritten due to some influence of noise or the like, the influence remains. Therefore, it is a first object of the present invention to provide a moving average circuit that requires a small number of adders and can be naturally restored without the influence of disturbance continuing.

A second object of the present invention is to provide a frequency division ratio equalizing circuit for generating a control signal for uniformly controlling the dual modulus frequency dividing circuit from a given control value.

[0011]

According to the present invention, a predetermined number of continuous numerical values are stored, and a new numerical value is stored every time a new numerical value is input and the storage is updated. Provided is a moving average circuit including a memory circuit that sequentially outputs everything and an accumulator circuit that accumulates values that are sequentially output from the memory circuit and that are cleared in association with update of a memory in the memory circuit. .

According to the present invention, the dual modulus frequency divider which operates by selecting one of the two frequency division ratios according to the control signal has a distribution of the frequency division ratios on the time axis according to a given control value. A frequency division ratio equalizing circuit for generating a control signal for controlling the control value to be uniform, wherein the control value is 1 / (a ₀ + 1 / (a ₁ + 1 / (a ₂ ... … + 1
/ A _m )) ……) quotient a ₀ , a ₁ , a ₂
A calculation circuit for continuously calculating and outputting a _m , and the plurality of quotients a ₀ , a ₁ , a ₂ ... a _m output by the calculation circuit
Includes a cascade connection of a plurality of programmable frequency dividers each set as a frequency division ratio, and outputs a frequency division output obtained by dividing a reference signal by the cascade connection of the plurality of programmable frequency dividers as the control signal. There is also provided a frequency division ratio equalizing circuit including a control signal generating circuit for performing the same.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows an example of a phase locked oscillator in which the moving average circuit and the division ratio equalizing circuit of the present invention are used. A reference clock (eg 51.84 MHz) from a reference oscillator (not shown) is divided by a dual modulus divider 10 whose division ratio is set to N or N + 1 (N is an integer, eg 33) according to a control signal. It The output of the frequency divider 10 is phase-compared with the input clock (for example, 1.544 MHz) in the phase comparator 12, and when the phase is delayed, the frequency division ratio of the frequency divider 10 is advanced to N (advance control). If it is, N + 1 is set (delay control). On the other hand, the count circuit 14 counts the number of times of advance control (or the number of delay control) in a fixed time (for example, 0.5 seconds). If the operation clock of the phase comparator 12 (for example, the output of the frequency divider 10 is used) is used as a time reference, the total number of times of advance control and delay control within a fixed time is constant. Only (here, the number of advanced controls) should be counted. The number of advance controls counted in the counting circuit 14 is moving averaged in the moving average circuit 16. Here, since the advance control number corresponds to the frequency of the input clock, the moving average of the advance control number corresponds to the average frequency of the input clock. From the moving average value of the advanced control number output from the moving average circuit 16, the central control value calculation unit 18 calculates the central control value of the advanced control number. Details of the calculation of the central control value are described in Japanese Patent Application No. 6-34324, and since they are not directly related to the subject of the present application, they are omitted.

On the other hand, also in the frequency divider 20 having the same structure as the frequency divider 10, the same reference clock is frequency-divided, and the phase of the output and the input clock is compared in the phase comparator 22. In the phase difference measuring circuit 24, the phase comparator 2
A digital value indicating the phase difference can be obtained by counting the master clock using the pulses representing the lead period and the lag period output by 2 as the gate signal. The value of the phase difference output from the phase difference measuring circuit 24 is moving averaged in the moving average circuit 26, multiplied by "phase gain" in the multiplier 28, and the center control value output from the center control value calculator 18 in the adder 30. To obtain the final control value of the advance control number. In order to smooth the control, the frequency division ratio equalizing circuits 32 and 34 are respectively added to the final control value to which a constant Δ (for example, 3) is added and the constant Δ is subtracted.
At respectively, a control signal is generated. If the average phase difference is positive in the selector 36 and the −Δ side is negative, the + Δ side is selected and given to the frequency divider 20.

FIG. 2 shows the detailed structure of the moving average circuit 16 or 26 according to the present invention. For simplicity of explanation, a circuit is shown which computes a moving average over four consecutive samples. Four n-bit latch circuits 80, 82,
84 and 86 are connected in series, the input of the first stage 80 is connected to the output of the selector 88, and the output of the final stage 86 is connected to one input (A input) of the selector 88. Selector 8
The other input (B input) of 8 is connected to a line that supplies input data. The output of the final stage 86 is the adder 9
It is also connected to one input of 0. The output of the adder 90 is n
It is connected to the input of the bit latch circuit 92, and its output is connected to the other input of the adder 90. The output of the adder 90 is connected to the input of another n-bit latch circuit 94, and its output is connected to the input of the division circuit 96. A loop enable signal line is connected to the select input of the selector 88. The loop enable signal line and the memory update signal line are connected to the input of the OR gate 98, and the outputs thereof are connected to the enable inputs of the n-bit latch circuits 80, 82, 84 and 86. A reset signal line and a shift enable signal line are connected to the reset input and the enable input of the n-bit latch circuit 92, respectively. A latch signal line is connected to the enable input of the n-bit latch circuit 94. A clock signal line is connected to the clock inputs of the n-bit latch circuits 80, 82, 84, 86, 92 and 94.

FIG. 3 is a timing chart for explaining the operation of the moving average circuit of FIG. 2, in which the signal states at the portions indicated by reference symbols (i) to (xiv) in FIG. 2 are (i). Shown in ~ (xiv). The operation of the moving average circuit of the present invention will be described with reference to FIGS. First, the n-bit latch circuits 80, 82, and 84 have data "C",
It is assumed that "B" and "A" are held and the input data is "D". The n-bit latch circuit 92 is reset and holds the data "0". In FIG. 3, when the clock signal (i) first rises,
Since the loop enable signal (iii) is at L level, the selector 88 selects the input data input from the B input. Since the memory update signal (ii) is at H level, O
The output (v) of the R gate 98 also becomes H level, and the n-bit latch circuits 80, 82, 84, 86 are enabled. Therefore, in synchronization with the rising edge of the clock signal (i), the input data is input to the first-stage n-bit latch circuit 80.
"D" is held, and data "C", "B", "A" are moved to the n-bit latch circuits 82, 84, 86, respectively. The memory update signal (ii) becomes L level immediately after that in synchronization with the rising edge of the clock. The n-bit latch circuit 92
Since "0" is held (xii), the output of the adder circuit 90 becomes "A" (xiii). The operation up to this point is the memory update operation.

The loop operation starts from the next rising of the clock, and immediately thereafter, the loop enable signal (iii) and the shift enable signal (iv) become H level, and the output (v) of the OR gate 98 also becomes H level again. Return. The selector 88 selects the output of the n-bit latch circuit 86 at the final stage input from the A input. The n-bit latch circuit 92 is also enabled. Therefore, the contents of the latch circuits 80, 82, 84 and 86 rotate through the selector 88 with the rise of the next clock, and the data "B" is output from the n-bit latch circuit 86 at the final stage. On the other hand, the n-bit latch circuit 92 outputs the previous output of the adder circuit 90.
"A" is retained (xii). Therefore, the output (xiii) of the adder circuit 90 becomes "A + B". When the clock (i) rises twice in this state, the latch circuits 80, 8
The contents of 2, 84, and 86 are further rotated through the selector 88, and data is output from the n-bit latch circuit 92 at the final stage.
"C" and "D" are sequentially output, and the output of the adder circuit 90 (xii
i) becomes "A + B + C + D". Almost at the same time, the shift enable signal (iv) returns to the L level, so that the n-bit latch circuit 92 is disabled, while the latch signal (vi) becomes the H level, the n-bit latch circuit 94 is enabled. Become. Also, reset signal
(vii) becomes L level (valid). Therefore, the output of the adder circuit 90 "A + B +
C + D "is transferred to the n-bit latch circuit 94 (xiv), and the n-bit latch circuit 92 is reset to" 0 "(xii).
After that, when the memory update signal (ii) becomes H level, new input data "E" is taken into the first stage n-bit latch circuit 80 at the next rising edge of the clock. After that, by executing the loop operation as described above, "B + C + D + E" is output from the n-bit latch circuit 94.
By dividing the output of the n-bit latch circuit 94 by 4 in the division circuit 96, a moving average value of four consecutive samples can be obtained. As described above, the number of samples is 2 ⁿ
, The division circuit 96 is unnecessary.

FIG. 4 shows the division ratio equalizing circuit 32 or 3 of FIG.
4 shows the configuration of No. 4. Calculation circuit 100 advances the control number entered, (the control advances count) / (total number of controls _{(fixed)) = 1 / (a 0} + 1 / (a 1 + 1 / (a 2 + ...... + 1 / a m) ) ...), the quotients a ₀ , a ₁ , a ₂ ... _Am are calculated and output. The control signal generation circuit 102 receives the quotient a ₀ ,
a _1, a ₂ ... a a _m is set to cascaded programmable frequency divider, then outputs the divided output is outputted as a frequency division ratio control signal.

FIG. 5 is a diagram showing the configuration of the calculation circuit 100. The dividend input of the division circuit 104 is the latch circuit 106.
, And the divisor input is connected to the output of the latch circuit 108. The input of the latch circuit 106 is the selector 11
0, and the input of the latch circuit 108 is connected to the output of the selector 112. The selector 110 selects one of the total control count (fixed) and the output of the latch circuit 108.
Select one to output. The selector 112 selects one of the input control value of the advance control count and the remainder output of the division circuit 104. The quotient output of the divider circuit 104 is connected to the inputs of the latch circuits 114, 116 and 118.

The operation of the calculation circuit of FIG. 5 will be described. the first
In addition, the selectors 110 and 112 both select the A input
Therefore, the latch circuits 106 and 108 each have a total
The control count and the advance control count control value are latched. division
The circuit 104 is a total control circuit input from the latch circuit 106.
The number is the dividend and the advance control input from the latch circuit 108
The division is performed with the number of times as the divisor, and the quotient a₀And output the remainder
It Quotient a₀Are latched by the latch circuit 114. next,
Selectors 110 and 112 both select the B input,
The divisor and remainder in the previous division selected are respectively
The latch circuits 106 and 108 as dividends and divisors.
Latched. The division circuit 104 inputs the dividend and
The division is performed on the divisor and the quotient a₁And output remainder
I do. Quotient a ₁Are latched by the latch circuit 116. this
The processing is performed until the remainder output from the division circuit 104 becomes zero.
Quotient a by repeating with₀, A₁, A₂... a_mIs la
Output. The division circuit 104 is
Divisor cannot be subtracted from the resulting dividend because the result is negative.
Iteratively subtracts until
Can be configured to output the rest of
It

FIG. 6 shows the structure of the control signal generation circuit 102 of FIG.
Indicates success. Programmable frequency divider D ₀, D₁, D₂... D
_nIs the quotient a from the calculation circuit 100.₀, A₁, A₂... a_m
Are respectively set as frequency division ratios. The total control count
The maximum value of m can be determined if is given
To prepare the required number of programmable frequency dividers.
Can be.

The reference signal is input to the frequency divider D _{0 for} which the quotient a ₀ is set, and the frequency division output d ₀ is output as the frequency division ratio control signal. Divided output d ₀ is also input to the divider D ₁ of the quotient a ₁ is set as the division ratio, the division ratio periodically a ₀ frequency divider D ₀ by the divided output d ₁ It is changed to a ₀ +1. More specifically, the frequency divider D ₁ has a frequency division number a.
_{While 1} (or a ₁ +1) has been counted and the carry is output, the frequency division ratio of the frequency divider D ₀ is changed to a ₀ +1. Further, the frequency division output d ₁ is also given to the frequency divider D ₂ as a frequency division input. Similarly, the frequency divider D _i (2 ≦ i ≦ m−
The frequency division output d _{i-1 of the} frequency divider D _i-1 is input to 1), and the frequency division ratio of the frequency divider D _i-1 is periodically changed from a _i-1 by the frequency division output d _i . Change to a _i-1 +1. The frequency division output d _i is also given to the frequency divider D _{i + 1} as a frequency-divided input. Divider D
Similarly for _m , the frequency division output d _i-1 from the frequency divider D _{m -1}
Although is inputted, the dividing ratio a _m is not changed until the value of a _m is updated.

In order to simplify the explanation, the total number of control times is 16
The operation of the frequency division ratio equalizing circuit of the present invention will be described for the case where the control value of the advance control count is 7. 7/16 = 1 / (2 + 1 / (3 + 1/2)) in the calculation circuit 100 are the a ₀ = 2, a ₁ =
3, a ₂ = 2 is determined. The operation of the control signal generation circuit in this case is shown in FIG. In FIG. 7, the frequency division ratios of the frequency dividers D ₀ and D ₁ are a ₀ +1 (= 3) and a ₁ +1 (= 4), respectively.
The transition of the count value inside each of the frequency dividers D ₀ , D ₁ , and D ₂ immediately after being changed to is shown. The downward arrow indicates that the count of the divider one step lower is increased due to the carry, and the upward arrow indicates that the advance control is performed due to the occurrence of the carry (divider D ₀ ), or It shows that the frequency division number of the one-step higher frequency divider is increased by one. Although only 16 clocks are shown in the figure, this pattern is repeated. As is clear from the figure, it can be seen that the control is advanced evenly among the 16 times of control.

[0024]

As described above, according to the present invention,
The moving average circuit can be configured by using one adder circuit, and the accumulated value for that purpose is cleared each time, so that even if the accumulated value is changed by a disturbance, the effect does not continue. Further, the dual modulus frequency dividing circuit can be uniformly controlled.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase-locked oscillator in which a moving average circuit and a division ratio equalizing circuit of the present invention are used.

FIG. 2 is a circuit diagram showing a configuration of a moving average circuit of the present invention.

FIG. 3 is a timing chart showing the operation of the circuit of FIG.

FIG. 4 is a block diagram showing a configuration of a frequency division ratio equalizing circuit of the present invention.

5 is a circuit block diagram showing a configuration of a calculation circuit of FIG.

6 is a circuit block diagram showing a configuration of a control signal generation circuit of FIG.

FIG. 7 is a timing chart for explaining the operation of the frequency division ratio equalizing circuit of the present invention.

[Explanation of symbols]

 10, 20 ... Dual modulus frequency dividing circuit 12, 22 ... Phase comparator 16, 26 ... Moving average circuit 32, 34 ... Frequency division ratio equalizing circuit

Claims (7)

[Claims] 1. A storage circuit for storing a predetermined number of consecutive numerical values and sequentially outputting all the stored numerical values each time a new numerical value is input and the storage is updated, and the storage circuit. Cleared in connection with memory updates in
A moving average circuit comprising: an accumulator circuit that accumulates numerical values sequentially output from the storage circuit. 2. The data storage circuit comprises a data holding circuit having a predetermined number of serially connected data latch circuits for latching and outputting an input numerical value, and a new data storage circuit when the memory of the memory circuit is updated. A selection circuit for selecting a numerical value and giving it to the input of the data holding circuit and, when sequentially outputting numerical values stored in the storage circuit, selecting the output of the data holding circuit and giving it to the input of the data holding circuit; 2. The moving average circuit according to claim 1, including: 3. The data latch circuit, wherein the accumulator circuit is cleared in association with the update of the memory in the memory circuit and latches and outputs the input numerical value, and the numerical value output from the memory circuit and the numerical value. 2. The moving average circuit according to claim 1, further comprising an adder circuit for adding the numerical value output from the data latch circuit and giving the sum to the input of the data latch circuit. 4. A dual-modulus frequency divider that operates by selecting one of two frequency division ratios according to a control signal has a uniform distribution of frequency division ratios on the time axis according to a given control value. A frequency division ratio equalizing circuit for generating a control signal for controlling the control value from the input control value to 1 / (a ₀ + 1 / (a
_{1 + 1 / (a 2 +} ...... + 1 / a m)) and the quotient _{a 0, a 1, a 2} ...... a m a calculating circuit for continuously calculated and output when expressed in ...), the The plurality of quotients a ₀ , a ₁ , a ₂ ...
a _m includes a cascade connection of a plurality of programmable frequency dividers, each of which is set as a frequency division ratio, and a frequency division output obtained by dividing a reference signal by the cascade connection of the plurality of programmable frequency dividers is the control signal. And a control signal generating circuit for outputting as a frequency division ratio equalizing circuit. 5. The calculation circuit repeats dividing a quotient a ₀ when a denominator of a fraction corresponding to the control value is divided by a numerator and a previous divisor until the remainder becomes 0. sequentially obtained quotient a _1, a ₂ ... a _m by
The division ratio equalizing circuit according to claim 4, wherein Wherein said control signal generating circuit, the calculated quotient a ₀ which circuit outputs, a ₁ ... a _m is more programmable frequency divider D ₀ which are set as respective division ratios, D ₁ ... D
_{In the} frequency divider D ₀ , a frequency-divided output d ₀ obtained by frequency-dividing a reference signal is output as the control signal, and the frequency is a value when i is any of 1 to m−1. In the frequency divider D _i , the frequency-divided output d _i-1 of the frequency divider D _i-1 is frequency-divided, the frequency-divided output d _i is input to the frequency divider D _{i + 1,} and the frequency-divided output d _i is also input. _The frequency division ratio of the frequency divider D _i-1 is periodically a _i-1 + by _i
1 and, in the case of the frequency divider D _m , the frequency divider D _m-
Dividing according to claim 4, wherein changing the _first frequency division output d _m-1 the frequency division ratio the divided output by d _m of the frequency divider D _m-1 of the dividing perilla periodically to a _m-1 +1 Ratio equalization control circuit. 7. The division circuit divides a dividend by a divisor and outputs a quotient and a remainder, and a first latch circuit which latches an input numerical value and outputs it to the division circuit as a dividend. A second latch circuit that latches the input numerical value and outputs it to the division circuit as a divisor, and the first latch circuit that selects one of the value of the denominator and the output of the second latch circuit. 6. A first selection circuit for inputting to the second latch circuit, and a second selection circuit for selecting one of the value of the numerator and the remainder output of the division circuit and inputting it to the second latch circuit. Frequency division ratio equalization control circuit.