JPH08236698A - Semiconductor device - Google Patents

Abstract

PURPOSE: To increase the capacitance without increasing the area on a semiconductor substrate being occupied by an MIM capacitor. CONSTITUTION: An MIM capacitor 7 is formed integrally in a via hole 6 of a substrate 1 while partially extending onto the rear surface of the substrate 1. Consequently, an MIM capacitor 7 having high capacitance can be obtained by occupying an area required only for a via hole 6 on the surface of the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MIM (Metal-Insulator-Meta).
l) The present invention relates to a semiconductor device having a capacitor.

[0002]

2. Description of the Related Art FIGS. 2A and 2B are views showing an example of a conventional semiconductor device of this type. FIG. 2A is a sectional view thereof, and FIG. 2B is a plan view thereof. Referring to the figure, the semiconductor substrate 1 is provided with a via hole 6 penetrating from the front surface to the back surface thereof. The via hole 6 is for electrically connecting the metal wiring layer 2 on the front surface of the semiconductor substrate 1 and the metal layer 10 on the back surface.

An MIM capacitor 7 is formed on the surface of the semiconductor substrate 1, a lower electrode 5 of this capacitor is adhered to the surface of the substrate, and a dielectric layer 4 and an upper electrode 3 are formed thereon. They are formed in this order. The lower electrode 5 is connected to the back surface metal layer 10 via the wiring layer 2 and further via the via hole 6. The upper electrode 3 is electrically connected to, for example, a bias line 9 which is circuit wiring selectively formed on the surface of the substrate 1.

Such an MIM capacitor 7 is used as a high-frequency short-circuit capacitor 16 in the bias circuit of the high-frequency amplifier circuit shown in FIG. 3, for example. In FIG. 3, 11 is an input terminal, 12 is an output terminal, 13 is a power supply terminal, 14 and 15 are DC cut capacitors, 17 is a resistor for a gate source bias potential of a transistor 19, and 18 is a resistor.
Indicates an RF (high frequency) cutting inductor, and 19 indicates a field effect transistor.

As described above, in order to provide the high frequency short circuit in the bias circuit in the high frequency circuit, the MIM capacitor 7 is formed in the vicinity of the bias line 9 and further the MIM capacitor 7 is formed.
A via hole 6 is formed in the vicinity of and the bias line 9 is grounded at a high frequency.

[0006] As another conventional example, the actual development of Sho 61-1001
No. 53, a MIM capacitor as shown in FIG. 4 is disclosed. A dielectric 4 is formed in a via hole 6 provided in a semiconductor substrate 1, and upper electrodes 3 are formed on the upper and lower surfaces of the dielectric, respectively. And the lower electrode (back surface metal layer) 10 are connected to each other to be formed.

In this structure, the MIM is formed in the via hole 6.
Since the capacitor is formed, there is an advantage that the both are integrated and the occupied area is reduced. However, in order to increase the capacitance of the capacitor, it is necessary to increase the area of the via hole 6, which is not efficient.

In view of this, Japanese Patent Laid-Open No. 3-99461 proposes a technique for constructing an MIM capacitor by utilizing not only the bottom of the via hole 6 but also the entire peripheral side surface as shown in FIG. That is, the lower electrode layer 5, the dielectric layer 4, and the upper electrode layer 3 are formed on the entire surface of the semiconductor substrate 1 along the bottom portion of the via hole 6 and the sidewalls around the via hole 6.
Are formed in this order.

By doing so, the capacitance of the MIM capacitor can be realized with a small occupied area.

[0010]

In the conventional MIM capacitor having the structure shown in FIG. 2, when the bias circuit is used as a high frequency short circuit for grounding in high frequency, MI
Since the M capacitor portion 7 and the via hole portion 6 are physically formed in separate places, a large area is required on the semiconductor substrate.

Normally, when the MIM capacitor for the bias circuit is 20 pF, the outer dimensions of the MMI capacitor portion 7 are about 284 × 284 μm, and the outer dimensions of the via hole portion 6 are about 150 × 150 μm. Therefore, there is a drawback that it becomes an obstacle to miniaturization of the semiconductor device.

In the conventional example of FIG. 4, the area of the via hole of about 284 × 284 μm is required, and in the conventional example of FIG. 5, the area can be made smaller than that in the case of FIG. Not enough to make area.

An object of the present invention is to provide a semiconductor device capable of obtaining a large capacitance value by making the area occupied by the MIM capacitor on the surface of the semiconductor substrate equal to the area occupied by one via hole. is there.

[0014]

A semiconductor device according to the present invention comprises a semiconductor substrate, a via hole penetrating from the front surface to the back surface of the semiconductor substrate, and an inner peripheral surface of the via hole. The dielectric layer formed on the back surface of the semiconductor substrate and extending over the back surface of the semiconductor substrate, the first electrode formed on the top surface of the dielectric layer, and exposed from the via hole on the front surface of the semiconductor substrate. And a second electrode formed on the upper surface of the dielectric.

[0015]

In addition to using the entire area of the peripheral side wall portion in the via hole as the capacitor area, the back surface of the semiconductor substrate is also used to increase the capacitance value of the capacitor, and the MIM capacitor is occupied on the substrate surface. The area is simply the area of the via hole.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.
(A) is a sectional view thereof, and (B) is a plan view thereof. still,
In the figure, the same parts as those in FIG. 2 are designated by the same reference numerals.

A via hole 6 is formed in the semiconductor substrate 1 so as to penetrate the front surface and the back surface thereof, and a metal wiring layer 2 is formed on the via hole 6 on the front surface of the substrate so as to cover the via hole 6. ing. An upper electrode layer 6 and a dielectric layer 4, and further a lower electrode layer 5 are formed in this via hole 6 in this order in contact with the wiring layer 2 and in contact with (along with) the entire sidewall of the via hole. There is.

The upper electrode layer 3, the dielectric layer 4 and the lower electrode layer 5 are formed on the inner peripheral surface of the via hole 6 as well as on the substrate 1.
Is also formed by being extended on the back surface of the substrate 1, so that the capacitance value which is insufficient with respect to the capacitance value inside the via hole 6 is satisfied by the capacitor structure extended on the back surface of the substrate 1. There is.

The metal wiring layer 2 in contact with the upper electrode layer 3 is connected to the bias line 9 on the surface of the substrate, and the high frequency short-circuit capacitor 16 shown in FIG. 3 is formed.

If the MIM capacitor for high frequency short circuit is realized with 20 pF by the conventional method shown in FIG. 2, the occupying area is about 284 × 284 μm and the via hole portion is about 150 × 150 μm, as described above. An area of 103,210 μm ² is required.

On the other hand, in the example of FIG. 1, the substrate thickness is 1
If the via hole diameter is 80 μm and the via hole inner diameter is 80 μm, the total surface area of the via hole inner surface is 37,650 μm ² , and if a 65,560 μm ² capacitor is further formed on the back surface of the substrate 1, a 20 μF MIM capacitor is obtained. The occupied area on the surface of the substrate 1 required at that time is only the metal wiring layer 2 which covers the via hole 6.
Only 50 μm square. Therefore, it is reduced to about 1/4 of the conventional one.

In the above embodiment, an example of use in a high frequency short circuit is shown, but it is clear that it can also be used in a short stub of a matching circuit.

For the calculation of the capacitance value C of the MIM capacitor, the equation C = ε0εrS / d = 0.0885 × 10 ^-6 × 7 × S / 2500 was used. Where ε0 is the dielectric constant of vacuum, εr is the relative dielectric constant of the dielectric, S is the total area of the capacitor (cm ² ), d
Is the dielectric thickness (angstrom).

[0025]

As described above, according to the present invention, since the MIM capacitor is formed not only in the via hole but also on the back surface of the substrate, the area occupied on the substrate surface is only the area of the via hole portion. Therefore, there is an effect that the area can be greatly reduced, the size area of the semiconductor chip is reduced, and the size and cost can be reduced.

Further, since the via hole and the MIM capacitor are integrally formed, the MIM capacitor can be grounded directly in the shortest distance, and therefore, it is possible to minimize the appearance of an unnecessary inductance component in the high frequency short circuit. A wide band of the characteristics of the high frequency circuit can be achieved. Furthermore, M
Even if the capacitance of the IM capacitor is large, it does not affect the area of the substrate surface, so that it is easy to increase the capacitance of the MIM capacitor and increase the high frequency short circuit capability.

[Brief description of drawings]

1A is a cross-sectional view of an embodiment of the present invention, and FIG. 1B is a plan view thereof.

FIG. 2A is a cross-sectional view of a conventional MIM capacitor,
(B) is the top view.

FIG. 3 is a diagram showing an example of a high frequency circuit.

FIG. 4 is a cross-sectional view of another conventional MIM capacitor.

FIG. 5 is a sectional view of still another conventional MIM capacitor.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Metal Wiring Layer 3 Upper Electrode Layer 4 Dielectric Layer 5 Lower Electrode Layer 6 Via Hole 7 MIM Capacitor

Claims (2)

[Claims] 1. A semiconductor substrate, a via hole penetrating from the front surface to the back surface of the semiconductor substrate, and an inner peripheral surface of the via hole and further extending onto the back surface of the semiconductor substrate. And a first electrode formed on the upper surface of the dielectric layer, and a second electrode formed on the upper surface of the dielectric exposed from the via hole on the surface of the semiconductor substrate. A semiconductor device comprising an electrode. 2. The semiconductor device according to claim 1, wherein an MMI capacitor is constituted by a dielectric layer in the via hole and a dielectric layer formed by extending on the back surface of the semiconductor substrate. apparatus.