JPH08222703A - Semiconductor device - Google Patents

Abstract

PURPOSE: To improve the protection performance of a semiconductor device, which is provided with a protective element for protecting an internal element from an excessive input, without increasing the chip size. CONSTITUTION: An external lead-out electrode layer 22A is formed in the vicinity of the end edge of a semiconductor substrate 10 via insulating films 12 and 20. The layer 22A is connected with an internal element via a wiring layer 24A. An insulating film 26 is formed in such a way as to cover the layers 22A and 24A, and a connection hole 26a is provided in the film 26 for making the connection of bonding wires 28 with the layer 22A possible. A protective element, such as a lateral bipolar transistor BT forms around the hole 26a except the area directly under the hole 26a, and is connected with the layer 22A via one or a plurality of connection holes 20a provided around the hole 26a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC (integrated circuit) device provided with a protection element for protecting an internal element from an excessive input such as surge and static electricity, and particularly to an electrode layer for external lead-out. The protection performance is improved without increasing the chip size by arranging the protection element around the area directly under the area.

[0002]

2. Description of the Related Art Conventionally, as an IC device having an input protection circuit, one shown in FIG. 10 is known.

A square semiconductor substrate (semiconductor chip) 1
A protected circuit 2 including an internal element such as a MOS transistor is formed in the central portion of the substrate 1, and a large number of external lead-out electrode layers (bonding pads) 3 are provided in the vicinity of the edge of the substrate 1. ing. An input protection circuit 4 is disposed between each input electrode layer of the multiple electrode layers 3 and the protected circuit 2 as shown in an enlarged view in FIG.
A and 5B connect to the electrode layer 3 and the circuit 2, respectively.

12 and 13 show examples of different configurations of the input protection circuit 4. In the example of FIG. 12, the PN junction diode D is provided between the pair of power supply lines V _DD and V _SS.
1 and D ₂ are connected in series, the electrode layer 3 is connected to the connection point of the diodes D ₁ and D ₂ via a resistor R, and the connection point is connected to the gate electrode or the like of the MOS transistor in the circuit 2. There is. In this case, the positive overvoltage is absorbed by the diode D ₂ and the negative overvoltage is absorbed by the diode D ₁ . Therefore, internal elements such as MOS transistors are
Protected from excessive input.

On the other hand, in the example of FIG. 13, the electrode layer 3 is connected to the drain and gate of the N-channel MOS type transistor T, and the source of the transistor T is connected to the electrode line V.
Diffusion resistance R consisting of N-type diffusion layer connected to _SS and electrode layer 3
_The P-type layer connected to the gate electrode of the MOS-type transistor in the circuit 2 via _D and forming a PN junction with the diffusion resistor R _D is connected to the power supply line V _SS . Normally, as the transistor T, one having a gate insulating film thicker than the gate insulating film of the MOS type transistor in the protected circuit 2 is used.

In the circuit of FIG. 13, the positive overvoltage is absorbed by the transistor T, and the negative overvoltage is absorbed by the PN junction of the diffusion resistor R _D. Therefore, internal elements such as MOS transistors are protected from excessive input.

According to the above-mentioned conventional technique, it is necessary to increase the size of the protective element such as the resistor, the diode and the transistor in order to enhance the protective function, which inevitably leads to an increase in the chip size.

In order to cope with such a problem, it has been proposed to form a protection element such as a polysilicon resistor or a PN junction diode directly under the electrode layer 3 (for example, Japanese Patent Laid-Open No. 4-206767). JP-A-4-206768
No.

However, according to such a conventional technique, when the wire bonding is performed on the electrode layer 3, the protective element may be deformed or destroyed by pressure or heat, and a sufficient protective function can be obtained. There was nothing.

An object of the present invention is to provide a novel semiconductor device capable of improving the protection performance without increasing the chip size.

[0011]

A semiconductor device according to the present invention includes a semiconductor substrate having an internal element to be protected, a first insulating film formed on the surface of the semiconductor substrate, and the internal element. An electrode layer for leading out the electrode of the semiconductor substrate to the outside, the first electrode being near the edge of the semiconductor substrate.
A second insulating film formed on the insulating film and a second insulating film formed on the first insulating film so as to cover the electrode layer and enable connection of external wiring to the electrode layer. And a protection element for protecting the internal element from an excessive input input to the electrode layer, the connection element being formed on the semiconductor substrate so as not to be located directly below the connection hole. Formed around the hole and connected to the electrode layer.

[0012]

According to the structure of the present invention, since the protection element is provided around the connection hole so as not to be located directly below the connection hole, an increase in the chip size can be avoided and the area inside the electrode layer (conventional input protection). Internal elements and the like can be formed in the area where the circuit was located). Further, pressure and heat do not adversely affect the protection element during wire bonding, and good protection performance can be obtained.

[0013]

1 and 2 show a semiconductor device according to an embodiment of the present invention, and FIG. 1 shows a cross section taken along line XX 'of FIG.

On the surface of the semiconductor substrate 10 made of, for example, square P-type silicon, as in the case of FIG.
A protected circuit (not shown in FIGS. 1 and 2) including an internal element such as an S-type transistor is formed, and an electrode layer (bonding pad) 22A for external lead-out is formed on the surface near the edge of the substrate 10. , 22B are formed via the insulating films 12 and 20. The electrode layers 22A and 22B are connected to the gate electrodes and the like of the MOS type transistors in the protected circuit via the wiring layers 24A and 24B, respectively.

When the protected circuit includes a MOS type IC,
The insulating film 20 may be an interlayer insulating film between the gate electrode layer of the MOS transistor and the wiring layers such as 24A and 24B.

On the insulating film 20, electrode layers 22A, 22A
A protective insulating film 26 is formed so as to cover B and the wiring layers 24A and 24B, and the insulating film 26 is provided with connection holes 26a and 26b for connecting the bonding wires 28 to the electrode layers 22A and 22B, respectively. .

A lateral bipolar transistor BT as a protection element is formed around the connection hole 26a on the surface of the substrate 10 so as to surround the connection hole 26a.
In this transistor BT, 14A is a collector region consisting of impurity-doped region of N ⁺ -type, 16A is an emitter region formed of impurity-doped region of N ⁺ -type, P-type region between the region 14A and 16A is the base region, 18 P ^A base terminal region made of a ⁺ type impurity-doped region, 24C is a wiring layer (ground terminal layer) which short-circuits the regions 16A and 18 with a large number of contact portions CN _c and is connected to the power supply line (ground line) V _SS. . In addition, in FIG.
Reference numeral b indicates a connection hole corresponding to the contact portion CN _c .

In the impurity-doped region 14A, a large number of connection holes 20a corresponding to _a large number of contact portions CNa are formed in the insulating films 12 and 20 so as to surround the connection holes 26a. The electrode layer 22A is connected to the N ⁺ type region 14A in a multi-point dispersed manner through a large number of connection holes 20a. Connection hole 2
0a (i.e. contact portion CN _a) is connecting hole 26a
It may be one surrounding. In this case, the electrode layer 22A is N ^{+ in} a loop contact state through one connection hole.
It is connected to the mold area 14A. When the electrode layer 22A is thus connected to the N ⁺ type region 14A in a multi-point dispersive manner or in a loop contact state, an excessive input is spread radially from the electrode layer 22A and is absorbed by the transistor BT.

FIG. 3 shows an equivalent circuit of the transistor BT. In the transistor BT, the collector is connected to the electrode layer 22A, and the base and the emitter are connected together to the power supply line V _SS .

With respect to other connection holes such as 26b, the transistor B is formed for each connection hole in the same manner as the connection hole 26a.
T is formed. In FIG. 2, 14B and 16B shown with respect to the connection hole 26b are an N ⁺ type collector region and an emitter region, respectively.

Between the connection holes 26a and 26b, P
⁺ With -type region 18 is formed so as to contact with both the N ⁺ -type regions 16A and 16B, a short circuit and the N ⁺ -type region 16 of the wiring layer 24C is N ⁺ type region 16A and the P ⁺ -type region 18
It is commonly used for short-circuiting the B and P ⁺ type regions 18. According to such an arrangement, the electrode layer 22A
22B can be narrowed, and the number of pads can be increased.

In manufacturing the device of FIG. 1, the following method can be used as an example. That is, the surface of the silicon substrate 10 is selectively oxidized to be thick (for example, 5
00 nm) an insulating film 12 made of a silicon oxide film,
12a is formed. Further, the surface of the silicon substrate 10 is oxidized to form a thin silicon oxide film connected to the insulating films 12 and 12a.

Next, the resist layer and the insulating films 12 and 12a
By a selective impurity doping process using a mask as N ⁺
The mold regions 14A, 14B, 16A, 16B are formed. Then, the P ⁺ type region 18 is formed by the impurity doping process using the resist layer as a mask. Ion implantation or the like can be used as the impurity doping treatment.

Next, the insulating film 20 made of silicon oxide or the like is formed on the upper surface of the substrate by the CVD (chemical vapor deposition) method or the like. Then, the contact portion C is formed on the insulating film 20 and the thin silicon oxide film thereunder by known photolithography and selective etching.
N _a, the connection hole 20a corresponding to the CN _c, to form a 20b.

Next, a wiring material is deposited on the upper surface of the substrate, and the deposited layer is patterned to form wiring layers 24A, 24B, 24C.
And the electrode layers 22A and 22B are formed. And CVD
An insulating film 26 made of silicon oxide, silicon nitride, or the like is formed on the upper surface of the substrate by a method or the like, and connection holes 26a and 26b are formed in the insulating film 26 by photolithography and selective etching. Most of the steps up to this point can be applied to the manufacturing steps of the MOS type IC as the protected circuit.

After the semiconductor wafer that has undergone the above-mentioned processing is divided into IC chips, each IC chip is fixed to a lead frame. Then, using a wire bonder, 22A,
Each electrode layer such as 22B is connected to a corresponding lead on the lead frame by a bonding wire 28. At this time, 2
Transistors BT are provided immediately below the respective connection holes such as 6a and 26b.
Since it does not exist, it is possible to prevent deterioration of the protective performance due to pressure or heat.

The device of FIG. 1 operates as follows. First, when a positive overvoltage is applied to the electrode layer 22A, the N ⁺ -P junction (collector junction) between the region 14A and the substrate causes avalanche breakdown to absorb the overvoltage. The minority carriers (holes) generated at this time are effectively collected in the region 16A. Further, when a negative overvoltage is applied to the electrode layer 22A, the diode composed of the collector junction conducts in the forward direction to absorb the overvoltage. Therefore, internal elements such as MOS transistors are protected from excessive input.

According to the device of FIG. 1, since the transistor BT is provided around the electrode layers such as 22A and 22B, the protection performance can be improved without increasing the chip size, and especially the connection hole 26a can be formed. Since the transistor BT is formed so as to surround it and the excessive input is radially absorbed from the electrode layer 22A, the current capacity can be significantly improved. Further, desired internal elements and the like can be formed in a region where the input protection circuit is conventionally provided inside the electrode layer, and the space can be effectively used.

FIG. 4 shows a modification of the apparatus shown in FIG. 1. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The device of FIG. 4 differs from that of FIG. 1 in that the electrode layer 22A is surrounded by N ⁺ type regions 14A and 16A.
Insulating films 12a, 20 extending over A and between these regions
That is, the N-channel MOS type transistor MT is provided in parallel with the transistor BT as shown in FIG.

The N ⁺ type regions 14A and 16A act as the drain region and the source region of the transistor MT, respectively, and are located in the peripheral portion (regions 14A and 16A) of the electrode layer 22A.
(The portion that extends over the area) acts as the gate electrode layer of the transistor MT. When a positive overvoltage is applied to the electrode layer 22A, the transistor MT becomes conductive and absorbs the overvoltage. Further, when a negative overvoltage is applied to the electrode layer 22A, the collector junction of the transistor BT is in a forward bias state and absorbs the overvoltage.

FIG. 6 shows a semiconductor device according to another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

The device of FIG. 6 differs from that of FIG. 1 in that, firstly, in the N ⁺ type region 14A, the distance D from the connection hole 20a to the end portion on the region 16A side is set corresponding to a desired resistance value. By doing so, the region 14A is used as the diffusion resistance DR as shown in FIG. 7, and secondly, the conductive layer 22a is formed so as to extend over the regions 14A and 16A and surround the connection hole 26a. By connecting to the electrode layer 22A, as shown in FIG.
That is, an N-channel MOS transistor MT is provided in parallel with the above.

The conductive layer 22a can be formed by diverting the step of forming the electrode layer 22A. In addition, the conductive layer 22a
May be formed by expanding the electrode layer 22A in a rectangular pattern as shown in FIG. 2 to substitute for the peripheral portion of the electrode layer 22A.

The N ⁺ type regions 14A and 16A act as the drain region and the source region of the transistor MT, respectively, and the conductive layer 22a acts as the gate electrode layer of the transistor MT. When a positive overvoltage is applied to the electrode layer 22A, the transistor MT becomes conductive and absorbs the overvoltage.
When the transistor MT absorbs the positive overvoltage as described above, the transistor BT can absorb the negative overvoltage by the above-described diode operation.

If the avalanche breakdown voltage of the transistor BT is set to be slightly higher than the threshold voltage of the transistor MT, when the transistor MT becomes inoperable or fails, the transistor BT absorbs a positive overvoltage due to the avalanche breakdown. Can be made.

If a diffusion resistance DR is placed on the collector side of the transistor BT or the drain side of the transistor MT, an excessive input can be attenuated by the diffusion resistance DR, and the protection performance is improved. A resistance layer made of polysilicon or the like may be provided on the thin silicon oxide film below the insulating film 20 instead of the diffusion resistance DR. In this case, however, the resistance layer may be the drain of the transistor MT or the transistor B.
A contact is required to connect to the T collector. The configuration of FIG. 6 has an advantage that such a contact portion is unnecessary.

FIG. 8 shows a modified example of the apparatus shown in FIG. 6. The same parts as those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

The device of FIG. 8 differs from the device of FIG. 6 in that the conductive layer 22a is omitted and the transistor MT in parallel with the transistor BT is eliminated as shown in FIG.

The structure shown in FIGS. 8 and 9 corresponds to the structure shown in FIGS. 1 to 3 in which the N ⁺ type region 14A is expanded to form a diffusion resistance region. N ⁺ type region 14A
Acts as a diffusion resistance DR and attenuates an excessive input, reducing the load on the transistor BT. Transistor BT
The overvoltage absorption operation of is as described above with reference to FIGS.

The present invention is not limited to the above-mentioned embodiments, but can be implemented in various modified forms. For example, the following changes are possible.

(1) In the configuration of FIG. 1, N ⁺ type region 1
6A may be omitted. By doing so, the lateral bipolar transistor BT simply becomes a PN junction diode.

(2) In the structure of FIG. 1 or 6, the wiring layer 24C may be omitted. In this case, the N ⁺ -P ⁺ junction is a junction between high impurity concentration layers and has a low reverse breakdown voltage. That is, the N ⁺ type region 16A can be connected to the P type substrate 10 (that is, the power supply line V _SS ) via the Zener diode having a low breakdown voltage.

(3) In the configuration of FIG. 1 or FIG.
As shown in FIG. 5, N ⁻ type regions 30A and 32A may be provided below the N ⁺ type regions 14A and 16A, respectively. In this way, when the bipolar transistor BT of FIG. 7 operates, the current flows in the deeper side, and the current concentration is relieved. As a result, the breakdown voltage of the transistor BT is improved.

(4) In the structure of FIG. 6, the MOS transistor MT has a thick insulating film 12a as a gate insulating film.
Instead of using, a thin insulating film similar to that on the regions 14A and 16A may be used.

[0046]

As described above, according to the present invention, the protective element is formed around the connection hole for allowing the electrode layer for external lead-out to be connected to the external wiring, and the protection element is formed around the connection hole. The protection performance can be improved without increasing the size, and the space in the chip can be effectively used.

Further, since the protective element is formed so as to surround the connection hole and the excessive input is radially absorbed from the electrode layer, there is an effect that the current capacity of the protective element can be greatly improved.

Further, since the common terminal means is provided for the plurality of protective elements formed around the plurality of connection holes, the distance between the electrode layers can be narrowed and the number of pads can be easily increased. There is also.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

2 is a top view of the device of FIG. 1. FIG.

3 is an equivalent circuit diagram of the device of FIG.

FIG. 4 is a cross-sectional view showing a modified example of the device of FIG.

5 is an equivalent circuit diagram of the device of FIG.

FIG. 6 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

7 is an equivalent circuit diagram of the device of FIG.

8 is a cross-sectional view showing a modified example of the apparatus of FIG.

9 is an equivalent circuit diagram of the device of FIG.

FIG. 10 is a top view showing an input protection circuit arrangement in a conventional IC device.

11 is an enlarged top view showing a portion near the electrode layer in the device of FIG.

FIG. 12 is a circuit diagram showing an example of a conventional input protection circuit.

FIG. 13 is a circuit diagram showing another example of a conventional input protection circuit.

[Explanation of symbols]

10: semiconductor substrate, 12, 20, 26: insulating film, 14
A, 14B, 16A, 16B: N ⁺ type region, 18: P ⁺
Mold region, 22A, 22B: electrode layer, 24A to 24C: wiring layer, 28: bonding wire, BT: lateral bipolar transistor, MT: MOS type transistor, D
R: Diffusion resistance.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 23/60 23/62 29/78

Claims (3)

[Claims] 1. A semiconductor substrate on which an internal element to be protected is formed, a first insulating film formed on a surface of the semiconductor substrate, and an electrode layer for leading out an electrode of the internal element to the outside. A second insulating film formed on the first insulating film near the edge of the semiconductor substrate and a second insulating film formed on the first insulating film to cover the electrode layer. And a protective element for protecting the internal element from an excessive input input to the electrode layer, in which a connection hole for connecting an external wiring is formed in the electrode layer, A semiconductor device, which is formed around the connection hole in the semiconductor substrate so as to avoid immediately below the connection hole and is connected to the electrode layer. 2. The protective element is formed so as to surround the connection hole, and the electrode layers are connected to the protective element in a multi-point dispersed manner or in a loop contact state. Semiconductor device. 3. A semiconductor substrate on which an internal circuit to be protected is formed, a first insulating film formed on the surface of the semiconductor substrate, and first and second electrodes of the internal circuit are externally provided. First and second electrode layers for leading out, which are formed adjacent to each other on the first insulating film in the vicinity of the edge of the semiconductor substrate; and the first and second electrode layers. A second insulating film that covers the electrode layer and is formed on the first insulating film, and enables connection of first and second external wirings to the first and second electrode layers, respectively. And first and second protection elements for protecting the internal circuit from an excessive input input to the first and second electrode layers. And avoiding directly below the first and second connection holes in the semiconductor substrate Provided between the first and second connection holes and respectively connected to the first and second electrode layers, and between the first and second electrode layers in the semiconductor substrate. And a terminal means commonly connected to the first and second protection elements.