JPH08222705A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE: To eliminate the generation of a leakage current in the zero voltage of a complementary semiconductor device and to set the value of the threshold voltage of the complementary semiconductor device at the value of a desired voltage by a method wherein in both gate electrodes of N-channel and P-channel transistors, the regions, which come into contact with an ultrathin film single crystal Si film, are constituted of a conductive material, whose work function becomes the intermediate work function between those of P-type and N-type high impurity concentration Si films. CONSTITUTION: A polycrystalline Si film 22 under the lower part of a channel of an N-channel transistor is set in P-type high impurity concentration and a polycrystalline Si film 21 under the lower part of a channel of a P-channel transistor is set in N-type high impurity concentration using a multilayer SOI wafer having a polycrystalline Si film 2 under the lower part of an ultrathin film single crystal Si layer 4 via a thin insulating film 3. Moreover, the regions, which come into contact with gate oxide films 6, of both gate electrodes 8 of the transistors are constituted of a conductive material having roughly the same work function as that of an intrinsic Si film. Thereby, the generation of a leakage current in the zero voltage of a complementary semiconductor device can be eliminated and the setting of the value of the threshold voltage of the complementary semiconductor device at the value of a desired voltage can be realized by a simple production process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary semiconductor device, and more particularly to a high performance complementary MOS transistor formed on an insulating film with low power consumption and high speed operation.

[0002]

2. Description of the Related Art A method of forming a transistor in a single crystal semiconductor layer on an insulating film is known as an SOI (Silicon On Insulator) structure and is well known. The structure shown in FIGS. have.

FIG. 2 shows, for example, the 1993 Symposium on BLS Technology (1993 Symposi
um on VLSI Technology), p.27, etc., and is formed on a thick silicon oxide film (hereinafter simply referred to as an oxide film) 1 on a supporting substrate (not shown). Very thin single crystal Si of 100 nm or less
Complementary MOS transistors are formed on the films 41 and 42. Reference numerals 9 and 10 denote N-type source and drain diffusion regions, 11 and 12 denote P-type drain and source diffusion regions, 6
Is a gate oxide film, 8 is a gate electrode, 13, 14 and 1
Reference numerals 5 are a ground potential line, an output terminal, and a power supply potential line, respectively. Reference numeral 51 is an element isolation oxide film.

In the known SOI structure transistor shown in FIG. 2, the channel region formed by the thin single crystal Si films 41 and 42 is 0.2 μm unless a high impurity concentration is set.
A transistor having an ultra-fine gate length as described below cannot suppress the punch-through phenomenon, and thus has a problem that the current driving capability is reduced due to the reduction in mobility due to the high impurity concentration.

FIG. 3 is called a double gate structure and is known, for example, from Japanese Patent Laid-Open No. 5-167073. Insulation film 1
The gate electrodes 8 and 81 and the gate oxide films 6 and 61 are formed so that the ultrathin single crystal Si films 41 and 42 on 00 are sandwiched from above and below. Gate electrodes 8 and 81 may be electrically connected to each other in a device isolation oxide film region (not shown), or may have independent potentials. The SOI structure shown in FIG. 3 is expected to have a large current characteristic, the threshold voltage value can be controlled to an ultra-fine gate length regardless of the gate length, and the punch-through phenomenon can be effectively suppressed. The gate electrode 81 and the gate oxide film 61 need to be additionally manufactured, and the manufacturing process is complicated and impractical.
Further, the gate electrodes 8 and 81 cannot be formed in a self-aligned relationship with each other, and extra parasitic capacitance is generated, which causes a problem such as a hindrance to high-speed operation.

[0006]

The problem common to the conventionally known MOS transistors of SOI structure shown in FIGS. 2 and 3 is that high concentration impurities are not introduced into the ultra-thin single crystal film forming the channel. As long as the charge amount is limited, the threshold voltage value becomes a negative value in the n-channel transistor,
It is set to a positive value in the channel transistor. That is, if the SOI transistor is a complementary transistor, there is a problem that a leakage current flows at zero voltage. Therefore, it is necessary to set the ultra-thin single crystal film forming the channel to a high-concentration impurity, but this causes a problem that mobility decreases and the drive current cannot be increased.

Further, in the SOI structure shown in FIG. 3, the threshold voltage value can be controlled by applying a desired potential to the gate electrode 81, but as described above, the manufacturing process is complicated, so that the manufacturing yield is low and the cost is high. The control circuit has not been put into practical use due to its drawbacks such as complexity.

The present invention does not have the problems of the conventional SOI structure described above and the problem of leakage current at zero voltage, and the threshold voltage value can be set to a desired voltage value by a simple manufacturing process. The present invention provides a complementary semiconductor device. At the same time, it is not necessary to set the ultra-thin single crystal film forming the channel to a high-concentration impurity, and therefore a large current driving capability is realized.

Another problem to be solved by the present invention is to set the threshold voltage value of the N-channel transistor to a positive value, and the threshold voltage value of the P-channel transistor to a negative value, which is as close to zero as possible by setting it to 1V. The following is to realize a low power consumption complementary semiconductor device that can sufficiently operate even with a low voltage power supply.

[0010]

In order to solve the above-mentioned problems, in the complementary semiconductor device of the present invention, as a substrate, a thick insulating film, a polycrystalline Si film, a thin oxide film, and an ultrathin single crystal are formed on a supporting substrate. Using a multi-layered SOI substrate in which Si films are sequentially formed, the polycrystalline Si film under the N-channel transistor formed in the ultra-thin single crystal Si film has a P-type high impurity concentration, and the ultra-thin single-crystal Si film P The polycrystalline Si film below the channel transistor is formed to have an N-type high impurity concentration. Furthermore,
Regarding both gate electrodes of N and P channel transistors,
At least the region in contact with the ultra-thin single crystal Si film through the gate oxide film has the work functions of P-type high impurity concentration Si and N
The mold is made of a conductive material such that it is in the middle of high impurity concentration Si. Tungsten (W) as the conductive material
Film, molybdenum (Mo) film, tantalum (Ta) film, tungsten nitride film, titanium nitride film (TiN), tungsten silicide film, molybdenum silicide film, nickel silicide film, cobalt silicide film, germanium mixed Si film, aluminum (A
l) There are membranes and the like.

[0011]

According to the present invention, the problems of the negative threshold voltage in the N-channel transistor and the positive threshold voltage in the P-channel transistor, which are the drawbacks of the conventional ultra-thin film SOI structure complementary semiconductor device, are solved. It can be eliminated by both actions of the concentration impurity polycrystalline Si layer and the work function of the gate electrode. By setting the gate electrode material and the impurity concentration of the polycrystalline Si layer, the threshold voltage value can be controlled to a small positive value of 0.5 V or less in the N-channel transistor and a small negative value of −0.5 V or less in the P-channel transistor. it can. Therefore, the leakage current during standby can be ignored and the operation can be performed with a low power supply voltage. Another role of the high-concentration impurity polycrystalline Si layer directly under the transistor is to suppress the punch-through phenomenon without increasing the channel impurity concentration. For the above-mentioned purpose, the oxide film thickness just under the single crystal Si film may be made as thin as about 10 nm, and the drain electric field concentration in the thin oxide film may be effectively suppressed.

A high-concentration P-type Si film is used as the gate electrode material of the SOI structure N-channel transistor shown in FIG.
If a high-concentration N-type Si film is used as the gate electrode material of the P-channel transistor, a negative threshold voltage of the N-channel transistor and a positive threshold voltage of the P-channel transistor can be achieved, but the threshold voltage value is about ± 1V. Becomes too large, and low voltage operation at a power supply voltage of 1 V or less becomes impossible.

According to the present invention, the effect of reducing the junction capacitance and wiring capacitance, which is a feature of the conventional ultra-thin film SOI structure, is not impaired. Further, in the present invention, the junction capacitance can be further reduced by increasing the resistance of the polycrystalline Si film immediately below the source / drain diffusion layers. That is, in the polycrystalline Si film, the dependence of the resistance value on the impurity concentration is much steeper than that of the single crystal Si because of the energy level based on the crystal grain boundaries, so that the high resistance polycrystalline Si film is completely depleted. There is. According to the present invention, the parasitic element region necessarily associated with the transistor has a structure in which the electrically inferior polycrystalline film is replaced. Therefore, the capacitance of the junction capacitive element, which is a parasitic element, is different from that of the underlying thick oxide film. It is reduced in combination with the effect of series connection.
Based on this low load capacity characteristic, further high speed and low power operation becomes possible.

[0014]

EXAMPLES The present invention will now be described in more detail with reference to examples. To make it easier to understand, we will explain using the drawings,
The main part is shown in a larger scale than the other parts. The material, conductivity type, manufacturing conditions, and the like of each part are not limited to those described in the present embodiment, and many variations are possible.

(Embodiment 1) FIGS. 4 to 6 are sectional views showing the order of manufacturing steps of a complementary semiconductor device according to the first embodiment of the present invention, and FIG. 1 is a completed sectional view thereof. The complementary semiconductor device of the present invention is manufactured using a multi-layer structure SOI wafer having a polycrystalline Si film between oxide films as shown in FIG. FIG.
1, 1 is a 500 nm thick silicon thermal oxide film formed on a supporting substrate (not shown) made of a single crystal Si wafer, 2 is a 200 nm thick polycrystalline Si film formed by chemical vapor reaction, 3 is an oxide film with a thickness of 10 nm formed by thermal oxidation of a single crystal Si wafer, 4 is a resistivity of 20 Ωc
It is a single crystal Si film with m, p conductivity type and crystal plane orientation (100) thickness of 100 nm. The wafer diameter is 12.5 cm.

The multi-layered SOI wafer of FIG. 4 was manufactured by the direct bonding technique. That is, the Si wafer 4 having the thin oxide film 4 and the Si deposited film formed thereon and the supporting substrate Si wafer having the thick oxide film 1 formed thereon are directly bonded to each other without an adhesive in a dust-free environment, and then the bonding strength is increased. The heat treatment for strengthening is performed in an oxygen atmosphere at 1100 ° C. for 2 hours, and the Si wafer 4
The single crystal Si layer 4 was thinned to about 4 μm by grinding and polishing from the back surface side. Next, the thickness distribution of the single crystal Si layer 4 in the wafer was measured by an optical method, and the diameter of 1
Etching was performed by a Si etching apparatus using a converged plasma beam of about mm according to the thickness distribution while controlling the distribution so as to be eliminated. By measuring the Si layer thickness distribution and performing the etching process several times, the film thickness of the single crystal Si film 4 was controlled so that the film thickness of the single crystal Si film 4 finally became 100 ± 10 nm in the wafer.

The method of manufacturing the multi-layered SOI wafer is not limited to the above method, and the polycrystalline S
A high concentration of impurities is added to the i film 2 or the oxide film 1
And 3 may be different in film thickness, or may be another insulating film such as a silicon nitride film.

In the multi-layer SOI wafer shown in FIG. 4,
The single crystal Si layer 4 other than the active region is selectively removed, and a device isolation insulating film 5 having a thickness of 350 nm and a thickness of LOCO is formed in the removed region.
It was selectively formed by a known oxidation method called S method. The thin oxide film 3 acts as an etching stopper film for the selective removal of the single crystal Si layer 4, and functions to improve the precision of the selective removal. Next, boron (B) ions were implanted into the N-channel transistor formation planned region, and phosphorus (P) ions were implanted into the P-channel transistor formation planned region under the conditions of acceleration energies of 150 keV and 250 keV, respectively. The amount of implanted ions is set so that the maximum impurity concentration in the polycrystalline Si film 2 is 5 × 10 ¹⁸ / cm ^3, and the subsequent heat treatment results in the P-type high-concentration polycrystalline Si layer 21 and the N-type high-concentration polycrystalline Si layer 21. Layer 22 was formed. The ion implantation may be performed before the formation of the thick element isolation insulating film 5 and further before the selective removal of the single crystal Si layer 4 (FIG. 5).

From the state shown in FIG. 5, a gate oxide film 6 having a thickness of 5 nm is formed by a thermal oxidation method based on a known MOS transistor manufacturing method, and then 50 by a helicon plasma device.
A titanium nitride (TiN) film 7 having a thickness of nm is deposited, and subsequently, a Si film 8 having a high concentration of P having a thickness of 200 nm is added.
Was deposited by vacuum chemical vapor reaction. From this state, the Si film 8 and the TiN film 7 were patterned to form the gate electrodes of the N-channel transistor and the P-channel transistor according to the desired circuit configuration. Minimum gate length is 0.2
was μm.

It is also possible that an extra gate protection insulating film is formed on the Si film 8 by the patterning and the entire gate protection insulating film is patterned. Further, the insulating film may be selectively left on the side wall of the gate electrode.

Next, ion implantation was performed using the patterned gate electrode as a mask. Although P ions are selectively implanted in the N-channel transistor region and B ions are selectively implanted in the P-channel transistor region, the high impurity concentration region introduced in the state of FIG. The acceleration energy and the implantation amount were set to make the resistance. By the ion implantation, the polycrystalline Si film except under the gate electrode 8 of the N-channel transistor became the P-type high resistance region 23, and the polycrystalline Si film except under the gate electrode 8 of the P-channel transistor became the N-type high resistance region 24. .

The ion implantation is performed on the polycrystalline S immediately below the regions where the source and drain diffusion layers are to be formed except under the gate electrode 8.
The purpose is to increase the resistance of the i film, and the implanted ions may be ions of oxygen (O), nitrogen (N), or the like, instead of ions of the opposite conductivity type. If desired, the ion implantation need not be performed (FIG. 6).

From the state of FIG. 6, the source diffusion layer 9 and the drain diffusion layer 10 having the N-type high impurity concentration are formed in the single crystal Si layer 41 in the N channel transistor formation planned region by ion implantation using the gate electrode 8 as a mask. The source diffusion layer 12 and the drain diffusion layer 11 having a P-type high impurity concentration were selectively formed in the single crystal Si layer 42 in the P-channel transistor formation planned region. After that, a desired wiring including the ground potential line 13, the output terminal line 14, and the power supply line 15 was formed by a metal wiring manufacturing process using aluminum (Al) as a main material (FIG. 1).

In the complementary semiconductor device according to the present embodiment manufactured through this manufacturing process, the punch-through phenomenon does not occur even in an ultrafine transistor having a gate length of 0.2 μm, although the impurity concentration in the channel region is not increased. Not recognized, the threshold voltage value is 0.2V in the N-channel transistor,
The voltage of the P-channel transistor was -0.15V. The threshold voltage value is defined as a gate voltage when a source / drain current of 10 nA flows with a channel width of 10 μm. In addition, it is an N-channel transistor with a gate length of 0.2 μm and a gate width of 10 μm, and the source and drain currents are 8.5 m when the gate voltage and the drain voltage are 2 V each.
A shows a very large current value and shows that the driving ability is also excellent.

The current value corresponds to an increase in current of about 1.5 times that of the conventional one. Further, the N-type and P-type drain junction capacitances are both 0.2 fF / μm ^2, which is an extremely small value which is about 1/10 of that of the conventional transistor. That is, the complementary semiconductor device according to the present embodiment is capable of sufficiently high-speed operation even with a low voltage power source of 1 V or less, and has a feature that it can be provided at a low price because the manufacturing method is based on a known method using existing devices. There is.

(Embodiment 2) FIG. 7 is a completed sectional view of a complementary semiconductor device according to a second embodiment of the present invention. Example 1
Then, a laminated structure of the TiN film 7 and the Si film 8 is used as the gate electrode, and the work function of the TiN film 7 is involved in the control of the threshold voltage value of the transistor. However, in the complementary semiconductor device of this embodiment, the W film 71 is used. The gate electrode was composed of a single layer material.

In the complementary semiconductor device according to the present embodiment, the element having the same size as that of the first embodiment has a threshold voltage value of 0.1 V for the N-channel transistor and − for the P-channel transistor.
It became 0.25V. In addition, no punch-through phenomenon was observed, and other electrical characteristics, that is, parasitic capacitance, maximum drive current, etc., were almost the same and showed excellent characteristics. In this embodiment, the gate material is not limited to W, but molybdenum (Mo) film, tantalum (Ta) film, tungsten nitride film, tungsten silicide film, molybdenum silicide film, nickel silicide film, cobalt silicide film, germanium mixed Si film. , A single layer film such as an aluminum (Al) film, or a multi-layered film in which the above material is in contact with the gate oxide film.

(Embodiment 3) Another embodiment will be described with reference to FIG. The present embodiment relates to a signal transmission processing device constituted by a complementary semiconductor device according to the present invention, and particularly to a signal transmission processing device relating to an asynchronous transmission system (called an ATM switch).

In FIG. 8, an optical signal is transmitted at a very high speed in series by an optical fiber and converted into an electric signal (O / E conversion),
Further, it is introduced into an integrated circuit (BFMLSI) including a complementary semiconductor device manufactured according to the first embodiment of the present invention through a device for parallelizing (S / P conversion). The electrical signal subjected to the addressing processing in the integrated circuit is serialized (P / S conversion) and converted into an optical signal (E / O conversion) and output through the optical fiber. The BFM LSI is a multiplexer (MUX), a buffer memory (BF).
M) and a separator (DMUX). The BF
The MLSI is a memory control LSI and an LSI (empty address FIFO memory LS) having a function of controlling the free address allocation.
Controlled by I).

The present signal transmission processing device is a device having a switch function for transmitting an ultra high speed transmission signal sent to a desired address at an ultra high speed regardless of an address to be transmitted. BFMLSI
Since the operating speed is significantly slower than the transmission speed of the input optical signal, the input signal cannot be directly switched.The input signal is temporarily stored, the stored signal is switched, and then converted to an ultra-high-speed optical signal. A method of transmitting to a desired address is used. If the operation speed of BFMLSI is slow, a large storage capacity is required.

In the ATM switch according to this embodiment, BFMLSI is used.
Since it is composed of the complementary semiconductor device manufactured according to the first embodiment, the operating speed is 1.
Since it is 5 times faster and less expensive, it has become possible to reduce the storage capacity of the BFM LSI to about 2/3 times that of the conventional one. As a result, the manufacturing cost of the ATM switch could be reduced.

[0032]

According to the present invention, in the SOI structure capable of greatly reducing the junction capacitance and the wiring capacitance, the threshold voltage value of the N-channel transistor is set to a positive value and the threshold voltage value of the P-channel transistor is set to an extremely small value. it can. Also, 0.2 μm
Therefore, even if the device has an ultra-fine gate length, the punch-through phenomenon does not occur even if the channel concentration is not increased, so that the high mobility based on the low channel concentration can increase the current about 1.5 times that of the conventional structure device. Furthermore, the junction parasitic capacitance is 1 compared to the conventional structure.
There is an effect that it can be reduced to / 10 or less. Therefore, according to the present invention, a complementary semiconductor device capable of operating at a low voltage of 1 V or less, low power consumption, and capable of operating at high speed can be manufactured and provided at low cost by the conventional manufacturing apparatus.

[Brief description of drawings]

FIG. 1 is a sectional view of a complementary semiconductor device according to a first embodiment of the present invention when it is completed.

FIG. 2 is a cross-sectional view of a conventional SOI structure complementary semiconductor device.

FIG. 3 is a cross-sectional view of a conventional SOI structure complementary semiconductor device.

FIG. 4 is a cross-sectional view showing the manufacturing process of the complementary semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the complementary semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the complementary semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a complementary semiconductor device according to a second embodiment of the present invention when it is completed.

FIG. 8 is an explanatory diagram of an asynchronous transmission mode system for explaining a third embodiment of the present invention.

[Explanation of symbols]

1 ... Thick oxide film, 2 ... Polycrystalline Si film, 3 ... Thin oxide film,
4 ... Single crystal Si film, 5 ... Element isolation oxide film, 6 ... Gate oxide film, 7 ... TiN film, 8 ... Si gate film, 9 ... N type source diffusion layer, 10 ... N type drain diffusion layer, 11 ... P-type drain diffusion layer, 12 ... P-type source diffusion layer, 13 ... Ground potential line, 14 ... Output terminal, 15 ... Power line, 21 ... P-type high-concentration polycrystalline Si layer, 22 ... N-type high-concentration polycrystalline Si Layer, 23
... P-type high resistance polycrystalline Si layer, 24 ... N-type high resistance polycrystalline S
i layer, 71 ... W electrode.

Claims (7)

[Claims] 1. A first insulating film formed on a supporting substrate,
A first semiconductor film formed on the first insulating film, the first semiconductor film including a first region having a first conductivity type and a second region having a second conductivity type, and formed on the semiconductor film. Formed on the second insulating film, and has a first conductivity type on the first region and a second conductivity type on the second region. A single crystal semiconductor layer, a third insulating film formed on the single crystal semiconductor layer, and an electrode formed on the third insulating film, and at least the third insulating film of the electrode. The area in contact with is the first area,
And a complementary semiconductor device, which is different from any work function of the semiconductor film forming the second region and is made of the same conductive material having an intermediate value. 2. A pair of second regions of a second conductivity type and a low resistance, which are separated from each other, are formed in the single crystal semiconductor layer on the first region, Complementary semiconductor device in which a pair of first conductivity type and low resistance fourth regions separated from each other is formed in the single crystal semiconductor layer on the region. 3. The high resistance region according to claim 2, wherein the first semiconductor film is polycrystalline, and the first semiconductor film immediately below the pair of third regions has a first conductivity type. And the semiconductor film directly below the pair of fourth regions is a high-resistance region having a second conductivity type. 4. The complementary semiconductor device according to claim 1, wherein the electrode is at least partially formed of a refractory metal, a silicide film thereof, or a refractory metal nitride film. 5. The complementary semiconductor device according to claim 1, 2, 3, or 4, wherein the first semiconductor film is externally connected to a constant potential via a high resistance. 6. The method according to claim 1, 2, 3, 4 or 5.
A complementary semiconductor device in which the first semiconductor film is connected to a ground potential via a noise input protection circuit. 7. The high resistance region having the first conductivity type in the first semiconductor film and the high resistance region having the second conductivity type in the first semiconductor film are the electrode ends. Complementary semiconductor device configured to be spaced at a fixed distance from.