JPH08228196A - Circuit element for communication processing - Google Patents

Abstract

PURPOSE: To provide a highly versatile terminal processor by providing a pair of input/output terminals for transmitting and receiving data and plural terminals connected in parallel to a shift register and switching the input/output directions of the plural terminals. CONSTITUTION: This element is provided with a pair of the input/output terminals 64 and 66 for transmitting and receiving the data and the plural terminals 71-84 connected in parallel to the shift register 104. Terminal pins 85 and 86 are added for the input of mode selection signals and an abnormality detection circuit 305 monitors reception signals RXD inputted through the pin 64. For selection by mode selection input, when mode selection is set to 1, 1 at an address 0 for instance, the CIM is operated in an AD mode, both input number and output number become 5 for an I/O buffer 105 and an automatic transmission function is not imparted. Thus, just by adding only two pins 85 and 86, the selection of many functions is made possible and the CIM provided with the multiple functions is easily made into an LSI.

Description

Detailed Description of the Invention [0001] The present invention relates to a data multiplex transmission system.
Related to the communication terminal device used for the system, especially the operation mode
Can be selected as desired, and data transmission system can be
Circuit elements in terminal processing equipment
I do. [0002] 2. Description of the Related Art For example, various lamps are used in automobiles and the like.
And electrical components such as motors, and various automobile control
There are many electric devices such as sensors and actuators,
The number will increase with the shift to electronics in automobiles.
It's going all the way. Therefore, as in the past, many of these electric
Because the wiring was done independently for each device
Makes wiring extremely complex and large.
Cost, weight, space, or mutual
It causes big problems such as interference. Therefore, a method for solving such a problem
As one of these, it is possible to transmit a large number of signals with few wires
However, simplification of wiring by multiplex transmission system has been proposed.
As an example, Japanese Patent Application No. 57-175 by the present applicant
No. 35 application (see JP-A-58-70657) is filed.
I can do it. FIG. 1 shows an automatic transmission system using such a multiplex transmission system.
An example of the integrated wiring system in a vehicle is shown. This system in Figure 1
The system uses an optical fiber cable OF as a signal transmission line.
Central control unit CCU (hereinafter, simply referred to as CCU.
Oh, this is an abbreviation for Central Control Unit) and multiple ends
Powder processing unit LCU (hereinafter referred to simply as LCU.
This is an abbreviation for Local Control Unit)
Optical fiber cable OF
An optical branch connector OC is provided at the branch point. The CCU is located near the dashboard of a car.
Installed at an appropriate place to control the entire system
It has become. LCU is various operation switches SW,
Indicators such as meter M, lamp L, sensor S, etc.
In the vicinity of a large number of electric devices installed in the
It is distributed and arranged. CCU and each LCU are optical fiber
The optical signal and the electrical signal are connected to the part connected to the IVA cable OF.
A photoelectric conversion module O / E for converting light into two directions is provided.
Have been. The CCU has a microcomputer and
It has a data communication function by ALDATA and supports it.
Each LCU has a communication processing circuit CIM (hereinafter simply referred to as CIM
Say. In addition, this is the Communication Interface Adapter
Is abbreviated) and the CCU selects one of the LCUs in sequence.
, And exchanges data with that LCU.
1-channel optical fiber cable by repeating
Multiplex transmission becomes possible via OF, and complex and large-scale
Wiring inside the vehicle can be simplified. For such an integrated wiring system in an automobile
An example of the data transmission method that can be used is shown in FIG. FIG. 2 shows the entire data transmission system.
In the figure, 10 is a central processing unit.
(Corresponding to CCU in FIG. 1), 20 is a signal transmission line (optical in FIG. 1)
(Corresponding to fiber cable OF), 30 to 32 are end treatment
Device (corresponding to LCU in Fig. 1), 40 is an analog digitizer
Converters (hereinafter referred to as A / D) 51 to 58 are external negative
It is a load. It should be noted that in this example, the signal transmission line 20 is an electric signal.
It shows the case where the air signal transmission line is used.
In the central processing unit 10 and the terminal processing units 30 to 32,
No photoelectric conversion module is required, and therefore the terminal processing device
The contents of 30 to 32 are substantially only CIM. A computer (microcomputer)
The central processing unit 10 includes the transmission line 20 for each terminal processing unit.
Combined with 30-32, various sensors, lamps, activators
External load 51 consisting of electric devices such as a user and a motor
To send data to and receive data from
The acquisition is performed by the multiplex transmission method. At this time, Ana
External loads 57, 58 such as sensors that output log data
Is connected to the terminal processing device 32 via the A / D 40,
Being able to perform transmission operations using digital data
There is. If the signal transmission line 20 is bidirectional,
Not only the electrical signal transmission system,
Any communication system such as a signal transmission system is used.
The formula is the so-called Half Duplex method, with central processing
One of the plurality of terminal processing devices 30 to 32 from the device 10
One of the terminal processing device and the middle
Data transfer between the central processing unit 10 and the transmission line 20
It is supposed to be performed alternately through. [0011] Multiplex transmission by such a half-duplex system is possible.
Therefore, the data sent from the central processing unit 10
An address indicating the destination is attached and received from the transmission path 20.
The address attached to the collected data is your own address
Only one of the terminal processing devices that
I'm supposed to answer. Thus, the address from the central processing unit 10 is
Address depending on the data sent with the address
Terminal processing that understands and determines that it is their own
Only one of the devices responds to the central processing of its data.
By sending to the processing device 10, the half-duplex method described above
Thus, the data transmission operation according to is obtained. Further, in this example, each terminal processing device 30-
These terminal processing devices are provided by consolidating 32 functions into specific ones.
30-32 LSI (Large-scale integrated circuit) made easy
ing. And as a specific function at this time, the above
Data transmission function, that is, multiplex transmission by half-duplex method
Required functions and A / D attached to each terminal processor
It has two types of functions to control external devices such as 40
It As a result, the data transmission function is exclusively used.
Is becoming possible. For example, an integrated wiring system in a car
If you want to apply the
According to the appropriate transmission speed and the number of bits of the address
You can decide. Furthermore, in this multiplex transmission system,
To utilize the functions of the terminal processing device that has been implemented as an LSI
However, the central processing unit 10 is also capable of being uneasy.
As a result, the central processing unit 10 has a data transmission function.
General-purpose computer (microcomputer without
Etc.), and the above-described LSI terminal processing device 3
To configure the central processing unit 10 only by combining 3
Software required for the computer of the central processing unit 10.
While reducing the load on the software,
The versatility of the terminal processing device can be increased. As a result, as a result of the above-mentioned LSI and specialization.
It has become possible to further promote commercialization
It For such sharing, these terminal units
Processing devices 30 to 32 (hereinafter, these are all referred to as CIM
U) and CIM33 are all made in the same structure,
DIOI mode, AD mode, MPU depending on mode setting
Operates by selecting any of the three modes
Is ready to go. The DIO mode is the CIM
Operations required when is used as 30 to 31 in FIG.
Mode, and hereinafter AD mode is also referred to as CI in FIG.
MPU mode is an operation mode required for M32.
This is an operation mode required for the CIM 33. An example of such an LSI CIM
As shown in FIG. In FIG. 3, 61 to 84 are LSI patterns.
The package terminal pins 60 represent the package. end
The child pins 61 and 62 are for power supply, and the terminal pin 63 is a reset.
Input signal. The terminal pin 64 is used for the transmission line 20 (Fig.
2), and the reception signal RXD is input. Terminal pin
The clock 65 is for clock input, for example, a clock of 4MHz.
Lock is supplied. The terminal pin 66 is coupled to the transmission line 20.
And functions to output the transmission signal TXD.
It The terminal pins 67 to 70 receive the address data ADDR.
For power, 4 bits are prepared. The address data ADDR is
Data indicating the destination of data during data transmission
However, in this CIM, the address data AD
The above-mentioned mode setting is performed by DR.
It The terminal pins 71 to 84 are for connection with an external device,
It is used for data input / output according to the operation mode described above.
Or for transmission of control signals. 101 represents a control circuit, and this control circuit 1
01 is a sequence counter 303 and a sequence decoder
Various control signals required in this CIM, including 304
Signal is generated as the sequence counter 303 advances.
The function of promoting the operation of this CIM sequentially
I do. Reference numeral 102 denotes a synchronizing circuit, which is a switch of the received signal RXD.
Clock φ that is start / stop synchronized with the start bit_MAnd φ_SMaking work
To 104 is a 24-bit shift register,
Send and receive real data, or serial data and
It is used for mutual conversion between larel data. 105
Is a 14-bit input / output buffer, which can
Exchanges parallel data with the register 104
It works. Reference numeral 106 denotes an A / D control circuit, which is an external A / D
It serves to control the D converter 40 (FIG. 2). 30
6 is address data, which is output via terminal pins 67-70.
According to the address data ADDR set and input from the
Generates a predetermined signal and outputs each bit of I / O buffer 105
The input / output direction of the
It functions to output a signal for conversion. Reference numeral 307 denotes an address comparison circuit, which is a terminal pin 6
Address set by 7 to 70 and shift register 10
The data stored in the predetermined bits of 4 and the predetermined timing
And the address of the received data is determined.
U An error detection circuit 308 transmits the received data.
Check whether there was an error, and
If the dresses don't match
It works to reset. Next, the address by the terminal pins 67 to 70
The setting of will be described. As already mentioned,
In the system, each CIM on the LCU side is different
An address is assigned, and based on this address, half
Multiplex transmission of data by the duplex system
ing. Then, this address is assigned to each CIM.
Input that functions to assign to
These are the four terminal pins 67-70 that are
Data ADDR to be given to input₀~ ADDR₃Due to
The address of the CIM is designated. For example, its CIM
To specify the address of "10",
Data ADDR₀= 0, ADDR₁= 1, ADDR₂= 0,
ADDR₃= 1 and terminal pins 67-70 (101
0) may be input. In this CIM, data "0" is not connected.
Ground potential, data "1" is power supply voltage V_ccRepresented by
Therefore, the terminal pin 67 for the address "10"
Ground 69 and 69 and connect terminal pins 68 and 70 to the power supply
Will be. By the way, in this CIM, the address data is
The data ADDR is also input to the address decoder 306,
Output controls the directionality of the I / O buffer 105.
It has become so. As a result, specify the address
And 14 terminal pins 71 to 8 of the I / O buffer 105
Determine which of 4 will be the data output port
Is done. In this CIM, the address is
It corresponds to the number of output ports as it is. Follow
Now, if the address is set to "10", I / O buffer
10 of the 14 terminals of the fa are output ports,
The remaining four ports are controlled to be input ports. Although not shown in FIG. 3, this ad
The output of the response decoder 306 is the sequence of the control circuit 101.
Also provided to the decoder 304 and other circuits, which
As shown in FIG. 4, the operation mode of the CIM becomes
It can be switched. Ie in this example
CMU with address set to "0" is in MPU mode
Then, set the address between "1" and "D" C
IM is in DIO mode and the address is "E",
CIM set to either “F”
Each is made to work. Next, in each of these operation modes,
The kicking operation will be described. First, the address is "1"
To “D” and set to DIO mode
Then, the CIM enters the functional block state of FIG. Therefore, the received signal input from the transmission line 20
No. RXD is supplied to the synchronization circuit 102, and the control circuit 101
Is a clock that is start-stop synchronized with the clock component of the received signal RXD.
Φ_M, Φ_SIs given, which gives the control circuit 101
Generates a control signal, and the shift register 104 receives the received signal.
The data part of is read serially. On the other hand, the address comparison circuit 307 has an add
Respond to the terminal processing in advance from "1" to "D"
One of the addresses assigned to the device is given
This address and the specified bit of the shift register 104
Data read in the address position is compared with the address comparison circuit 307.
The shift register is compared only when the two match.
Data in the I / O buffer 105 is transferred to the I / O buffer 105.
Provided to external devices. Further, the control circuit 101 advances by a clock.
Generates sequential control signals, including a counter
Then, the data by the received signal RXD is transferred to the I / O buffer 10
After giving it to 5, then this time I / O buffer
Data from the user 105 to the shift register 104 in parallel
Data from the external device to the central processing unit 10.
Serial data in the shift register 104
Prepare as. Then, this data is transferred to the shift register 10
Serially read from 4 and transmitted as transmission signal TXD
Send to path 20. At this time, the received signal RXD
The existing address is added to the transmission signal TXD as it is.
Other end connected to the transmission line 20
However, the central processing unit
The device 10 matches the address sent by itself.
This transmission signal TXD is further captured, and
Transfer of data for one cycle by the half-duplex method is completed
I do. In this way, the central processing unit 10 operates the next terminal processing.
Send data to the processing device and repeat this
As a result, a plurality of terminal processing devices 30 to 32
Data is exchanged periodically, enabling multiplex transmission.
It The data contents of the shift register 104 at this time are shown in the figure.
As shown in DIO mode No. 6, from No. 0 to No. 5
No. 6 to No. 19 is not used, 1 from No. 6 to No. 19
4 bits allocated to data DIO of I / O buffer 105
Be taken. 4 bits from No. 20 to No. 23
No. 24 is assigned to the address data ADDR of
It is assigned to the start bit. In addition, DIO day
The number of bits allocated to the data is 14
I / O buffer 105 has 14 bits
Because there is. Also, for this reason, in this CIM, I
The maximum number of external loads that can be connected to the I / O buffer 105
There are 14 child pins 71 to 84 (FIG. 3). The method of data transmission by this system is as follows.
It is called start-stop synchronization, bidirectional, reverse two-way transmission system,
NRZ (nonreturn to zero) method for digital data
The transmission waveform is shown in Fig. 7.
As shown. That is, is it the CIM on the CCU side?
Receives a frame that transmits data to the CIM on the LCU side
If a frame is a transmission frame,
Both frames are 74 bits, so one frame is 14
It has 8 bits. Then, the received frame and the transmitted frame
Both have the same frame structure.
There is a “0” in the set, and then 1 bit for start / stop synchronization.
A start bit consisting of a "1"
Following this, 24-bit received data RXD is transmitted data T
XD is transmitted in the NRZ signal format, and
Inverted data RXD (with bar top) or RXD (with bar top)
) Is transmitted. Note that this inversion
Transmit data RXD (bar top) or RXD (bar top)
It is sent to check the transmission error. As already explained, in this system,
Since multiplex transmission is performed by the half-duplex method, the reception frame
The CCU is located in the first 4 bits of the system data RXD.
, The address data of the LCU to be called
Data ADDR is attached as shown in FIG.
Data TX of the transmission frame transmitted from the LCU
The same address data ADDR is added to the first 4 bits of D.
And transmitted. The transmission frame is transmitted from the LCU side.
Is it limited to the LCU called on the CCU side?
, The address is not added to the transmission data TXD
On the CCU side, the data is from which LCU
It can be immediately judged whether or not. Therefore, the transmission frame
It is not always necessary to add an address to the data TXD.
The first 4 bits of the data TXD to L such as (0000)
Even if the data does not match any address of the CU
Good. Next, the address is either "E" or "F".
If set to either one, the CIM will be in AD mode.
Function block is switched to the state shown in FIG.
It The A / D control circuit 106 is the terminal processing device in FIG.
A / D40 control function required when used as 32
Is a sensor that generates an analog signal.
The data from which external load 57, 58 is read by the A / D 40.
Digitized and loaded into the shift register 104
It works to give the necessary control functions. Incidentally, that
Others are the same as the case of FIG. This CIM operates in the AD mode.
Stored in shift register 104 when set to
The contents of the data to be reproduced are as shown in the AD mode of FIG.
8 bits from No. 0 to No. 7 through A / D40
AD data stored from external loads 57, 58, etc.
2 bits of No. 8 and No. 9 for AD channel data
It is for storage, which makes it the No. for DIO data.
It is 10 bits from 10 to No. 19. In addition,
Others are the same as in the DIO mode. Further, the AD channel data at this time and
Is a channel when using multi-channel A / D.
This is data for specifying the flannel, and in this embodiment, A / D40
As it uses 4 channels, 2 bits
Is assigned. The A / D control circuit 106 is dedicated to that situation.
It has a sequence counter and sequence decoder of
It operates independently of the control operation by the control circuit 101,
Step forward and control sequentially. So
Then, this controls the external A / D40,
Analog data from up to four types of external equipment can be
Periodically digitally converted and imported as serial data
4 channels provided in the A / D control circuit 106
It operates to write sequentially to the register of the channel. On the other hand, when the reception frame has been input
(Time t in FIG.₀) Is written in the shift register 104
The format of the data is the AD mode shown in Fig. 6.
Therefore, the Q of this shift register 104₈And Q₉A bit of
Two-bit AD data is stored. There
Then, the A / D control circuit 106 uses this AD channel data.
Write to the above 4 channel register based on
Read some AD data and shift it
Q of 4₀To Q₇Write to a bit. And after this
This AD data is transmitted by transmitting a transmission frame.
Will be included in the TXD and will be transmitted to the CCU.
The operation in the mode can be obtained. By the way, in this CIM, as described above,
The reception processing of the reception signal RXD and the subsequent transmission signal TX
Regardless of the D transmission processing, the A / D control circuit 106 is always
AD data is prepared in the register in the table. Follow
In this CIM, at what timing
Even if the reception signal RXD appears, the AD data is immediately used.
Transmission of the transmission signal TXD can be performed, and the A / D 40
The transmission process is not affected by the operation, and A / D
The transmission speed decreases due to the time required for the conversion operation, etc.
There is no fear of In this system, the CIM is an LSI
A / D40 is externally attached when converting to CIM
It is designed to reduce the cost when converting. One
Mari, as explained in Figure 2, in this system mode
Setting one type of CIM as LCU30-31
, LCU32, or CIM3 of CCU10
It can be used as 3. At this time, however, by incorporating the A / D
If you use it as a CIM 30, 31, 33
Wasteful and, in general, integrated wiring for automobiles
When applied to the system, it is used as CIM32.
The number that is given is used as the other CIM 30, 31, 33
A / D is included in all CIMs
There is not much merit to store it. for that reason,
The A / D is externally attached. However, since this A / D is externally attached,
As is clear from 8, 4 for external A / D40
Book connection terminals are required, and terminal pins when integrated into an LSI
This may lead to an increase in the number. So in this example,
With the connection configuration shown in Fig. 3, the CIM is in AD mode.
When set, the 14 ports of the I / O buffer 105
4 of the terminals are connection terminals for the A / D 40
It is being used. That is, in this CIM, the I / O buffer is
The port 105 is 14 ports and these are clear from FIG.
As you can see, when the CIM is set to DIO mode
May all be used as input / output ports
However, only 10 ports are used at maximum in AD mode
However, 4 ports are not used for input / output of DIO data.
It's left over. Therefore, the remaining 4 ports are set in the AD mode.
Switch with and use as a terminal pin for A / D40
Therefore, the number of terminal pins does not increase even if the A / D is externally attached.
Greater versatility when integrated into LSI, enabling cost reduction
Become. Next, set the address of this CIM to "0".
The case in which the MPU mode is set to the MPU mode will be described.
This MPU mode is used as the CIM 33 in FIG.
DIO is a mode for giving necessary functions when
CC, unlike when used in AD mode and AD mode
U10 microcomputer (hereinafter simply referred to as a microcomputer
When the data is given from
Data to the transmission line 20 and returned in response.
When you receive the incoming data, make it parallel data
Transmission interface operation to transfer to a microcomputer
This is the mode in which work is performed. By the way, the description so far relates to FIG.
As explained above, the explanation as seen from the CIM on the LCU side
Since it was mainly, CIM on the CCU side to C on the LCU side
Frames that transmit data to IM receive frames, vice versa
The frame to be transmitted from the LCU side to the CCU side.
However, after that, as shown in FIG.
From the CIM of the
Receives a frame when it accepts data
Described as a frame. Therefore, hereinafter, a certain CIM, for example, CI
The transmission frame in M33 is another CIM, for example, CIM3.
0 indicates a received frame, while CIM30 transmits
The frame is a received frame in CIM33. Now, FIG. 10 shows the address of this CIM.
Set to "0" and control to operate in CPU mode
Figure 10 is a rough functional block diagram when
As is clear, in COU mode, I / O buffer 1
05 (Fig. 3), A / D40 has stopped its function, microcomputer
And are connected by a 14-bit data bus. In addition, this
The terminal pin at this time is the input / output port of the I / O buffer 105
Commonly used with, so that no increase or decrease in terminal pins
It goes without saying that it has become. And this 14
8 bits of the input / output of the 14 bits are for data
The remaining 6 bits are for control signals. Now, in this CPU mode, the shift
The data contents of the register 104 are changed to the MPU mode of FIG.
Q as shown₀To Q_{twenty three}All 24 bits up to MPU
It is data, and the microcomputer is an 8-bit data bus.
To access this shift register 104 by
It has become. Therefore, the microcomputer and the shift register 10
Data exchange with 4 is 3 per cycle.
It will be accessed once. On the other hand, the control circuit 101 is controlled by the microcomputer.
Q signal of the shift register 104₀~ Q_{twenty three}All of
At the same time that data from the microcomputer is stored in all bits
At the time t when this data is stored.
_xTo start transmission of the transmission frame as shown in FIG.
It Thus, the transmission frame is transmitted from the CIM 33.
When sent, CIMs 30-32 on the LCU side will be sent accordingly.
One of them responds and the CIM continues to transmit?
, Time t_xFrom one frame (148 bits)
Time t when the interval has elapsed_yThen, the shift register 104
Some of the CIM (CI
Data transmitted from one of M30-32) is acceptable
The portability function will end. Therefore, the control circuit 101 of the CIM 33 is
At this time t_yGenerates an interrupt request IRQ at
In response, the microcomputer reads the data in the shift register 104
Data transmission for one cycle is completed. In addition, this
The data transfer operation between CIMs is related to Fig.5.
The same as in the DIO mode described above.
Needless to say. The CIM described above is based on Japanese Patent Application No.
No. 8-40581, Japanese Patent Application No. 58-104880, Japanese Patent Application
Japanese Patent Application No. 58-106666 and Japanese Patent Application No. 58-1066.
According to the invention filed by the applicant as No. 67
Further details are given in the specification relating to these applications.
It is explained well. [0062] [Problems to be Solved by the Invention] By the way,
Used in data transmission systems
More functions are often required for CIM. So
Then, even in this case, those functions are arbitrarily selected and paired.
It is desirable that they can be used together. Therefore, the selection and combination of such functions are
In order to perform any setting, input the setting for that.
It is necessary to supply it to the decoder etc. in the CIM.
It is necessary to add the terminal pin of the package. Soshi
The number of terminal pins required at this time depends on the function selection.
The number of choices and combinations increases, and
It will be a major obstacle to I-ization. The present invention has been made in view of such a constant situation.
The purpose is the number of terminal pins of the LSI package.
Increase the number of features and combine many features
The purpose is to provide a CIM that can be adjusted. [0065] [Means for Solving the Problems]
Therefore, according to the present invention, among the terminal pins of the LSI package,
Multiple pins for selecting functions and combination settings
Divide into multiple groups of pins and
Matrix selection by combination input for each group
The point that the functions described above are selected and combined
It is characterized by. [0066] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a CIM (terminal according to the present invention will be described.
The processing device) will be described with reference to the illustrated embodiment.
FIG. 11 shows an embodiment of the present invention.
Is a terminal pin, 305 is an abnormality detection circuit, and 330 is automatic transmission
A circuit 331 is a mode decoder, and others are shown in FIG.
Is the same as the conventional example. The terminal pins 85 and 86 are connected to the mode select signal.
It was added for the input of No. MS. Abnormality detection circuit 3
05 is a reception signal RXD input through the terminal pin 64
Is monitored, and the input of this reception signal RXD is predetermined.
If the traces are cut off for more than a specified period of time,
A function that determines that a failure has occurred and generates a fail-safe control signal
do. And this fail-safe control signal is I / O
It is supplied to the buffer 105 and the state of its output port is stored.
It works to fix it in a fixed state. The automatic transmission circuit 330 is a sequence counter.
Check the count number of 303, and if it reaches a predetermined number,
Load a predetermined number into the count output of this counter 303
However, the control state by the sequence decoder 304 is shown in FIG.
Time t_xThe required control state in
Work. FIG. 12 shows the address data ADDR input
Four terminal pins (67-70 in Fig. 11) and mode select
2 terminal pins (85 in FIG. 11,
86) only, and in this embodiment,
Dress input mode Select by matrix with input
The setting for the fixed operation mode is now done
There is. FIG. 13 shows address data and mode select.
An example of operation mode setting by combination with a signal is shown.
In a matrix chart, with 4-bit address data
Addresses "0" to "F" to be set and 2-bit mode
Deselect signal MS₀, MS₁Depending on the setting of
It is shown whether the operation mode is set. Here, each function will be described.
It The connection form refers to the operation mode of this entire CIM.
The operating modes of MPU, DIO, and AD are already
As explained in. Set the address to "0" and select the mode.
Connection obtained when the input is set to anything other than (0,0)
The forms (TEST0) and (TEST1) mean LS
You can easily perform the product test of I-CIM.
If you set (TEST0) in the operation mode
-Counter 303 counts at 4 times faster than normal
The DIO mode and AD
Functions required for receiving and transmitting data in normal mode are normal
Whether or not the test can be completed in a short time. When set to (TEST1), the abnormality detection
The output circuit 305 can be operated with a short waiting time,
You can efficiently test whether the function is normal or not.
It The input / output direction refers to each terminal of the I / O buffer 105.
By setting the input / output direction, the address can be changed from "1" to "D".
In the DIO mode set to one of the
As you can see, this address determines
Mode "0" and mode select (0,0)
Mode, the I / O buffer 105 is turned through and its directionality
Disappears and becomes bidirectional, and data input and output
CIM is controlled by the connected microcomputer
become. On the other hand, when the address is "0", mode select
Is other than (0,0), that is, in test mode
And in AD mode at addresses “E” and “F”,
Deselect signal MS₀, MS₁By I / O buffer 1
The input / output direction of 05 is determined. The fail-safe function is the abnormality detection circuit 3
05 is activated and the resulting I / O buffer 1
05 fixed output state function, for detailed explanation
As will be described later, in this embodiment, the I / O buffer
Of the 105 input / output terminals, set to the output direction
If an error occurs, check the output data status of the pin directly
How to fix the previous state (this is called maintaining the status quo)
Is turned off) and a method of turning it off uniformly (turn this off
You can select and). The automatic transmission function means that this CIM is
Used for data transmission system, 1: 1 transmission by CIM only
This is a function that is necessary for configuring the system, and details about it.
As described later, the automatic transmission circuit 330 is activated.
Whether to grant or not is selected depending on whether or not to make it
It has become. The selection by the mode select input is
Each function works in the same way. So for example
Set the mode select to (1,1) at address "0"
If so, the CIM operates in AD (TEST0) mode.
However, the I / O buffer 105 has 5 inputs and 5 outputs.
, The fail-safe function is OFF method, and automatic transmission
The communication function is not added. Therefore, according to this embodiment, only two
Many functions can be selected simply by adding terminal pins 85 and 86
Function, and it is easy to implement a multi-function CIM LSI.
You can follow. Next, details of the abnormality detection circuit 305 and
The fail-safe function obtained by will be described.
In the transmission system where this CIM is used,
Multiple signal transmission lines such as a single optical fiber cable
Since many signals are being transmitted, it is possible that
If a transmission failure occurs, the control status of many electrical devices will be affected.
May affect the safety of automobiles.
It Therefore, in such a system,
If an abnormality such as a failure occurs in the transmission system, be sure of it
To detect and control the operation of loads such as electrical equipment.
Will cause a safety issue for automobiles even when the car stops
I would like to try to hold it in a less feared direction.
Yes. Therefore, the abnormality detection times are provided for this purpose.
The path 305 and the fail-safe function by this. FIG. 14 shows an embodiment of the abnormality detection circuit 305.
In the figure, 501 is a timer counter, and 50
2 is a flip-flop acting as a 1-bit register,
503 to 506 are AND gates, 507 is an inverter
is there. 331 is the address data ADDR and the mode
Mode operating by matrix with select signal MS
It represents a decoder, and the others are the same as those in the embodiment of FIG.
The same. The counter 501 counts an appropriate clock.
Output every time a predetermined number is counted
Generates CO. Then, the reset input R is
Address output from the output comparison circuit 307 (FIG. 11).
The input signal MYADDR is input. The mode decoder 331 is the set shown in FIG.
A switching signal is generated at the same time and is supplied to a predetermined part.
However, at this time, the fail-safe function is shown in Fig. 13.
As shown, the status of the output port of the I / O buffer 105
Are all turned off regardless of the state until then.
OFF mode and output state up to that point are saved as is
There are two types of current status maintenance mode, and the OFF mode signal is
AND gate 503 and the current status mode signal is
Output to the respective gates 504. Also, the I / O buffer 105 has
When writing data, input the clock for writing CK
It is designed to be supplied to. That is, the shift register
Data D is given to a predetermined bit from 104 (FIG. 11)
With nothing, nothing is written to the I / O buffer 105,
After applying the data D, the clock was supplied to the input CK.
Only when the data in it can be rewritten
Is there. Then, input a clock to the input CLR.
If you do, all the data D written at that time will be
Are cleared and all data at the output port becomes 0,
The output ports of electric machines etc. connected to these output ports.
All loads such as electric devices connected to the switch are off
Will be done. Next, the operation of this embodiment will be described.
It The counter 501 always counts by the clock
However, it is reset only when the signal MYADDR is input.
Be done. Therefore, if the signal MYADDR is not input,
Determined by lock frequency and number of bits in counter 501
Generates carry-out output CO every predetermined period
It On the other hand, the signal MYADDR is an address comparison signal.
Is the output of path 307, so this CIM is
Mode, AD mode, and automatic transmission mode described later.
When it is used, it is generated every time the data addressed to itself is received.
It And in the data transmission system using this CIM
In addition, if it is in a normal state
Data transmission to yourself is always performed within the period.
This is as already explained. Therefore, the number of bits of the counter 501 is now
And select the frequency of the clock input to it.
Carry-out output CO of counter 501 of
The cycle (this is PCO) is the above-mentioned self-addressed data
Greater than the maximum transmission cycle of (which is referred to as PD) by a predetermined value
Suppose that That is, PCO> PD
It is assumed that Then, this CIM is the LCU 30-3.
In the data transmission system (Fig. 2) incorporated as 2
While the functions of the CCU 10 and the transmission path 20 are normally maintained
Is always C during the period within the above-mentioned predetermined period PD.
Data is transmitted to IM and address comparison is performed.
Signal MYADDR will be generated from path 307.
As a result, the counter 501 has the above-mentioned PCO> PD.
Due to the condition of, the count value reaches the countout
Will always be reset before the
No CO is output, so the flip-flop is
502 remains reset. Next, some abnormality, for example, this CIM
When an abnormality such as disconnection of the transmission line 20 for
I do. Then, from the time this abnormality occurred,
It is no longer possible to receive data for CIM, this time
The signal MYADDR will not appear anymore
I will end up. As a result, the counter 501 is
The data for this CIM was received immediately before it occurred.
It will be reset when it is received and then reset.
Only the counting operation can proceed without being
It Therefore, whether the counter 501 is at the time when the abnormality occurs
From the maximum, the period corresponding to the above cycle PCO has elapsed
The carry-out output CO is generated when
The flip-flop 502 is set. Therefore, this counter 501 is
The system is normal and data is being received normally.
Output CO is not generated while the flip-flop 502 is turned on.
Keep in reset state, but something wrong with the transmission system
Occurs and it becomes impossible to receive data by this CIM
And output CO to set flip-flop 502
It will work as a
It is possible to know the occurrence of an abnormality from the state of the rop 502.
Then, the abnormality detection function will be obtained. Next, the Q of the flip-flop 502 is
The output is one of the AND gates 503 and 504.
It is tied to the input. Therefore, as described above,
Is detected and the flip-flop 502 is set
And these AND gates 503 and 504 are activated.
It On the other hand, these AND gates 503, 50
Mode decoder 331 to the other input of each of 4
The current mode maintaining signal and the OFF mode signal are respectively
Is being supplied. In addition, these two types
As shown in FIG. 13, the signal signals are supplied at the same time.
It will not be done. So between these signals, Current status maintenance mode signal (+) OFF signal = 1 Relationship is given. Therefore, the mode decoder 331 is now used.
Select the fail-safe function
If so, the flip-flop 50 in which the abnormality is detected
When the Q output of 2 becomes "1", AND gate 50
Only the output of AND gate 504 out of 3,504
It becomes "1". Therefore, as a result, AND gate 505
Output is fixed at "0" and clock WCLOCK
-Superscript) to CK input of I / O buffer 105
The supply of the write clock to be performed is prohibited. Therefore, at this time, if an abnormality is detected,
After that point, the data of the I / O buffer 105
Writing (rewriting) is prohibited, and I /
The state of the output data of the O buffer 105 is the one at the time of the abnormality detection.
The state is maintained as it was immediately before, and the current state is maintained.
Therefore, the fail-safe function can be obtained. On the other hand, the mode decoder 331
If the selection of the safe function is in the OFF mode,
For example, if an abnormality is detected at this time, AND gate
Only the output of AND gate 503 of 503 and 504
Becomes “1”, and as a result, via the inverter 507
AND gate 506 is activated and clock WCLOC
Clear input of I / O buffer 105 by K (bar superscript)
Will be supplied to the force CLR. Therefore, at this time, an abnormality is detected.
Immediately after that, all the data in the I / O buffer 105 is cleared.
Rear, output data are all "0", that is, turned off
And the fail save by OFF mode
Function will be given. Next, another embodiment of the abnormality detection circuit 305
Is shown in FIG. In this embodiment, the counter 501
Bit output Q_nUse the to display the reduced points of occurrence of abnormalities.
This is different from the embodiment of FIG.
Adds AND gate 508 and OR gate 509
And the fail-safe function in OFF mode worked.
The output Q of the last bit of the counter 501_nThe terminal pin
It is only the point that I took out to one of 71-84,
Others are the same as in the case of FIG. The clock is always input to the counter 501.
Therefore, the MYADDR signal is no longer supplied.
Generates carry-out output CO, and flip-flop 5
This counter 501 continues counting even after setting 02.
Production, so the output Q of its last bit_n
Is the duty ratio with the above cycle PCO as one cycle
Pulse of 50% (rectangular wave) is continuously obtained. Therefore, an external negative which should be connected to the terminal pin 71.
Loads as electrical equipment such as automobile room lamps
If an abnormality is detected, the room lamp up to that point will be
The room lamp can start blinking regardless of whether it is on or off.
Then, it is possible to display the occurrence of an abnormality. The OR gate 5 is used in the embodiment of FIG.
09 is used because the terminal pin 71 is commonly used.
As a result, in this embodiment, it should be connected to the terminal pin 71.
External load is limited to equipment like the room lamp above
If this is not done, the display device cannot be used. Therefore, the terminal pin for the abnormality detection display output is
It is provided exclusively and the AND gate 508 is output from the terminal pin.
If you take out the force directly, you can save the terminal pin.
Although it cannot be obtained, the degree of freedom in use should be high.
You can By the way, the counter 501 counts up.
Time to generate carry-out output CO
Is compared with the period PD of data transmission for one CIM.
Therefore, it is necessary to make it large enough.
It is necessary to select, for example, 100 mS or more as the term PCO.
It Therefore, for example, the clock frequency is set to 4 MHz.
If z, the number of bits of the counter 501 is 20 bits or more.
Will be required, and the cost increase will be significant.
It gets worse. On the other hand, in the embodiment shown in FIG.
Path 102 contains a 4-bit counter, which
The signal φ is obtained by dividing the clock of 4MHz._M, Φ_STona
And this signal φ_M, Φ_SIs an 8-bit sequence
Unta 303 is counting. Therefore, in this embodiment, the sequence cow
The carry-out output of the counter 303 to the counter 501.
It is supplied as a lock, so that the counter 5
So that the number of bits required for 01 is as small as 8 bits
are doing. Next, details of the automatic transmission function will be described.
It The explanation so far is that this CIM is as shown in FIG.
When applied to a data transmission system
It was. In addition, in this system of FIG.
CCU is provided to control data transmission between each other,
System by the microcomputer etc. included in this CCU
The whole control is properly performed. Therefore, it is used in CCU and each LCU.
If the CIM is set to MPU mode on the CCU side,
In the case of control, the data from each frame is controlled by the microcomputer.
Data TXD transmission starts, while the LCU side
If it is set to the mode, the data sent from the CCU side
Data TXD is input as received data RXD and
Due to the fact that the reception is completed, the transmission data TXD
To start the transmission of. Therefore, a transmission system using this CIM
In order to obtain the data transmission function required there.
Therefore, a CCU equipped with a microcomputer is indispensable.
It is not possible to configure the transmission system with M alone. Immediately
Then, as shown in Fig. 16, two CIs are used without using a microcomputer.
Only M and M are combined with one OF, and CIM is M
Assuming PU mode and CIM in DIO mode
However, if this is the case, data transmission from any CIM
Since it does not start, the data transmission function is not exerted. this
This means that both CIMs are in MPU mode or DIO mode.
It is the same even if it is de. However, in the case of the configuration as shown in FIG.
However, if you use some means,
Data transmission, data transmission after that
The operation is started and the data transmission is continued alternately.
can do. However, the transmission is started in this way.
Even if you do, there is no noise in such a data transmission system.
It is inevitable that data transmission errors will occur due to
As a result, once a transmission error occurs, the data will be
Data transmission operation will be stopped, thus
The specified data transmission operation cannot be expected. On the other hand, as a wiring system in an automobile,
Relatively large scale data transmission system including many LCUs
Not limited to this, multiplex transmission between two LCUs can be performed
Is sufficient, a relatively small data transmission system
A stem may also be needed. For example, steering wheel column
Switch panel on the side of the
The wiring system between controlled devices such as
is there. So for such a system, if
If possible, use the small-scale data transmission system shown in FIG.
Use is desirable. However, this kind of small-scale data transmission
For the transmission system, use the CIM described above.
When configured, one CIM can use a microcomputer
A control device is provided, and this CIM has a function as a CCU.
Or more CCU for 2 LCUs
It is necessary to provide it separately, and it is comparatively large compared to the overall scale.
There was a drawback that the system was expensive. The automatic transmission function handles such a case.
The purpose is to connect two CIMs to each other via a transmission line.
Immediately, just by setting up an LCU one-to-one transmission system
Stable multiplex data transmission, small scale
Low cost data transmission system is possible,
To make an improved CIM useful for integrated wiring of
Therefore, specifically, as shown in FIG.
330 to activate this circuit as needed.
It is a scam. Now, this automatic transmission circuit 330 is
The condition for starting the data transmission operation is transmitted from another CIM.
It is not only due to the end of data reception operation
In addition to the fact that a predetermined time has passed after the power was turned on,
And at a predetermined time after the data transmission operation is completed by itself.
Data sent from another CIM is not received within
The thing that adds the function of adding due to
Then, a CI transmission system as shown in FIG.
To configure by M, one CIM, eg C
IM automatic transmission mode (hereinafter, this is the active mode
, And the other CIM (in this case CIM
) Automatic transmission no mode (hereinafter this is passive mode
Set). In this embodiment, as shown in FIG.
To set the CIM to active mode.
Set the response to any one from "1" to "D"
(At this time, as is clear from FIG.
Mode selection input MS₁= 1, M
S₀= 0 is set for each
To set the mode to the same
Set to any one from "D" to "D" and select the mode.
Input MS₁It is set to = 0. By the way, this active mode and pass
Even in sub mode, the
There is no change in the function of the loess. On the other hand, as shown in FIG.
In a one-to-one transmission system, between CIM
Data is exchanged with each other. Therefore, at this time
CIM and CIM to enable data transmission
Both of them to the same address (only between addresses 1-D)
You must set and configure the system. Therefore, the same applies in the active mode.
I / O buffer input port and output port
Needs to be inverted and is configured that way
However, this point will be described later. The automatic transmission circuit 330 according to this embodiment is
Circuit, inverter, and flip-flop
Then the CIM was set to active mode
Sometimes, the count output of the sequence counter 303
When S254 is reached, the signal LOA is output at a predetermined timing.
D49 is generated and S49 is added to the sequence counter 303.
It acts as a loader, which allows you to
Even if you do not receive the
The data transmission operation is automatically started.
It Thus, in the DIO mode, further access is possible.
CIM that can be set to active mode and active mode
, And the LCU 1: 1 transmission system as shown in FIG.
FIG. 17 shows the structure of the system. Where CIM3
4 is DIO mode and C set to active mode
IM and CIM35 are in DIO mode and pass
Represents the CIMs set to the bus mode. Therefore, the CIM 34 can automatically display the CIM 34 shown in FIG.
As described above, except that the transmitter circuit 330 is activated.
Operates as CIM in DIO mode, while CI
Since the automatic transmission circuit 330 is not activated in M35,
Exactly the same operation as the CIM in the DIO mode described in
It is supposed to. Next, the configuration using the CIM shown in FIG.
The operation of the one-to-one transmission system as shown in FIG.
And explain. As described above, C in FIG.
The IM 34 and 35 each have a basic operation of DIO.
It is in the mode (especially CIM35 is D
It is exactly the same as the IO mode), so in the following explanation, D
Focus only on the differences from the IO mode.
U First, the engine key of the automobile is operated.
When the power of the transmission system is turned on by
Rise is performed and the output of the sequence counter 303 is
It is set to S0 (note that this S is an abbreviation for stage).
Then, following that, the clock φ_MBy the count of
Then, the counter 303 advances. In this way, the counter 303 starts stepping
When the count output reaches S25, CIM3
Both 4 and 35 become idle and receive after that
Just waiting for a signal to come in
turn into. By the way, in this system, from FIG.
As can be seen, what is coupled to the signal transmission line 20 is
There are only two CIMs 34 and 35, so these
Once both have entered the idle state, explained in Fig. 16.
As described above, the data transmission operation starts forever.
Not. However, in FIG. 17, CIM3
4, 35 are according to the embodiment of the present invention shown in FIG.
This puts the CIM35 in active mode.
ing. On the other hand, as described above, the CI according to the present invention
The basic operation of M is the same as that of CIM in FIG.
Therefore, even if it is in the idle state,
Sequence counter 303 is clock φ_MThe count of
It continues as it is. Therefore, in the system shown in FIG.
CIM34 and 35 go into idle after Charize
And after that, the CIM35 in passive mode
It remains idle, but CIM34
Since it is set to the active mode, the automatic transmission circuit 33
0 is activated, and as a result, sequential cow
Predetermined after the count output of the computer 303 reaches S254.
Signal LODO49 is generated at the timing of
S49 is loaded to the output of the local counter 303. As already described, this CIM 34,3
5 also, as described in FIG. 3 to FIG.
It is transmitted by the count data of the sequential counter 303.
The sending operation is controlled. Therefore, the CIM34 sequence
When the output data of the counter 303 is set to S49,
The operation of this CIM 34 is D from the previous idle state.
Jump to UMMY state and then this sequencer
25-bit “0” is sent by the step of the counter 303.
Signal and subsequent data TXD transmission operation from S74
Will enter. Thus, once the data from CIM34
This data is in the idle state when the transmission of
Received by CIM 35, resulting in CIM 34 and
The data transmission with 35 is alternated in DIO mode.
It is performed for each ram, and two CIMs 34 and 35
Data transmission by the one-to-one transmission system
become. Therefore, at this time, CIM34 and CIM35
A state transition diagram is shown in FIG. On the other hand, in this way, the CIMs 34 and 35 are
The data transmission operation between
Transmission error occurs while data transmission is being performed by
If so, both CIMs 34 and 35 are idle
Then, the data transmission operation is stopped again. However, even at this time, the CIM34
Is in the active mode, sequence counter 30
When the count output of 3 reaches S254, the seek is resumed.
S49 is loaded into the counter 303 and automatically
Data transmission is started. Therefore, according to the CIM according to this embodiment,
The active mode and passive mode.
Then, a one-to-one transmission system is constructed as shown in FIG.
You can always perform stable data transmission just by
A small data transmission system at low cost.
Can be Now, the mode in one embodiment of the present invention.
For selection and switching of I / O buffer 105 input / output ports
explain about. As already explained, as shown in FIG.
In one embodiment of the present invention, the active in DIO mode.
Mode and passive mode can be selected and set.
In automatic mode, the automatic transmission circuit 330 is activated.
However, other data transmission in DIO mode
The operation and other configurations are the same as those of the CIM shown in FIG.
Therefore, in DIIO mode, the port of I / O buffer 105 is
The directionality of the address is determined by the address, and the address
The number of output ports remains unchanged. For example, in the DIO mode, 4-bit add
The addresses "1" to "D" correspond, but the address
If set to “1”, the I / O buffer 105
Of the ports, 1 bit is an output port and 13 bits are an input
Outputs 13 bits at address "D"
One bit becomes an input port in the port. On the other hand, as described above, as shown in FIG.
In a one-to-one transmission system such as
If you do not match the address of 35, data transmission
It cannot be sent. Therefore, in the system of FIG.
The data sent from one CIM, eg CIM34,
Must be received only by CIM35, while CIM3
The data sent by 5 is received only by CIM34
I / O buffer 1 in both of these CIMs 34 and 35
Since the number of input ports and output ports of 05 are made the same
Has a waste of data transmission and has a bit number that can be transmitted.
It cannot be used effectively. That is, from the essence of data transmission,
In one CIM in a simple one-to-one transmission system
Data on the power port to the output port on the other CIM
Therefore, if it is not received, the data was transmitted.
The number of input ports in one CIM
Equals the number of output ports in the other CIM and
The number of output ports of one CIM in the pair is the input of the other CIM
Most preferably it should be equal to the number of ports. Therefore, in this embodiment, it depends on the address.
I / O buffer 105 I / O port switching is
In Cube mode, the same operation as in the CIM of FIG. 3 is performed.
When set to Chib mode,
On the contrary, the number of addresses corresponds to the number of input ports.
I am doing it. For example, now, the CIMs 34 and 35 of FIG.
Is set to address "1", CIM3
5 out of 14 ports of I / O buffer 105
One is an output port and 13 is an input port
And in CIM34 which is in active mode, the output port is
13 ports, 1 input port for 1: 1 transmission
The data transfer function can be fully utilized. As described above, the CI of the present invention is
When M is set to active mode, power on
Sequence or after the data transmission is interrupted.
Unta 303 advances to S254 and then starts automatic transmission operation
enter. Therefore, now, the clock φ_MData by
If the transmission speed of 250Kbir / Sec is about 1m
The automatic transmission operation starts during the waiting time of Sec.
Is the maximum number of bits of sequence counter 303 and
It goes without saying that the lock frequency can be set arbitrarily.
Yes. Further, in the embodiment shown in FIG.
Set the time until automatic transmission is started using Unta 303
Configuration required for operation in active mode
Addition is low and cost is low. Incidentally, this active mode and passive mode
For the CIM that can be set and operated,
Further details are given in the specification of Japanese Patent Application No. 58-104880.
It has been revealed. [0145] As described above, according to the present invention,
The function selection of CIM is managed by the combination of input by group.
Since it was decided to use Trix, many function-based selections were made.
Can be done with a minimum number of inputs and the required number of terminal pins
Can be effectively reduced to LSI by suppressing
Moreover, it can be used by switching to many functions.
A highly versatile CIM can be easily provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing an example of an integrated wiring system in a vehicle. FIG. 2 is an explanatory diagram showing an example of a data transmission system using CIM. FIG. 3 is a block diagram showing a conventional example of CIM. FIG. 4 is an explanatory diagram showing switching of modes by addresses. FIG. 5 is a functional block diagram in a DIO mode. FIG. 6 is an explanatory diagram showing an example of data contents. FIG. 7 is an explanatory diagram of a transmission waveform. FIG. 8 is a functional block diagram in AD mode. FIG. 9 is an explanatory diagram of a transmission waveform. FIG. 10 is a functional block diagram in MPU mode. FIG. 11 is a block diagram showing an embodiment of a terminal processing device according to the present invention. FIG. 12 is an explanatory diagram of mode select input according to an embodiment of the present invention. FIG. 13 is an explanatory diagram showing an example of matrix selection by address input and mode select input according to the present invention. FIG. 14 is a block diagram showing an embodiment of an abnormality detection circuit according to the present invention. FIG. 15 is a block diagram showing another embodiment of the abnormality detection circuit according to the present invention. FIG. 16 is a conceptual diagram of a small-scale data transmission system. FIG. 17 is a conceptual diagram showing an embodiment of a one-to-one transmission system using the terminal processing device according to the present invention. FIG. 18 is an operation explanatory diagram of the one-to-one transmission system using the terminal processing device according to the present invention. [Description of Codes] 60 CIM Package 61 to 84 Terminal Pin 101 Control Circuit 102 Synchronous Circuit 104 Shift Register 105 I / O Buffer 106 A / D Control Circuit 303 Sequence Counter 304 Sequence Decoder 305 Abnormality Detection Circuit 306 Address Decoder 307 Address Comparison Circuit 308 Error detection circuit 330 Automatic transmission circuit 331 Mode decoder

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akira Hasegawa             2520, Takaba, Katsuda City, Ibaraki Prefecture             Hitachi Sawa Factory

Claims (1)

[Claims] 1. The shift register (104) and data of the shift register (2) as a serial signal (TXD).
0) and a control circuit for receiving a serial signal (RXD) from the data transmission path and storing the serial signal (RXD) in the shift register, the communication processing circuit element comprising: At least a pair of input / output terminals (64, 66) for transmitting and receiving data between the transmission line and the control circuit, and a plurality of terminals connected in parallel with the shift register
(71 to 84), and further includes a switching circuit (306 or 331) for switching the input / output direction of the plurality of terminals, which is a circuit element for communication processing. 2. The circuit element for communication processing according to claim 1, wherein the plurality of input / output terminals connected in parallel with the shift register are connected to a microcomputer via a data bus. 3. In Claim 1, The shift register and the plurality of terminals are connected in parallel via an I / O buffer, and the plurality of terminals are connected to an arbitrary electric device. Circuit element for communication processing. 4. The shift register (104) and data of the shift register (2) as a serial signal (TXD).
0) and a control circuit for receiving a serial signal (RXD) from the data transmission path and storing the serial signal (RXD) in the shift register, the communication processing circuit element comprising: At least a pair of input / output terminals (64, 66) for transmitting and receiving data between the transmission line and the control circuit, and a plurality of terminals connected in parallel with the shift register
(71 to 84), a switching circuit (306 or 331) for switching the input / output directions of the plurality of terminals, and a serial signal (R) received from the data transmission path (20).
A circuit element for communication processing, characterized in that it incorporates an abnormality detection circuit for detecting a system abnormality by monitoring a state of (XD) and generating a fail-safe signal when the system abnormality occurs. 5. The shift register (104) and data of the shift register (2) as a serial signal (TXD).
0) and a control circuit for receiving a serial signal (RXD) from the data transmission path and storing the serial signal (RXD) in the shift register, the communication processing circuit element comprising: At least a pair of input / output terminals (64, 66) for transmitting and receiving data between the transmission line and the control circuit, and a plurality of terminals connected in parallel with the shift register
(71 to 84), further includes a switching circuit (306 or 331) for switching the input / output directions of the plurality of terminals, and shifts a signal from a load connected to a part of the plurality of terminals. A / Captured as digital signal in register
A communication processing circuit element having a built-in D conversion interface.