JPH08213613A - Vertical semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE: To enhance the breakdown strength while decreasing the leakage current in an accumulation type MOSFET. CONSTITUTION: The near part of the end part of a trench 52 with a gate electrode 46 buried therein and the outer side on the outermost side are made to have the same conductivity type as that of a substrate so that an n<+> source region 44 may be formed in the part excluding the parts so that an active region is inside a depletion layer formed when a gate is negative-biased. Besides, a low concentration n epitaxial layer 42 is formed on a high concentration n<+> substrate 41 and then lower concentration n-epitaxial layer 43 is formed on the layer 42 while the trench 52 reaching the n epitaxial layer 42 is formed from the surface so as to fill up the inside of the trench 52 with a gate electrode 46 through the intermediary of a gate oxide film 45. Through these procedures, the breakdown strength sharing ratio on the n epitaxial layer 42 is increased so that the ratio of the gate oxide film may be reduced thereby enhancing the breakdown strength as the whole element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical semiconductor device for switching, which has a low withstand voltage and a low on-resistance and handles a relatively large amount of electric power, which is used in a power source section of a disk drive device, an electric component for automobiles, etc.

[0002]

2. Description of the Related Art Conventionally, the power supply voltage of a control system such as an electric component for an automobile or a disk drive has been predominantly 5V. However, due to high-speed processing of computers, low power consumption, and consideration of design for longer life of battery-using devices due to the expansion of rechargeable secondary batteries, mainstream power supply voltage is lower than 5V. It is going to shift to 3.3V or 1.5V which is lower. When the power supply voltage becomes low, the voltage drop in the semiconductor element used cannot be ignored, and a semiconductor element having a lower ON resistance is required.

Used in the above-mentioned application fields,
DMOSFET (double-diffusion type metal-oxide film), which is one of power devices with low breakdown voltage and low on-resistance that handles relatively large power,
FIG. 6 shows a sectional view of the main part of the semiconductor field effect transistor). What is shown in the figure is a unit portion of an active region that performs current switching, and in actual semiconductor devices, many structures as shown in the figure are often integrated. In the figure, an acceptor formation type is selectively formed on a surface layer of an epitaxial substrate in which an n epitaxial layer 2 having the same conductivity type and a low impurity concentration is laminated on an n ⁺ substrate 1 containing a high concentration donor formation type impurity. The p base region 11 containing impurities is formed, and the n source region 4 is formed in a part of the surface layer of the p base region 11. Then, on the surface of the p base region 11 sandwiched between the n source region 4 and the n epitaxial layer 2 and on the exposed surface portion of the n epitaxial layer 2, a gate made of polycrystalline silicon is provided via a gate oxide film 5. An electrode 6 is provided. Further, a source electrode 8 that is in common contact is provided on the surfaces of the n source region 4 and the p base region 11, and a drain electrode 9 is provided on the back surface of the n ⁺ substrate 1. In the figure, the source electrode is extended to above the gate electrode 6 via the insulating film 7. In this DMOSFET, a voltage is applied between the drain electrode 9 and the source electrode 8, and the gate electrode 6
When a signal having a positive value or more is applied to, a channel of the inversion layer is generated in the surface layer of the p base region 11 immediately below the gate electrode 6, and electrons pass from the n source region 4 through the channel,
It flows into the n epitaxial layer 2 and reaches the n ⁺ substrate 1 according to the electric field, and the source electrode 8 and the drain electrode 9
There is continuity between the two. That is, the current flows from the drain electrode 9 to the source electrode 8. When the signal from the gate electrode 6 is removed, the channel disappears and the source electrode 8 and the drain electrode 9 are cut off from each other. A semiconductor element having a structure in which electrodes are provided on both main surfaces of the semiconductor substrate as shown in the figure and a current flows in the thickness direction of the semiconductor substrate is called a vertical semiconductor element. It is suitable for a power device because it can have a high utilization rate and a large current capacity. When the on-resistance of the vertical DMOSFET in conduction is estimated for each generation component, it is n for securing a withstand voltage in a high withstand voltage element.
The contribution of the epitaxial layer 2 is high, and the contribution of the channel resistance is not so high. However, in the low breakdown voltage element, since the thickness of the n epitaxial layer 2 for ensuring the breakdown voltage may be small, the ratio of the channel resistance to the ON resistance is high.

Therefore, as one of the methods for reducing the channel resistance, UMOSFE having a gate having a trench structure is used.
The T was devised. FIG. 7 shows a sectional view of the main part of the UMOSFET. 6 is different from the DMOSFET in FIG. 6 in that a trench 12 is formed in the surface layer of the n-epitaxial layer 2 so as to penetrate the p-base region 11 and the gate electrode 6 is embedded in the trench 12 via a gate oxide film 5. That is the point. Reference numeral 7 is an insulating film. The positive voltage signal applied to the gate electrode 6 switches the current between the drain electrode 9 and the source electrode 8 as in the DMOSFET of FIG. This UMOSFET is a DMOSF of FIG.
Compared to ET, the use of a trench gate allows a wider channel area (gate area) per unit area of the semiconductor element, and does not cause a narrowing of the channel due to the junction-type FET effect, thus lowering the channel resistance. Yes, it's actually heavily used.

Recently, B. J. Baliga et al. Have reported a storage MOSFET (hereinafter referred to as ACCUFET) having a trench gate that can further reduce the channel resistance.
Electron Device Letters Vol.13 No.8 427
Page 1992]. Figure 8 shows the structure of the main part of the ACCUFET.
Shown in In the figure, an n epitaxial layer 2 having a low impurity concentration is formed on an n ⁺ substrate 21 having a high impurity concentration.
An n source region 24 is formed in the surface layer of an epitaxial substrate in which 2 layers are stacked. Then, n ⁺ source region 24 and n epitaxial layer 22 are penetrated from the substrate surface to n ⁺
A trench 32 reaching the substrate 21 is formed,
Inside the trench 32, a gate electrode 26 made of polycrystalline silicon is buried via a gate oxide film 25. A source electrode 28 is provided on the front surface of the n ⁺ source region 24, and a drain electrode 29 is provided on the back surface of the n ⁺ substrate 21. In the figure, the source electrode 28 extends to above the gate electrode 26 via the insulating film 27. Typical shape parameters and the like are as follows. The specific resistance of the n ⁺ substrate 21 is 0.
002 Ωcm, the impurity concentration and the thickness of the n epitaxial layer 22 are 1 × 10 ¹⁴ cm ^-3 and 2.5 μm, respectively, the width and the depth of the trench 32 are both 3 μm, and the n source region 24 is formed.
The dose and thickness are 1.3 × 10 ¹⁵ cm ^-2 ,
The gate oxide film 25 has a thickness of 0.5 μm and a thickness of 70 nm.

FIG. 9 is a perspective sectional view of the ACCUFET. In this ACCUFET, the drain electrode 2
9. A voltage is applied between the source electrode 28 and the gate electrode 26.
When a positive bias is applied to the n epitaxial layer 22
A storage layer 33 is formed in a portion along the gate electrode 26, and electrons pass from the n ⁺ source region 24 through the storage layer 33,
flows into the n-type epitaxial layer 22 and n ⁺
Reaching the substrate 21, conduction is established between the drain electrode 29 and the source electrode 28.

Conversely, if a negative bias is applied to the gate electrode 26, the storage layer 33 disappears and the depletion layer expands, and the drain electrode 29 and the source electrode 28 are cut off from each other. In this element, since the channel portion in the on state is not the inversion layer but the storage layer, the mobility of carriers in the channel portion can be increased and the channel resistance can be reduced. In addition, since it has no pn junction in the current path, it has the advantage that there is no effect of a parasitic diode.

On the other hand, the ACCUFET is turned off by the spread of the depletion layer from the trench gate. Therefore,
Even if the gate is negatively biased when the source-drain voltage is applied, if there is a wide portion where the trench 92 is not provided around the chip as shown in FIG. 10, the depletion layer 95 is formed only around the trench and the trench 92 On the outside, there is a path through which leakage current flows, and a sufficient breakdown voltage cannot be obtained.

As a countermeasure against this, a breakdown voltage structure proposed by Dr. Baliga et al. Is shown in FIG. In FIG.
A p-type diffusion region 36 is provided below the n ⁺ source region 24 outside the outermost trench 32 of the active portion where a current flows, and a p-type diffusion region 36 is provided between the diffusion region 36 and the n epitaxial layer 32.
The n-junction maintains the breakdown voltage and reduces the leakage current. Reference numeral 37 is a trench for element isolation.

[0010]

However, in the structure of FIG. 11, since it partially includes the pn junction, it becomes a structure having a parasitic diode, and the bidirectional operation (the source and the drain are applied in opposite polarities) is lost. It causes a defect such as being broken.

Further, the above ACCUFET has the following problems. Due to the fact that the surface of the gate oxide film 25 formed in the trench 32 is an etching surface and has a corner portion, the withstand voltage of the gate oxide film formed on a normal flat portion (about 8 MV / cm). In the structure of the ACCUFET of FIG.
The voltage applied between the drains is almost applied to the gate oxide film 25 at the bottom of the trench 32, and the breakdown voltage cannot be higher than that of the gate oxide film 25. That is, a high breakdown voltage element cannot be obtained.

The ACCUFET applies a negative voltage to the gate electrode 26 when it is switched off. Then, a depletion layer spreads in the channel region, is connected to the depletion layer spreading from the gate electrode 26 of the adjacent trench 32, and if the entire drift region is depleted, the flowing current can be cut off. That is, if the pitch of the trenches 32 is not narrowed considerably, a leakage current flows when a voltage is applied to the device at the time of off. On the other hand, if the width is made narrower, the current path becomes narrower and the on-resistance increases.

In view of the above problems, it is an object of the present invention to provide a vertical semiconductor element which has bidirectional operability, has a high breakdown voltage, has a small leakage current, and operates in a storage type.

[0014]

[Means for Solving the Problems] In order to solve the above problems,
The present invention is directed to a high-concentration first-conductivity-type semiconductor substrate and a high-concentration semiconductor layer formed on the surface layer of a semiconductor laminated plate in which semiconductor layers having the same conductivity type and a lower concentration than the first-conductivity-type semiconductor substrate are laminated. A first conductivity type source region, a trench penetrating the first conductivity type source region from the surface of the semiconductor laminated plate, a gate electrode filled in the trench through a gate oxide film, and formed on the gate electrode In a single conductivity type vertical semiconductor element having a formed insulating film, a source electrode provided on the surface of the first conductivity type source region, and a drain electrode provided on the back surface of the first conductivity type semiconductor substrate, It is assumed that the surface layer of the portion near the end of the trench filling the gate electrode and the outer portion of the outermost trench is of the first conductivity type, and the source region of the first conductivity type is formed except for the portion.

Particularly, it is preferable that the first-conductivity-type source region is formed inside the end portion of the trench gate by a distance equal to or more than the trench interval, and the source is provided between the outermost trench and the second outermost trench. It is preferable to have at least one portion where a region is not formed. The semiconductor layer is composed of a first semiconductor layer having a concentration lower than that of the first conductivity type semiconductor substrate and a second semiconductor layer having the same conductivity type and a concentration lower than that of the first conductivity type semiconductor substrate, and the trench penetrates the second semiconductor layer. It may reach the first semiconductor layer.

In particular, it is preferable that a part of the surface layer of the second semiconductor layer between two adjacent trenches has the second conductivity type region. As a method for manufacturing the vertical semiconductor device as described above, a high-concentration first-conductivity-type semiconductor substrate has an epitaxial layer of the same conductivity type and a low concentration, and an epitaxial layer of the same conductivity type and a lower concentration on the epitaxial layer. It is assumed that a double epitaxial wafer in which is laminated is used.

[0017]

By taking the above-mentioned means, the surface layer of the portion near the end of the trench in which the gate electrode is filled and the outer portion of the outermost trench are of the first conductivity type. If the gate is negatively biased, a depletion layer is formed between the first conductivity type source region and the peripheral portion.

In particular, the first-conductivity-type source region is formed inside the end of the trench gate by a distance equal to or more than the trench interval, and the source region is not formed between the outermost trench and the second outermost trench. If at least one is provided, the separation effect of the depletion layer can be enhanced. The first semiconductor layer plays a part of the source-drain voltage by providing a trench that penetrates the first conductivity type source region and the second semiconductor layer and reaches the first semiconductor layer from the surface of the semiconductor laminate. As a result, the voltage carried by the gate oxide film is reduced, and as a result, the breakdown voltage of the device can be improved.

Further, by forming a second conductivity type region in a part of the surface layer of the second semiconductor layer between two adjacent trenches, a depletion layer extending from one trench and a second conductivity region are formed. Therefore, the depletion layer extending from the adjacent trench can be easily reached, and the second semiconductor layer can be further depleted, so that the leakage current can be reduced.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the ACC of the first embodiment of the present invention.
FIG. 7 is a plan view showing a state in which an insulating film on a semiconductor and an electrode on an end portion of a trench gate of a UFET are removed. Except for the peripheral portion of the semiconductor chip, a trench 52 having a gate electrode 46 made of polycrystalline silicon is formed inside via a gate oxide film 45, and the inside of the trench 52 except the end portion and the outermost trench 52 is formed. At the n ⁺ source region 44
Are formed.

FIG. 2 shows the ACCUF of the first embodiment of FIG.
The sectional view in the AA line of ET is shown. This figure also shows the insulating film and the electrodes on the semiconductor. In the figure, on an n ⁺ substrate 41 having a specific resistance of 0.002 Ωcm and a thickness of 300 μm, an n epitaxial layer 42 having an impurity concentration of 4 × 10 ¹⁵ cm ⁻³ and a thickness of 6.0 μm, and further n epitaxial layer thereon. The impurity concentration is 1 × 10 ¹⁴ cm ⁻³ , which is lower than that of the layer 42, and the impurity concentration is 1 × 10 ²⁰ cm in a part of the surface layer of the epitaxial substrate on which the n ⁻ epitaxial layer 43 having a thickness of 4.5 μm is laminated. ^-3 , thickness 0.2μ
An n ⁺ source region 44 of m is formed. And n
A trench 52 having a width of 1.8 μm and a depth of 5.5 μm reaching the n epitaxial layer 42 is formed through the ⁺ source region 44 and the n ⁻ epitaxial layer 43, and the trench 52 has a thickness of 0. A gate electrode 46 made of polycrystalline silicon is embedded through a 1 μm gate oxide film 45. A source electrode 48 made of an aluminum-silicon (Al-Si) alloy is provided on the surface of the n ⁺ source region 44, and a drain electrode 49 of an Al-Si alloy is also provided on the back surface of the n ⁺ substrate 41. ing. In the figure, the source electrode 48 is extended to above the gate electrode 46 via the insulating film 47.

In this ACCUFET, when a voltage is applied between the drain electrode 49 and the source electrode 48 and a positive bias is applied to the gate electrode 46, the accumulation layer 53 is formed in the portion of the n ⁻ epitaxial layer 43 along the gate electrode 46. Then, electrons flow from the n source region 44 through the storage layer 53 into the n epitaxial layer 42, reach the n ⁺ substrate 41 according to the electric field, and establish conduction between the source electrode 48 and the drain electrode 49. When a negative bias is applied to the gate electrode 46, the storage layer 53 disappears and the depletion layer expands, and the source electrode 48 and the drain electrode 49 are cut off from each other.

In FIG. 1, there are three features. First, the n source region 44 is formed except for the end portion of the trench 52. Secondly, the distance L2 between the n source region 44 and the end of the trench 52 is larger than the interval L1 of the trench 52 (for example, 0.1 to 5 μm). Thirdly, a 1 μm gap is formed between the outermost trench 52 and the second outermost trench 52 so that the n source region 44 is not formed so that the n source region 44 does not contact the outermost trench 52. did. By doing so, a depletion layer having a sufficiently wide width is formed between the n source region 44 and the peripheral portion, and the leakage current in the peripheral portion can be prevented.

This structure can be realized by selectively performing ion implantation for forming the n source region 44 using a photoresist mask, for example. Further, in this element, the n epitaxial layer 42 provided below the n ⁻ epitaxial layer 43 bears a part of the voltage between the source and the drain, thereby lowering the voltage carried by the gate oxide film 45 and improving the breakdown voltage. To be achieved. Further, since the channel in the ON state is the storage layer 53 instead of the inversion layer, the carrier mobility of the channel can be increased and the channel resistance can be reduced.

Moreover, the ACCUFET of the embodiment of the present invention
Is an ACCUFET having a bidirectional operability in which the source and the drain are exchanged, because the current path does not have a pn junction and the parasitic diode does not have an effect. FIG. 4 shows the breakdown voltage distribution of the ACCUFET of the first embodiment shown in FIGS. The horizontal axis is pressure resistance, and the vertical axis is frequency of appearance. For comparison, the withstand voltage distribution of the conventional ACCUFET shown in FIG. 8 is also shown. It can be seen that the ACCUFET of the first embodiment in FIG. 1 has an average breakdown voltage increase of 40% as compared with the ACCUFET of the conventional structure. ACCUFET of conventional structure
Then, the bottom of the trench 32 has a high concentration on the substrate 2
Since it reached 1, the depletion layer did not spread at the bottom of the trench 32, and a strong electric field was applied to the gate oxide film 25 at the bottom of the trench 32, especially at its corners. In the ACCUFET of the first embodiment of FIG. 1, since the depletion layer also spreads below the trench 52, the gate oxide film 45 at the bottom of the trench 52 is formed.
Since the withstand voltage required by the device may be small, it is considered that the withstand voltage as a whole is improved.

The device of FIG. 1 is manufactured by the following manufacturing method.
Obtained. Arsenic-doped with a specific resistance of 0.002 Ωcm
n⁺The impurity concentration is 5 × 10 on the substrate 41.^Fifteen
cm ^-3, 6.0 μm thick phosphorus-doped n-epitaxial
Layer 42, with an impurity concentration of 1 × 10¹⁴cm^-3,thickness
4.7 μm phosphorus-doped n^-Deposit the epitaxial layer 43
A stacked double epitaxial wafer is prepared. Tip
An initial oxide film is formed on the periphery, and then a dose is applied to the surface layer.
Is 1.3 × 10^Fifteencm^-2Arsenic ion implantation and
Heat treatment, n⁺The source region 44 is used. Next, illustrated
Not applied, but apply photoresist, silicon oxide film
By patterning the photoresist and the oxide film.
Squeeze n⁺Source regions 44 and n^-Epitaxia
And etching the layer 43 to make the width and depth 1.8 each.
A trench 52 of μm and 5.5 μm is formed. Then hot acid
The inner surface of the trench 52 is formed with a thickness of 0.1 μm.
The oxide film 45 is formed, and then a low pressure CVD method is used to
After depositing polycrystalline silicon in the wrench 52, the trench
The polycrystalline silicon other than the inside is removed to form the gate electrode 46.
Form. Then, the gate electrode 46 and the source electrode 48
Insulating film 47 is formed to separate the spaces between
Minute contact hole is formed and Al-Si alloy is evaporated.
Then, the source electrode 48 is formed by patterning. Change
To n⁺Al-Si alloy on the back surface of the substrate 41
To form a drain electrode 49. in this way,
Step of introducing n-type impurities using an epitaxial wafer
And trench formation process is the main process, and p-type impurity
There is an advantage that a step of introducing a product is unnecessary.

FIG. 3 shows the ACCUF of the second embodiment of the present invention.
The principal part sectional drawing of ET is shown. The difference from the first embodiment of FIG. 1 is that the p region 70 is formed deeper than the n ⁺ source region 64 in the surface layer of the n ⁻ epitaxial layer 63 between two adjacent trenches 72. Then, the source electrode 68 is in contact with the surface of the p region 70. With such a structure, the depletion layer extending from one gate can easily reach the depletion layer extending from the adjacent trench 72 due to the p region 70, and the channel region can be further depleted. Leakage current can be reduced. In FIG. 2, the surface of the p region 70 is dug down from the surface of the n source region 64, but it is not always necessary to dug down, and the height may be the same. The dug down has an advantage that the diffusion heat treatment time for forming the p region 70 can be shortened.

FIG. 5 shows the prototype A of the second embodiment of FIG.
The leakage current distribution of CCUFET is shown. The horizontal axis is the leakage current,
The vertical axis is the frequency of appearance. ACC with conventional structure for comparison
The UFET leakage current distribution is also shown. It can be seen that in the ACCUFET of the first embodiment of FIG. 1, the leakage current is reduced by about one digit as compared with the ACCUFET of the conventional structure.

[0029]

As described above, in the storage type vertical semiconductor device of the present invention, the surface layers of the portion near the end of the trench in which the gate electrode is filled and the outer portion of the outermost trench are the first. It is of a conductive type, and by forming the source region of the first conductivity type excluding that part, it has bidirectional operability without the action of a parasitic diode, and a depletion layer of sufficient width suppresses leakage current and withstands voltage. Can be improved. Further, the semiconductor layer is composed of a first semiconductor layer having a concentration lower than that of the first conductivity type semiconductor substrate and a second semiconductor layer having the same conductivity type and a concentration lower than that of the first semiconductor layer on the first conductivity type semiconductor substrate. By providing the reaching trench, the voltage applied to the gate oxide film inside the trench can be reduced and the breakdown voltage of the device can be improved. Furthermore, by forming the second conductivity type region in the surface layer of the second semiconductor layer between two adjacent trenches, depletion of the second semiconductor layer at the time of voltage application is promoted, and leakage current can be reduced. .

According to the present invention, the breakdown voltage is 50 V and the leakage current is 10
It was possible to realize a storage vertical semiconductor element of μA or less and improve the yield.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of an ACCUFET according to a first embodiment of the present invention.

FIG. 2 is a plan view of the ACCUFET of FIG. 1 with the insulating film and electrodes removed.

FIG. 3 is a sectional view of an essential part of an ACCUFET according to a second embodiment of the present invention.

FIG. 4 is a comparison diagram of the breakdown voltage distribution in the ACCUFET of the first embodiment of the present invention and that of the conventional ACCUFET.

FIG. 5 is a comparison diagram of the leakage current distribution in the ACCUFET of the second embodiment of the present invention and that of the conventional ACCUFET.

FIG. 6 is a sectional view of a main part of a conventional DMOSFET.

FIG. 7 is a sectional view of a main part of a conventional UMOSFET.

FIG. 8 is a sectional view of a main part of a conventional ACCUFET.

FIG. 9 is a perspective sectional view of a conventional ACCUFET.

FIG. 10 is a plan view of an example of a conventional ACCUFET with an insulating film and electrodes removed.

FIG. 11 is an end cross-sectional view of another example of a conventional ACCUFET.

[Explanation of symbols]

1, 21, 41 n ⁺ substrate 2, 22, 42 n epitaxial layer 4, 24, 44, 64 n ⁺ source region 5, 25, 45 gate oxide film 6, 26, 46 gate electrode 7, 27, 47 insulating film 8, 28, 48, 68 Source electrode 9, 29, 49 Drain electrode 11 p Base region 12, 32, 52, 72, 92 Trench 33, 53 Storage layer 36 p-type diffusion region 37 Trench 43, 63 n ^- Epitaxial layer 70 p-type region 95 Expansion of depletion layer

Claims (6)

[Claims] 1. A high-concentration first-conductivity-type source region formed on a surface layer of a semiconductor layer of a semiconductor laminated plate in which semiconductor layers of the same conductivity type and a lower concentration than the semiconductor substrate are laminated on a first-conductivity-type semiconductor substrate. A trench penetrating the first conductivity type source region from the surface of the semiconductor laminate, a gate electrode filled in the trench via a gate oxide film, and an insulating film formed on the gate electrode, In a vertical semiconductor element having a source electrode provided on the front surface of the first conductivity type source region and a drain electrode provided on the back surface of the first conductivity type semiconductor substrate, in the vicinity of an end of a trench filled with a gate electrode A vertical semiconductor device, wherein the surface layer of the portion and the outer portion of the outermost trench is of the first conductivity type, and the source region of the first conductivity type is formed except for the portion. 2. The vertical semiconductor element according to claim 1, wherein the first-conductivity-type source region is formed inside the trench gate by an amount equal to or more than the trench interval. 3. The vertical semiconductor device according to claim 2, wherein at least one portion in which the source region is not formed is provided between the outermost trench and the second outermost trench. 4. The semiconductor layer comprises a first semiconductor layer having a concentration lower than that of a semiconductor substrate of a first conductivity type and a second semiconductor layer having the same conductivity type thereon and a concentration lower than that of the first semiconductor layer, and the trench is a second semiconductor layer. 4. The vertical semiconductor element according to claim 1, wherein the vertical semiconductor element penetrates two semiconductor layers to reach the first semiconductor layer. 5. The vertical semiconductor device according to claim 4, wherein a part of the surface layer of the second semiconductor layer between two adjacent trenches has a second conductivity type region. 6. A double epitaxial wafer having an epitaxial layer of the same conductivity type and a concentration lower than that of the semiconductor substrate on a semiconductor substrate of the first conductivity type, and a double epitaxial wafer having an epitaxial layer of the same conductivity type and a concentration lower than that of the semiconductor substrate. The surface layer of the portion near the end of the trench filling the gate electrode and the outer portion of the outermost trench is of the first conductivity type, and the first conductivity type source region is formed except for that portion. Manufacturing method of vertical semiconductor device.