JPH08204539A - Signal transmission circuit - Google Patents

Abstract

PURPOSE: To reduce noise and to secure a sufficient amplitude in the signal transmission between ICs where the signal amplitude is smaller than a CMOS level or a TTL level. CONSTITUTION: On-chip termination resistor means 42, 43 in a transmitter side IC 40 are switched oh/off and a signal of an H or L level is sent to a receiver side IC 60 via a transmission line 20 as the result of on/off switching. Since the transmission line 20 is terminated by termination resistors 21-24, a current flowing to a ground level point via a resistor means 42 in the case of L level in comparison with the transmission line 20 connected only to a termination potential point Vt to reduce switching noise. Furthermore, the on-chip termination resistor means 42, 43 are turned on/off in a complementary way to form the on-chip termination resistor with respect to the transmission line 20, then the effective impedance of the transmission line 20 is not decreased. Thus, the amplitude of the transmission signal is sufficiently secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit (interface circuit) for transmitting and receiving a binary signal between semiconductor integrated circuits manufactured by CMOS technology.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference 1: Nikkei Electronics, [556] (1992)
-6-8) “Microprocessor, CP that has entered 100MHz
U-board design changes "P.110-113 Reference 2; US Pat. No. 5,023,488 In recent years, TTL level or CMOS which has been conventionally used has been used with the increase in the transmission / reception speed of binary signals between CMOS semiconductor integrated circuits. It is difficult to send and receive signals at the level because of TTL level and CM.
The output amplitude of the transmission circuit at the OS level is 2V each
It is disadvantageous for high-speed operation because it is large and about 5V. A printed circuit board (for example, C) on which a plurality of semiconductor integrated circuits (hereinafter referred to as ICs) are mounted is also affected by switching noise or ground bounce.
Designing PU boards, etc.) has become extremely difficult. These are described in detail in Document 1 above.

On the other hand, Reference 2 proposes GTL (Gunning Transceiver Logic) for realizing high-speed signal transmission, and TT
An interface circuit is proposed in which the signal amplitude is made smaller than that of the L level and the CMOS level for transmission. In the conventional interface circuit based on Document 2, both ends of the transmission line are terminated via terminating resistors to a termination potential Vt lower than the power supply potential Vcc used in each IC, and for example, an NMOS transistor is used in the transmission circuit in the IC. By switching, the transmission line is driven between the potential Vt and the ground GND.
The signal propagated through the transmission line is I having the receiving circuit.
Input to C. The IC having the receiving circuit converts the received signal into the CMOS level. By doing so, the signal amplitude of the transmission signal is reduced, enabling high-speed signal transmission.

[0004]

However, the conventional signal transmission circuit has the following problems (1) and (2). (1) In the configuration of the signal transmission circuit based on Document 2, switching noise is large when the signal is switched between the “H” level and the “L” level. Therefore, there is a problem that the quality of the transmission signal waveform deteriorates. FIG. 2 is a circuit diagram showing a conventional signal transmission circuit based on Document 2. Both ends of the transmission line 1 formed on the printed circuit board are terminated to the termination potential Vt by resistors 2 and 3. Transmission line 1 and a plurality of ICs 4 to 7 connected to arbitrary places of the transmission line 1
And form a bus-type signal transmission circuit. IC4
~ 7 has a transmission circuit, a reception circuit or a transmission / reception circuit,
Each off-chip terminal is connected to the transmission line 1. For example, IC5 has a transmitting circuit and IC7 has a receiving circuit. The transmitter circuit includes an input terminal 5-1 to which a CMOS logic level input signal is input from a logic circuit (not shown) in the IC 5, a CMOS inverter 5-2, and an N-channel MOSFET (hereinafter, simply referred to as NMOS) 5
-3, the NMOS 5-3 forms an open-drain type off-chip output, and its drain is connected to the transmission line 1. The receiving circuit includes a reference potential input terminal 7-1 and a transmission signal input terminal 7 via the transmission line 1.
-2 and a differential amplifier circuit 7-3 for comparing and amplifying the potentials of the input terminal 7-1 and the input terminal 7-2 and outputting a CMOS level signal to the output terminal 7-4. .

Regarding the operating principle of the signal transmission circuit of FIG.
Briefly explained. For example, a plurality of I's operating on a 5V power supply
A plurality of ICs connected to the transmission line 1 in C4 to C7
One of 4 to 7 is alternatively enabled for output. IC
5 is selected, and a binary signal is transmitted from the transmission circuit in IC5 to the reception circuit of IC7 via the transmission line 1. The transmission line 1 such as a microstrip line formed on a printed circuit board has a characteristic impedance of 50 to 70Ω as is well known. Due to the resistors 2 and 3, the transmission line 1 is lower than the power supply voltage Vcc of the ICs 4 to 7, for example, 1.
It is terminated to the termination potential Vt of 2V. Here, the transmission line 1
Has a characteristic impedance of 50Ω, the impedance of each of the resistors 2 and 3 is 50Ω, and the termination potential Vt is 1.2V.
And the on-state output impedance of the NMOS 5-3 of the transmission circuit is 12.5Ω. In the transmission circuit, CMO
The NMOS 5-3 is turned on / off based on the binary signal input to the input terminal 5-1 at the S level. As a result, the transmission line 1 is driven at the "H" level of 1.2 V (= Vt) or the "L" level of 0.4 V. The level of the transmission line 1 set by the transmission circuit is received by the input terminal 7-2 of the IC 7 as a transmission signal. The differential amplifier A21 compares the level of this transmission signal with the reference potential of, for example, 0.8 V input to the reference potential input terminal 7-1. The IC 7 detects the "H" / "L" level of the transmission signal, amplifies it to the CMOS level, and outputs it from the output terminal 7-4.

The switching noise is noise caused by the inductance of the bonding wire and the lead pin of the IC package, and changes in current (di /
The switching noise increases as dt) increases. For example, assuming that the potential Vt is 1.2 V, when the “L” level signal is transmitted from the transmitter circuit of IC5 to the receiver circuit of IC7, the NMOS 5-3 is in the ON state, and the output current of about 32 mA is equal to the termination potential Vt. From I through NMOS 5-3
It flows to GND of C5. When transmitting the "H" level signal, the NMOS 5-3 is in the off state and the output current is 0A. When the transmission signal switches from “L” to “H” or from “H” to “L”, the current of 32 mA changes in an extremely short time. That is, rapid current change (di / dt)
Occurs, and large switching noise is generated.

(2) When the number of ICs connected to the transmission line 1, that is, the number of transmission circuits or reception circuits connected to the transmission line is increased, the amplitude of the "H" level of the transmitted signal waveform becomes insufficient. There is a problem. The off-chip input / output terminal of the IC has a parasitic capacitance of about 1 pF to 10 pF per terminal, and the effective characteristic impedance of the transmission line 1 is considerably low. This is transmission line 1
The reflected wave is generated as a cause of impedance mismatch in the output waveform and the output waveform becomes stepwise. If the transmission line 1 is long and the frequency becomes high, the amplitude of "H" cannot follow the frequency, and the amplitude becomes insufficient. This reduces the input voltage margin in the receiving circuit and, in the worst case, may cause malfunction. FIG. 3 is a diagram showing a configuration of a simulation circuit for the signal transmission circuit of FIG.
(I)-(iii) is a waveform diagram of the simulation result by FIG.

In the simulation circuit of FIG. 3, a transmission circuit 11 is connected to one end of a transmission line 10 having a characteristic impedance Z ₀ and a length of 1 m, and the other end is terminated to a termination potential Vt via a resistor 12. ing. Transmitter circuit 11
Has the same configuration as the transmission circuit shown in FIG. In (i) of FIG. 4, a waveform S13 of the input signal from the input signal terminal 13 of the transmission circuit 11 is shown. (Ii) of FIG.
(Iii) is a simulation result when the characteristic impedance Z ₀ is 50Ω and 29.5Ω, and shows the signal waveform S at the connection point 14 between the transmission circuit 11 and the transmission line 10.
14 and a signal waveform S15 at the connection point 15 of the transmission line 10 and the resistor 12 are shown. When the impedance Z ₀ is 50Ω, each signal waveform S14, S15
Is from "L" level (about 0.2V) to "H" level (1.
2V), it stands up immediately. However, when the impedance Z ₀ is 29.5Ω, it changes stepwise when the signal level rises from “L” to “H”. This indicates that the transmission signal is repeatedly reflected at the end of the transmission line 10 and finally settles at 1.2V which is the “H” level. On the other hand, when the signal changes from the “H” level to the “L” level, a stepwise waveform is formed, but the degree is smaller than when the signal changes from the “L” level to the “H” level. That is, the influence of reflection is small. This is because when the “H” level is output, the output end of the transmission circuit 11 is in the open state and the reflection coefficient Γ = −1 (total reflection), and when the “L” level is output, This is because the output impedance becomes about 10Ω and the reflection coefficient Γ can be suppressed to about −0.5.

[0009]

In order to solve the above-mentioned problems, a signal transmission circuit according to the first to fourth aspects of the present invention includes a transmission circuit in a semiconductor integrated circuit on the transmission side and a semiconductor integrated circuit on the reception side. The transmission line is composed of a reception circuit and a transmission line terminated via a terminating resistor to a termination potential lower than the power supply potential supplied to the transmission side and reception side semiconductor integrated circuits. A binary signal having an amplitude smaller than the voltage between the termination potential and the ground potential is transmitted to the semiconductor integrated circuit on the receiving side via the. Here, in the signal transmission circuit, one end or both ends of the transmission line are terminated to the termination potential via the first termination resistor, and to the ground potential via the second termination resistor different from the first termination resistor. It is terminated. Further, the semiconductor integrated circuit on the transmission side is configured to supply a termination potential. On the other hand, the transmission circuit is provided with the following first and second on-chip termination resistance means. The first on-chip termination resistance means is turned on and off based on the level of the input signal in the transmission circuit, and when in the on state, has a predetermined impedance between the transmission line and the termination potential supplied to the semiconductor integrated circuit. The connection is made to form an on-chip terminating resistor of the transmission line. The second on-chip terminating resistance means is turned on and off complementarily to the first on-chip terminating resistance means, and when in the on state, the transmission line and the ground potential are connected with a predetermined impedance. An on-chip terminating resistor is formed.

[0010]

In the first to fourth inventions, since the signal transmission circuit is configured as described above, the transmission line is connected to the termination potential and the ground potential by the first and second termination resistors, and A binary signal having an amplitude smaller than the voltage between the ground potentials is transmitted via the transmission line. Here, since the transmission line is connected to the termination potential and the ground potential by the first and second termination resistors, the neutral level of the transmission line becomes an intermediate value between the ground potential and the termination potential, and a signal to be transmitted is transmitted. Both the “H” level potential and the “L” level potential are lowered. Therefore, the amount of current flowing to the ground potential via the transmission circuit is reduced. Further, the first and second on-chip termination resistance means form the termination resistance of the transmission line when the transmission circuit sets the "H" level or the "L" level, and the transmission line is opened. Not in a state. Therefore, the above problem can be solved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a signal transmission circuit showing a first embodiment of the present invention. This signal transmission circuit performs signal transmission between ICs at high speed via the transmission line 20, and the transmission line 20 in FIG. 1 is a model of, for example, a microstrip line of a printed circuit board. Both ends of the transmission line 20 are terminated to a termination potential Vt lower than the power supply potential Vcc via two resistors 21 and 22 which are first termination resistors, and two termination resistors which are second termination resistors. Resistors 23, 24
Through to the ground potential GND. Transmission line 2
For example, four ICs 30 to 60 are connected to any place of 0. Each of the ICs 30 to 60 includes a transmission circuit, a reception circuit, or a transmission / reception circuit, and serves as a transmission side or reception side IC when transmitting signals. In the example of FIG. 1, the IC 40 is a transmitting side IC including a transmitting circuit, and the IC 60 constitutes a receiving side IC including a receiving circuit. The input terminal In of the transmission circuit described in the IC 40 is provided with a CMOS level input signal IN from a logic circuit in the IC 40 (not shown). The input terminal In is connected to the resistance element control circuit 41, and the output side of the resistance element control circuit 41 has the first and second
On-chip terminating resistance means 42, 43 are connected. The on-chip termination resistance means 42 connects the transmission line 20 and I
The on-chip termination resistance means 43 is connected between the termination potential Vt supplied to C40 and the transmission line 20 and the ground potential G.
It is connected between ND. On-chip termination resistance means 42
Is for turning on and off based on the output of the resistance element control circuit 41, and connecting the transmission line 20 and the termination potential Vt in the on state to form an on-chip termination resistance for the transmission line 20. The on-chip terminating resistance means 43 is turned on and off based on the output of the resistance element control circuit 41, and when in the on state, connects the transmission line 20 and the ground potential GND to form an on-chip terminating resistor for the transmission line 20. Is.

FIG. 5 is a circuit diagram showing the structure of the transmission circuit in FIG. 1. In FIG. 5, the resistance element control means 41 and the first element are shown.
And second on-chip termination resistor means 42, 43. When a plurality of transmission circuits are connected to the transmission line 20, one of the plurality of transmission circuits is selected, and only the selected transmission circuit is in the output enabled state. The resistance element control means 41 in the transmission circuit includes an inverter 41-1 that inverts the level of the selection signal EN, a NOR gate 41-3 that inputs the input signal IN and the output of the inverter 41-1 and the input signal IN and the selection signal. An AND gate 41-2 having EN as an input is provided. On the output side of the AND gate 41-2 and the NOR gate 41-3,
First and second on-chip termination resistance means NMOS
The gates 42-1 and 43-1 are connected to each other. The connection point of the two NMOSs 42-1 and 43-1 is an off-chip output terminal, which is connected to the transmission line 20. On the other hand, the receiving circuit in the IC 60 has a differential amplifier 61. The reception signal via the transmission line 20 and the off-chip input terminal 62 and the reference potential via the reference potential input terminal 63 are input to the differential amplifier 61. The output terminal Out of the differential amplifier 61 is connected to a CMOS logic circuit (not shown) in the IC 60.

FIG. 6 is a circuit diagram showing the receiving circuit in FIG. 1, and shows an example of the configuration of the differential amplifier 61. The differential amplifier 61 is a P-channel type M for inputting a received signal to the gate.
OS transistor (hereinafter referred to as PMOS) 61-1
And a PMOS 61-2 for inputting a reference potential to the gate. The drains of the NMOSs 61-3 and 61-4 are connected to the drains of the PMOSs 61-1 and 61-2, respectively, and the sources of the NMOSs 61-3 and 61-4 are connected to the ground potential GND. NMOS 61-
The gates of 3, 61-4 are connected to the drain of PMOS 61-1. The drains of the PMOS 61-5 serving as a current source are connected to the sources of the PMOSs 61-1 and 61-2. The source of the PMOS 61-5 is the power supply potential Vc
The gate of the PMOS 61-5 is connected to the ground potential GND. The drain of the PMOS 61-2 is commonly connected to the gate of the PMOS 61-6 and the gate of the NMOS 61-7. The source of the PMOS 61-6 is connected to the power supply potential Vcc, and the PMOS 61-6
The drain of is connected to the drain of the NMOS 61-7 and is also connected to the output terminal Out. NMOS 61
The source of −7 is connected to the ground potential GND. M
The OS transistors 61-1 to 61-5 have a function of comparing the level of the received signal with a reference potential and amplifying it to a desired potential, and the MOS transistors 61-6 and 61-7 are CMs.
It has a function of converting to an OS level signal. next,
The operation of the signal transmission circuit of FIG. 1 will be described.

ICs 30 to 6 in the signal transmission circuit of FIG.
0 operates at a power supply potential Vcc of 5 V, for example. One of the plurality of ICs 30 to 60 is in the output enabled state by the selection signal EN. For example, the IC 40 is selected to be in an output ready state. Here, it is assumed that the characteristic impedance of the transmission line 20 is set to 50Ω and the resistance value of each of the termination resistors 21 to 24 is set to 100Ω. Also, the first
And the output impedance when the second on-chip termination resistance means 42, 43 are in the on state, that is, the NMOS 42-
It is assumed that the ON resistances of 1,43-1 are set to 12.5Ω. First, a CMOS logic circuit in the IC 40 outputs a CMOS level input signal IN, for example, “L”
It is assumed that it is given to the input terminal In. Resistance element control means 4
1 gives a control signal to the on-chip termination resistance means 42 and 43 based on the level of the input signal IN. The control signal turns on the on-chip termination resistance means 42 and turns on the on-chip termination resistance means 43. That is, NMO
S42-1 turns off and NMOS 43-1 turns on. The “L” level potential V _0L of the transmission line 20 is the terminating resistor 21.
And 24, a NMOS43-1, is set by the terminal potential Vt, approximately V _0L = 0.2V. At this time,
An output current of 16 mA flows from the terminal potential Vt to the ground potential GND of the IC 40 via the off-chip output terminal of the IC 40.

On the other hand, in the receiving circuit of the IC 60, the differential amplifier 61 compares the reference potential, which is set to, for example, 0 and 6 V, with the potential of the transmission line 20, which is 0.2 V, and the comparison result is C.
It is converted to the MOS logic level "L" and output from the output terminal Out. Subsequently, it is assumed that the CMOS-level “H” input signal IN is applied to the input terminal In. The resistance element control means 41 gives a control signal based on the level of the input signal IN to the on-chip termination resistance means 42, 43. The control signal turns on the on-chip termination resistance means 42 and turns on the on-chip termination resistance means 43. That is, the NMOS 42-1 is turned on and the NMOS 43-1 is turned off. Therefore, the current flowing into the ground potential GND of the IC 40 becomes 0A. At this time, the “H” level potential V _0H of the off-chip output terminal of the IC 40 changes the terminating resistors 21 to 21.
24, the NMOS 42-1 and the termination potential Vt, and V _0H = 1.0V. This potential V _0H propagates through the transmission line 20 and is input to the off-chip input terminal 62 in the IC 60 after the propagation delay time determined by the transmission characteristic of the transmission line 20 has elapsed. The receiving circuit of IC60 is
The potential V _{0H of} 1.0 V is compared with the reference potential of 0.6 V,
The comparison result is converted into a CMOS logic level "H" and output from the output terminal Out.

After that, when the CMOS logic circuit in the IC 40 again supplies the CMOS-level "L" input signal IN to the input terminal In, the NMOS 42-1 is turned off and the NMOS 43-1 is operated by the same operation as described above. Turns on. Therefore, 0.2 V is output to the off-chip output terminal of the IC 40, which propagates through the transmission line 20,
It is input to the off-chip input terminal 62 of the IC 60. IC
In the receiving circuit 60, the differential amplifier 61 compares the reference potential set to 0,6 V with the potential of the transmission line 20, which is 0.2 V, and converts the comparison result into a CMOS logic level “L”. Output from the output terminal Out. As described above, in the present embodiment, the resistors 21 to 24 are connected to both ends of the transmission line 20, and the transmission line 20 is in a state of being terminated with an impedance equal to the characteristic impedance. That is, since impedance matching is performed, a waveform with less distortion can be transmitted with respect to the propagation signal on the transmission line 20. Therefore, CMOS level or TTL
High-speed and low-noise signal transmission is possible compared to level signal transmission. Further, as in FIG. 2, since the signal amplitude propagating through the transmission line is as small as 0.8 V, the CMOS
High-speed signal transmission is possible as compared with signal transmission at the level or TTL level. Further, the signal transmission circuit of the present embodiment has the following effects (1), (2) and (3).

(1) Improvement of switching noise In the signal transmission circuit of FIG. 1, noise (switching noise) generated when the transmission signal is switched between "H" level and "L" level is the signal transmission circuit of FIG. Has been improved compared to. This is because the configuration of the transmission circuit in the IC 40 and the termination method of the transmission line 20 are different from those in FIG. 2, and it is realized by reducing the current flowing to the ground potential GND of the IC 40. That is, in the conventional circuit of FIG.
The output current when the terminal potential Vt = 1.2V, the amplitude of the transmission signal is 0.8V, and the transmission signal is “L” is 32 mA, whereas in the present embodiment, when the transmission signal is “L”. Output current is 16 mA. If the output current is small, the change amount (di / dt) of the output current at the time of switching between the “H” level and the “L” level of the transmission signal becomes small. Therefore, the switching noise generated by the inductance is improved.

(2) Improvement of "H" level amplitude FIG. 7 is a diagram showing a model of the signal transmission circuit of FIG.
8 (i) to (v) are waveform diagrams of the transmission signal in the transmission line in FIG. The length of the transmission line 1 in FIG. 7 is 4
It is set to 0 cm. The transmission circuit ₁ has a transmission circuit 5 ₁
IC 5 ₁ and the transmitting side with -2, the receiving circuit 7 ₁ -
Receiving side I provided with 3, 7 ₂ -3, ..., 7 ₈ -3 respectively
C7 ₁ , 7 ₂ , ..., 7 ₈ are connected at 2 cm intervals.
In FIG. 7, each IC 5 ₁ , 7 ₁ , 7 ₂ , ..., 7 ₈
And the capacitances 8 ₀ , 8 ₁ connected between the
, 8 ₈ are shown to model the load capacitance parasitic on the off-chip terminals of the IC.
The capacitance value of the electrostatic capacitance 8 ₀ , 8 ₁ , ..., 8 _{8 is 1} pF to 1
It is generally known that the size is about 0 pF. Termination potential Vt = 1.2V, characteristic impedance Z ₀ = 50Ω of the transmission line 1, propagation delay time Td per 1 m of the transmission line T = 6.7 nsec / m, and resistors 2 and 3
The signal waveforms at points A, B, C, and D on the transmission line 1 were evaluated by simulation under the condition that the resistance values of the above were 50Ω. With respect to the waveform of the input signal IN shown in (i) of FIG. 8, the signal waveform at each point A, B, C, D is
It becomes like (ii)-(v) of FIG. In addition, the waveform shown by a shows the capacitance value of each electrostatic capacitance 8 ₀ , 8 ₁ , ..., 8 ₈ by 5
It is a waveform when pF is set, and b is a waveform when 0 pF is set.

When the capacitance value of each electrostatic capacitance 8 ₀ , 8 ₁ , ..., 8 ₈ is ₀ pF, the signal waveform at each point A, B, C, D has an "H" level of 1.2 V, The L ″ level becomes about 0.3 V, and the signal amplitude as designed can be obtained. On the other hand, when the capacitance value of each electrostatic capacitance 8 ₀ , 8 ₁ , ..., 8 ₈ is set to 5 pF, “H” is set at each point of A, B, C, and D.
It can be confirmed that the level signal amplitude increases stepwise. For example, when the signal waveform is switched from the “L” level to the “H” level at the point B, the potential rises only up to about 0.95 V for about 2 nsec. Normally, the reference potential used in the receiving circuit is 0.8 V, and the amplitude of the "H" level is only about 38%. In this state, the input voltage margin of the receiving circuit is small and it is difficult to guarantee the circuit operation. Further, depending on the condition of the load capacitance, the "H" level of 0.8 V or higher may not be obtained, and the binary signal cannot be transmitted. This is because the connection of 5 pF of each load capacitance reduces the effective characteristic impedance of the transmission line 1 to 50Ω or less, and the transmission line 1 cannot be impedance matched. Under this simulation condition, the effective characteristic impedance is about 29.5Ω, and the reflection coefficient Γ at the end of the transmission line 1 is about 0.26.

FIG. 9 is a diagram showing a model of the signal transmission circuit of FIG. 1, and FIGS. 10 (i) to 10 (v) are waveform diagrams of transmission signals in the transmission line in FIG. The length of the transmission line 20 in FIG. 9 is also set to 40 cm. Transmission line 20
The, IC 40 of the transmission side with a transmission circuit 40 ₁ -1 ₁
If each reception circuit 61 _1, 61 _2, ..., recipient IC60 with 61 _8, respectively _1, 60 _2, ..., 60 ₈ 2cm
Connected at intervals. In FIG. 9, each IC 40 ₁ , 6
Capacitors 9 ₀ , 9 ₁ , ..., 9 ₈ connected between 0 ₁ , 60 ₂ , ..., 60 ₈ and the ground localization GND are also shown. Here, as in FIG. 7, the termination potential Vt = 1.2 V, the characteristic impedance Z ₀ = 50Ω of the transmission line 20, and the delay time Td per 1 m of the transmission line 20 = 6.7 nsec / m.
And the resistance value of each of the terminating resistors 21 to 24 was set to a condition of 100Ω, and the signal waveforms at points A, B, C and D on the transmission line 20 were evaluated by simulation.

10I shows the waveform of the input signal IN, and the signal waveforms at points A, B, C and D are shown in FIG.
It becomes like (ii) ~ (v). In addition, the waveform shown by a shows the capacitance value of each electrostatic capacitance 9 ₀ , 9 ₁ , ..., 9 ₈ by 5 pF.
And the waveform b is 0 pF. The capacitance value of each electrostatic capacitance 9 ₀ , 9 ₁ , ..., 9 ₈ is set to 0.
When pF is set, the transmission waveform at each point A, B, C, D has an "H" level of 1.0 V and an "L" level of about 0.1 V, and both of them have the designed signal amplitude. In contrast, each of the electrostatic capacitance _{9 0, 9 1, ...,} 9 8 5p capacitance value of
It can be confirmed in FIG. 10 that the signal amplitude at the “H” level increases stepwise at points A, B, C, and D when F is set. However, the signal amplitude at the “H” level is improved as compared with the respective transmission waveforms in FIG.
I can confirm. For example, in the waveform at the point B, the potential rises to about 0.9 V for about 2 nsec after the level is switched from "L" to "H". Since 0.6 V is used as the reference potential of the receiving circuit in the case of the present embodiment,
The amplitude of the "H" level is about 75%. That is, the input voltage margin of the receiving circuit is improved. The improvement of the input voltage margin for the "H" level signal of the receiving circuit is
The output impedance of the transmission circuit in the present invention is
Approximately 1 for both "H" level output and "L" level output
It is realized because it is set to 0Ω. That is,
In the present embodiment, the first and second on-chip termination resistance means 4
Since 2 and 43 are provided, compared to the conventional circuit,
The impedance matching at the connection point of the transmission circuit at the time of "H" level output is improved.

In the transmitting circuit 51-2 used in FIG.
The output impedance at “L” level output is about 8Ω and the reflection coefficient Γ is about 0.56, and the output impedance at “H” level output is 1.0 (total reflection) in the open state. . Therefore, while switching from "H" level to "L" level, sufficient amplitude can be obtained.
When switching from the "L" level to the "H" level, the amplitude was extremely short, resulting in the shortage of the input margin in the receiving circuit. In the transmission circuit 40 ₁ -1 used in FIG. 9, the output impedance is "H" when the level output is also "L" level when the output is also any output impedance is equal to approximately 8ohms. Therefore, when switching from "H" level to "L" level and from "L" level to
The signal waveform shows the same behavior when switching to the “H” level. Therefore, as shown in FIG. 8 of the conventional example, the signal amplitude does not become extremely insufficient only at the “H” level.
Around the reference potential of 0.6 V, the same amplitude can be obtained for both the "H" level and the "L" level.

(3) Improvement of Duty Stability As shown in (ii) to (v) of FIG. 8, in the conventional circuit, the waveforms of the rising and falling edges of the transmission signal are unbalanced during impedance mismatch. That is, the rising time and the falling time of the signal are different, and the rising time of the received signal becomes longer than the falling time. Therefore, in the conventional signal transmission circuit of FIG.
Even if good duty is obtained when impedance matching is performed, duty variation occurs when impedance matching is not performed. Due to this duty failure,
In the worst case, the circuit operation may be hindered.
In this case, the size of the load capacitance connected to the transmission line 20 and the length of the transmission line 1 are affected. In this embodiment, since the output impedance of the transmission circuit at the time of “H” level output and at the time of “L” level output are equal, the rising and falling waveforms of the transmission signal are (ii) to (v) in FIG.
Shows the same behavior. That is, for example, even when impedance mismatches, the rising waveform and the falling waveform are symmetrical and the rising time and the falling time are equal. Therefore, the stability of the duty is improved.

Second Embodiment FIG. 11 is a circuit diagram of a transmission circuit showing a second embodiment of the present invention. In the signal transmission circuit of this embodiment, the structure of the transmission circuit in the transmission side IC 40 in the first embodiment of FIG. 1, that is, the structure of the transmission circuit shown in FIG. 5 is changed to FIG. The transmission circuit in FIG. 11 includes a resistance element control means 41 having the same configuration as that in FIG. The first and second on-chip termination resistance means 44, 4 are provided on the output side of the resistance element control means 41.
5 is connected. The first and second on-chip termination resistance means 44, 45 have the same functions as the on-chip termination resistance means 42, 43 in the first embodiment,
The structure is different. That is, the on-chip termination resistance means 4
4 is the first MO whose drain is connected to the termination potential Vt.
NMOS 44-1 which is an S transistor and its NMO
The resistor 44-2 which is the first resistor element connected in series between the source of S44-1 and the output terminal is provided. NMO
The AN in the resistance element control means 41 is connected to the gate of S44-1.
The output of the D gate 41-2 is connected. On the other hand, the on-chip termination resistance means 45 is an NMOS 45-1 which is a second MOS transistor whose source is connected to the ground potential.
And a resistor 45-2 which is a second resistance element connected in series between the drain of the NMOS 45-1 and the output terminal. The output of the NOR gate 41-3 in the resistance element control means 41 is connected to the gate of the NMOS 45-1.

As described in the first embodiment, it is necessary to set the first and second on-chip termination resistance means 42 and 43 to be 12.5Ω when in the ON state. However, in recent miniaturization technology, each NMOS 42-1 and
It is difficult to manufacture the gate length of 43-1 with an accurate and stable value, and the ON resistances of those NMOSs 42-1 and 43-1 may vary. In the transmission circuit having the structure of FIG. 11, the combined resistance of the ON resistance of the NMOS 44-1 and the resistance value of the resistance 44-2, and the combined resistance of the ON resistance of the NMOS 45-1 and the resistance value of the resistance 45-2 are 12 respectively. .5
Set to Ω. For example, NMOS 44-1 and 45-1
The on resistance value of each resistor is designed to be sufficiently low, and each resistor 44-2, 4
5-2 is composed of a diffusion resistance. This allows the NMOS4
Even if the on-resistances of the finished products 4-1 and 45-1 vary, the first and second on-chip termination resistance means 4 are provided.
The fluctuations in the resistance values of the on-states of Nos. 4 and 45 are small. The signal transmission circuit using the transmission circuit of FIG. 11 also operates similarly to the signal transmission circuit of the first embodiment. As described above, in this embodiment, the first and second on-chip termination resistance means 44, 45 are connected to the NMOSs 44-1 and 45, respectively.
-1 and resistors 44-2 and 45-2 in series with it, respectively, so that the effect (1) described in the first embodiment can be obtained.
(2) and (3) can be ensured.

Third Embodiment FIG. 12 is a circuit diagram of a signal transmission circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. Transmission line 2 in the first and second embodiments
0 uses the termination resistors 21 to 24 and is connected to the termination potential Vt and the ground potential GND on the printed circuit board. In the signal transmission circuit of the third embodiment, the terminating resistors 21 to 2
Third and fourth resistance elements 21a to 24a corresponding to 4 are formed in the IC. A plurality of ICs 70 to 100 including a transmission circuit, a reception circuit, or a transmission / reception circuit are connected to the transmission line 20 of the signal transmission circuit of FIG. For example, the IC 70 is an IC on the transmission side, and includes the same transmission circuit as the IC 40 in FIG. Also, IC1
00 is an IC on the receiving side, and has a receiving circuit similar to the IC 60. The IC 70 further includes a third resistance element 21a connected between the off-chip output terminal and the termination potential Vt, an off-chip output terminal and the ground potential GN.
A fourth resistance element 23a connected between D is provided. The IC 100 is provided with a third resistance element 22a connected between the off-chip input terminal and the termination potential Vt and a fourth resistance element 24a connected between the off-chip input terminal and the ground potential GND. There is.

The resistance elements 21a to 24a are constituent elements such as a MOS transistor having a predetermined ON resistance (100Ω) or a diffusion resistance, and can be formed in the IC. These are the terminating resistors 21 to 21 in FIG.
It works almost the same as 24. As described above, in this embodiment, the terminating resistors 21 to 2 in the first and second embodiments are used.
Resistor elements 21a to 24a corresponding to No. 4 are formed in the IC. Therefore, for example, the resistance component of the terminating resistor mounted on the printed board can be eliminated, and the mounting efficiency of the printed board is improved. Moreover, since the number of resistance components can be reduced, the cost can be reduced. The present invention is not limited to the above embodiment, and various modifications can be made.
The following are examples of such modifications.

(I) In the first to third embodiments, the CMO
An example of signal transmission between ICs by S technology is shown, but B
Signal transmission between ICs to which iCMOS technology is applied is also possible. (II) Both of the circuits shown in FIGS. 1 and 12 are bus-type signal transmission circuits in which both ends of the transmission line 20 are connected to the termination potential Vt.
It is also possible to transmit to multipoint. FIG. 13 is a circuit diagram showing a modified example of the signal transmission circuit,
The case of a signal transmission circuit of the point to multipoint format is shown. In FIG. 13, the transmission circuit 1 is provided at one end of the transmission line 120.
The IC 130 on the transmission side including 31 is connected, and the other end of the transmission line 120 is connected to the termination potential Vt. Receiving side ICs 140 to 160 are connected to the transmission line 120. Each of the ICs 140 to 160 has a receiving circuit 141 to 1
It has 61. Only from IC130, IC140 ~
The signal is transmitted to 160.

(III) The "H" level, "L" level and reference potential of the signal transmitted via the transmission line 20 can be set according to the application. For example, in the signal transmission circuit of FIG. 1, by changing the termination potential Vt and the impedance of the on-chip termination resistance means 42 and 43,
"H" level, "L" level, and reference potential can be set. Assuming that the termination potential Vt = 1.2V and the impedance of the on-chip termination resistance means 42 and 43 is 12.5Ω, the “H” level is 1.0V centering on the reference potential of 0.6V,
A signal having an "L" level of 0.2 V can be transmitted. Similarly, if the termination potential Vt = 1.0V and the impedance of the on-chip termination resistance means 42 and 43 is 6.25Ω, the “H” level is 0.9V and the “L” level is centered on the reference potential of 0.5V. Can transmit a signal of 0.1V. (IV) In the first embodiment, the NMOSs 42-1 and 43-1 are used as the first and second on-chip termination resistance means 42 and 43, but they can be changed to PMOS.
Similarly, in the second embodiment as well, the first and second on-chip termination resistance means 42, 43 have NMOSs 44-1 and 45-1.
However, it is possible to use a PMOS.

[0030]

As described above in detail, the first to the fourth
According to the invention, it is provided with first and second terminating resistors that terminate one end or both ends of the transmission line to a terminating potential and a ground potential, and turn on and off based on the level of the input signal in the transmission circuit, and the on state thereof. At this time, there are provided first and second on-chip termination resistance means for connecting the transmission line and the termination potential or the ground potential to form an on-chip termination resistance of the transmission line. Therefore, when switching the signal level transmitted by the transmission circuit between the “H” level and the “L” level, the amount of current flowing to the ground potential can be reduced and the switching noise is reduced. Further, when transmitting a signal of either the "H" level or the "L" level, impedance matching of the transmission line is ensured, and the "H" level amplitude of the transmission signal can be sufficiently ensured. Further, the duty of the transmission signal is stable.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a signal transmission circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional signal transmission circuit.

FIG. 3 is a diagram showing a configuration of a simulation circuit for the signal transmission circuit of FIG.

FIG. 4 is a waveform diagram showing a simulation result according to FIG.

5 is a circuit diagram showing a configuration of a transmission circuit in FIG.

6 is a circuit diagram showing a receiving circuit in FIG.

FIG. 7 is a diagram showing a model of the signal transmission circuit of FIG.

FIG. 8 is a waveform diagram of a transmission signal in the transmission line in FIG.

9 is a diagram showing a model of the signal transmission circuit of FIG. 1. FIG.

10 is a waveform diagram of a transmission signal in the transmission line in FIG.

FIG. 11 is a circuit diagram of a transmission circuit showing a second embodiment of the present invention.

FIG. 12 is a circuit diagram of a signal transmission circuit showing a third embodiment of the present invention.

FIG. 13 is a circuit diagram showing a modification of the signal transmission circuit.

[Explanation of symbols]

20 Transmission Lines 21-24 First and Second Termination Resistors 21a-24a Third and Fourth Resistance Elements 30-100 ICs 42,43,44,45 On-Chip Termination Resistance Means 42-1,43-1,44 -1,45-1 NMOS 44-2,45-2 First and second resistance elements

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication H01L 21/822 H03K 17/16 H 9184-5K 19/003 Z

Claims (4)

[Claims] 1. A transmission circuit in a semiconductor integrated circuit on a transmission side, a reception circuit in a semiconductor integrated circuit on a reception side, and a termination lower than a power supply potential supplied to the semiconductor integrated circuits on the transmission side and the reception side. A transmission line terminated to a potential via a terminating resistor, from the semiconductor integrated circuit on the transmission side to the semiconductor integrated circuit on the reception side via the transmission line,
2 with amplitude smaller than the voltage between the terminal potential and the ground potential
In a signal transmission circuit for transmitting a value signal, one end or both ends of the transmission line are terminated to the termination potential via a first termination resistor, and via a second termination resistor different from the first termination resistor. And a configuration in which the terminal potential is supplied to the semiconductor integrated circuit on the transmission side, the transmission circuit turns on and off based on the level of an input signal in the transmission circuit, First on-chip termination resistance means for connecting the transmission line and the termination potential supplied to the semiconductor integrated circuit with a predetermined impedance to form an on-chip termination resistance of the transmission line in the ON state. And the first on-chip terminating resistance means are turned on and off complementarily, and when in the on state, the transmission line and the ground potential are connected by a predetermined impedance and the transmission is performed. Signal transmission circuit is characterized in that a second on-chip termination resistor means forming the on-chip termination resistors of the line. 2. The MO of each of the first and second on-chip resistance means is set so that the impedance in the ON state becomes the predetermined impedance.
The signal transmission circuit according to claim 1, wherein the signal transmission circuit is an S transistor. 3. The first and second on-chip termination resistance means include first and second MOS transistors that are turned on and off complementarily according to the level of the input signal, and the first and second transistors. And a first resistance element and a second resistance element connected in series, respectively, the ON resistance of the first MOS transistor, the combined resistance of the first resistance element, the ON resistance of the second MOS transistor, and the The signal transmission circuit according to claim 1, wherein a combined resistance of the second resistance element is set to each of the predetermined impedances. 4. The first and second terminating resistors are third and fourth resistance elements formed in the transmitting side semiconductor integrated circuit or the receiving side semiconductor integrated circuit. The signal transmission circuit according to Item 1, 2 or 3.