JPH08204017A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE: To make production processes during diffusion, etc., to be simplified and reduce the on-state resistance in a vertical element part sufficiently by forming the sub substrate side of the vertical element of high impurity concentration area and forming an isolation around a small signal element formed of epitaxial layer. CONSTITUTION: A semiconductor substrate 10 is comprised of a first conductive sub-substrate 11 with high impurity concentration and a first conductive epitaxial layer with low impurity concentration formed on the substrate 11. The epitaxial layer is formed of at least two layers, first layer 12 and second layer 15, and the first layer 12 on the substrate 11 side for a vertical element 30 for large electric power is formed of first conductive area 13 with high impurity concentration. In addition, a second conductive isolation 16 is formed around a control circuit part 20 made of small signal elements for controlling the epitaxial layer. Thus, the impurity concentration on the substrate 10 side of the element part 30 can be sufficiently made high in a short time, the on-state resistance be reduced sufficiently, and an element for large electric power with high performance be also obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. More specifically, the present invention relates to a semiconductor device, which is a so-called intelligent power device, in which a vertical element for high power such as a vertical MOSFET and a small signal element for control are formed on the same substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Double diffusion MOSFET
A control circuit including a logic element, a small signal element for control, a resistor, a capacitor, etc. in order to reset a vertical element for high power such as (hereinafter referred to as D-MOS) or to protect it from overcurrent, overvoltage, overheat, etc. A so-called intelligent power device (hereinafter referred to as an IPD), which is integrated with a vertical element for high power on the same chip, is used for a high side switch, a low side switch, a motor drive, and the like.

For example, as shown in FIGS. 4 to 5 in perspective views and sectional explanatory views, this IPD is a vertical type for high power, which is composed of a control circuit section 20 and a D-MOS, for example, on a one-chip semiconductor substrate 10. The element portion 30 is formed and configured. Since the control circuit section 20 is electrically insulated from the vertical element section 30, the control circuit is formed by a logic element, a control small signal element, a resistor, a capacitor, etc. in the small signal element formation region separated by the isolation 16. Has been formed. In FIG. 5, only one npn transistor 21 is shown. A buried layer 24 for reducing collector resistance is formed below the transistor 21.

A bipolar power transistor, a power MOSFET, or the like is formed in the vertical element portion 30 and a large current can be obtained. Therefore, the element is formed so that the current flows in the vertical direction which is the vertical direction of the substrate 10. In FIG. 5, D-MOS
Of the source region 3 on the front surface side of the substrate 10.
The 1 and p-type regions 32 and the channel region 33 at the end thereof are formed, the epitaxial layer 14 of the substrate 10 is used as a drain region, and the channel region 33 is turned on by a signal applied to a gate electrode (not shown) on the channel region 33. Therefore, a current flows between the source electrode 35 (see FIG. 4) and the drain electrode 36 (see FIG. 4) on the back surface side of the substrate 10. A large number of FET cells composed of the source region 31 and the channel region 33 are formed in the vertical element portion 30, each electrode is connected in parallel, and the gate electrode 37 (see FIG. 4) is connected to the control circuit portion 20. There is. The sum of the currents flowing through the cells flows as the D-MOS current.

[0005] substrate 10, p the control circuit section 20 described above for vertical element 30 must form isolation 16 for electrically isolating the, for example, on the n ⁺ -type sub-board 11 ^- A type epitaxial layer 42 is grown to form the bottom of the isolation 16. Further, as described above, the vertical element portion 30 needs to pass a current in the vertical direction of the substrate 10. If a p ⁻ -type layer is present on the n ⁺ -type sub-substrate 11, no current will flow, so that n-type impurities are removed. Introduce n ⁺
The mold area 43 is formed. An n ⁻ -type epitaxial layer 14 forming a control small signal element and a vertical element is grown on it. After that, a p-type impurity is introduced around the control circuit portion 20 to form the side wall portion 16c of the isolation 16 so that the control circuit portion 20 is separated into island regions.

In this type of semiconductor substrate 10 for IPD, since the current of the vertical element section 30 flows vertically through the semiconductor substrate 10, the specific resistance of the drain region (epitaxial layer 14) is desired D. It is necessary to maintain the value necessary for obtaining the -MOS characteristics and to sufficiently increase the impurity concentration of the n ⁺ type region 43 to reduce the on-resistance. On the other hand, if the breakdown voltage of the pn junction accompanying the isolation 16 of the control circuit unit 20 is lowered, the breakdown voltage as IPD is lowered and the electrical characteristics are lowered. Therefore, the thickness of the p ⁻ -type epitaxial layer 42 is, for example, 30 μm. It must be thick enough as above. Therefore, in the vertical element portion 30, it is necessary to introduce an n-type impurity into the p ⁻ -type epitaxial layer 42 having a considerable thickness to change it into the n ⁺ -type region 43. However, if an impurity material having a large diffusion coefficient is introduced, the impurity is introduced into the drain region. When the impurity material having a small diffusion coefficient cannot be controlled so that the p ^- type epitaxial layer 42 can be completely n ⁺ -type, a high temperature of about 1200 ° C. for a period of 20 hours or more is required. Requires heat treatment for hours.

The vertical type element portion 30 of the semiconductor substrate of this IPD
In order to reduce the on-resistance by lowering the n ⁺ -type region 43 of the above, the p ⁻ -type epitaxial layer 42 is formed of two layers or three layers in the thin state of each layer in JP-A-2-69974. Introducing an n-type impurity so as to form the n ⁺ -type region 43 over the entire thickness of the thick p ⁻ -type epitaxial layer 42, or p ^{− in} JP-A-64-8672.
By providing a recess in the vertical element portion of the epitaxial layer 42 to make it thinner, and by providing in the recess a diffusion layer of the same conductivity type as the sub-substrate having a large diffusion coefficient so as to reach the sub-substrate.
A method of forming a ⁺ type region is disclosed, but in any case, it is formed by growing a p ⁻ type epitaxial layer on an n ⁺ type sub-substrate.

[0008]

As the semiconductor substrate for INVENTION Problems to be Solved conventional IPD, as described above, p on n ⁺ -type sub-substrate ^- is grown -type epitaxial layer, the vertical element unit that p ^- n and n-type impurity is introduced into the type epitaxial layer ⁺
It is a type. Therefore, the p ⁻ -type epitaxial layer is divided into many layers, and n-type impurities are diffused in each thin layer.
It is necessary to form a recess in the p ⁻ -type epitaxial layer of the vertical device portion by etching to make the p ⁻ -type layer thin and then form the n ⁺ -type region, which requires a large number of manufacturing steps and increases the cost. There is.

Further, by introducing an n-type impurity into the p ^-- type layer, n
^{Since it is a +} type, it is necessary to invert the conductivity type to obtain a high impurity concentration, it is necessary to increase the amount of impurities to be introduced, a long diffusion time is required, and the entire thickness is perfect. A high impurity concentration cannot be achieved and the on-resistance cannot be reduced. Further, since it is necessary to change the conductivity type to increase the concentration, there is a problem in that lattice defects of the crystal lattice are likely to occur and the on-resistance cannot be sufficiently reduced.

The present invention solves such problems, shortens the manufacturing time such as the diffusion step, sufficiently reduces the on-resistance of the vertical element portion, and provides a semiconductor device having excellent IPD element characteristics at low cost. The purpose is to do.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
What is claimed is: 1. A semiconductor device comprising a semiconductor substrate having a high-power vertical element and a control small-signal element monolithically formed, wherein the semiconductor substrate is a first-conductivity-type sub-substrate and a high impurity concentration sub-substrate. And an epitaxial layer of a first conductivity type and a low impurity concentration, the epitaxial layer being composed of at least two layers of a first layer and a second layer. One layer is a first-conductivity-type high-impurity-concentration region, and a second-conductivity-type isolation is formed around the region where the small signal element is formed in the epitaxial layer.

It is preferable that the high impurity concentration region of the first layer is formed of an impurity having a small diffusion coefficient because the impurity concentration of the FET portion does not change.

The epitaxial layer has a third layer between the first layer on the sub-substrate side and the second layer on the front side, and the small signal element forming region is provided in the small signal element forming region of the third layer. It is preferable that the buried layer is formed because the buried layer can be accurately formed without penetrating the isolation when the buried layer is formed.

The manufacturing method of the semiconductor device of the present invention is as follows:
A first conductive type low-impurity concentration epitaxial layer first layer is grown on a conductive type high-impurity concentration sub-substrate, and (b) a portion of the first layer corresponding to a formation region of a high-power vertical element. To a high impurity concentration region by introducing the first conductivity type impurity, and by introducing the second conductivity type impurity into the surface layer portion of the portion corresponding to the formation region of the control small signal element in the first layer. And (c) growing a second layer of a first conductivity type and low impurity concentration epitaxial layer on the first layer, and (d) forming a region of the small signal element in the second layer. A second conductivity type impurity is introduced into the periphery of the isolation region to form a side wall portion of the isolation and is connected to the lower bottom portion of the isolation to surround the small signal element forming region with the second conductivity type isolation, (E) The A control circuit forming region of the signal element, and forming a high power vertical element to the second layer on the high impurity concentration region of the first layer.

After forming the lower bottom portion of the isolation in the step (b), the second conductivity type impurity for the sidewall lower layer portion of the isolation is introduced into both ends of the lower bottom portion (hereinafter referred to as step (f)). (1) is preferable since the side wall of the isolation can be formed from above and below and can be easily formed.

After step (b) or step (f), a third layer of the first conductivity type, low impurity concentration epitaxial layer is formed, and the third layer is formed on the lower bottom portion of the isolation.
By introducing an impurity into the surface of the layer and forming a buried layer having a high impurity concentration of the first conductivity type, the buried layer can be accurately formed.

[0017]

According to the semiconductor device of the present invention, since the epitaxial layers of the semiconductor substrate on which the IPD is formed are all of the same conductivity type as the sub-substrate, the impurity concentration on the substrate side of the vertical element portion is sufficiently increased in a short time. The concentration can be adjusted to minimize crystal defects. . As a result, the on-resistance can be sufficiently reduced, and a high-performance high-power device can be obtained.

Further, since the control circuit portion is electrically isolated by isolation and the isolation region can be formed by impurities having a large diffusion coefficient, it can be formed to a sufficient thickness in a short time, and the breakdown voltage of the pn junction is also high. It can be kept high enough.

According to the method of manufacturing a semiconductor device of the present invention, a control small signal element formation region is electrically connected to a large power vertical element portion while an epitaxial layer having the same conductivity type as that of the sub substrate is grown on the sub substrate. In order to form a high impurity concentration region, an impurity of the same conductivity type as that of the epitaxial layer may be introduced to form a high impurity concentration region, and a high impurity concentration region with few crystal defects can be formed in a short time. be able to.

As a result, it is possible to sufficiently reduce the on-resistance of the high power vertical element while sufficiently maintaining the breakdown voltage between elements, and to obtain an IPD with high characteristics and high reliability.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device of the present invention and a manufacturing method thereof will be described with reference to the drawings.

FIG. 1 is a sectional explanatory view of a semiconductor device of the present invention.
2 to 3 are cross-sectional explanatory views of the manufacturing process.

In the semiconductor device of the present invention, a semiconductor substrate 10 is provided with a control circuit portion 20 electrically isolated from each other by an isolation 16 and a large power vertical element portion 30 composed of a D-MOS or the like. Then, the semiconductor substrate 10
The present invention is characterized in that all the epitaxial layers 12, 14, and 15 are formed with the same conductivity type as the sub-substrate 11.

The semiconductor substrate 10 has a first conductivity type, for example, an n ⁺ type sub-substrate 11 and a first layer (1EP) of an n ⁻ type epitaxial layer having a low impurity concentration first conductivity type.
I) 12 is epitaxially grown. An n-type impurity having a small diffusion coefficient such as antimony and arsenic is introduced into the high-power vertical element portion 30 of the first layer 12 to form an n ⁺ -type high impurity concentration region 13. Further thereon, a third layer (3EPI) 14, which is an n ⁻ type epitaxial layer,
The second layer (2EPI) 15 is sequentially epitaxially grown. Around the control circuit portion 20 of the epitaxial layers 12, 14 and 15 to electrically separate the control circuit portion 20 from the high power vertical element portion 30, a second conductivity type region such as ap ⁺ type region is formed. Is formed by connecting the lower bottom portion 16a, the side wall lower layer portion 16b, and the side wall portion 16c. As a result, in the control circuit unit 20, a part of the epitaxial layers 12, 14, 15 are separated into islands, and as described above, the large power vertical devices are protected from overcurrent, overvoltage, overheat, and the like. A control circuit including a control small signal element for resetting or resetting, a logic element, a resistor, a capacitor, and the like is formed.

The withstand voltage of this type of semiconductor device is regulated by the withstand voltage between the source and drain of the FET when a D-MOS is used for a high power vertical element, for example, but the pn junction formed by the isolation 16 is used. It is also regulated by the pressure resistance of. Therefore, if the breakdown voltage of the pn junction of the isolation 16 is small, the semiconductor device itself becomes defective. However, in the present invention, since the isolation 16 is formed with a high concentration of impurities, the width of the void layer formed in the pn junction can be formed on the n ⁻ type epitaxial layer side around the isolation, and the withstand voltage can be increased. Can be high enough. On the other hand, since the first layer 12 of the epitaxial layer is formed to have the same conductivity type as that of the sub-substrate 11, when the high impurity concentration region 13 for reducing the on-resistance is formed in the high power vertical element portion, It suffices to diffuse n-type impurities, which have the same conductivity type as the epitaxial layer, to obtain sufficient n ⁺
It can be a mold area. As a result, the generation of crystal defects can be suppressed, and the on-resistance can be further reduced.

Impurities introduced to form the high impurity concentration region 13 have a diffusion coefficient of not so much as to diffuse into the second layer 15 of the epitaxial layer in order to maintain constant the device characteristics of the high power vertical device. It is preferable to use small impurities. In the case of n-type, antimony or arsenic can be used as the impurity having a small diffusion coefficient. Even if the diffusion coefficient is small, the first layer 12 that diffuses the impurities has the same conductivity type, and thus can have a high impurity concentration with few crystal defects.

The third layer 14 of the epitaxial layer described above is
This is provided in order to prevent the lower bottom portion 16a of the isolation 16 from being eroded when the buried layer 24 for reducing the collector resistance of the transistor of the control small signal element is formed. So that the buried layer 2
4 is preferable because it can be formed without considering the interaction with the lower bottom portion 16a of the isolation 16. However, if the buried layer 24 is not provided, the lower bottom portion 16a of the isolation 16 is made sufficiently thick and the lower bottom portion 16a
If the n-type impurity is introduced into the surface side of a and controlled so that the n-type impurity is diffused in the second layer 15 epitaxially grown thereon, the third layer 14 may be omitted. Good.

Further, the side wall lower layer portion 16b of the isolation 16 is formed by forming the lower bottom portion 16a of the isolation 16 and then p ⁺ -type impurities are further introduced around the lower portion 16a to grow an epitaxial layer thereon. After being diffused by autodoping, p ⁺
Side wall portion 16 of the isolation 16 by diffusing type impurities
When forming c, the isolation 16 can be easily formed by joining with the sidewall lower layer portion 16b without completely diffusing to the lower bottom portion 16a.
Therefore, only the diffusion from the surface of the second layer 15 causes the sidewall 1
When forming 6c, the sidewall lower layer portion 16b is not necessary, but it is preferable to provide the sidewall lower layer portion 16b because the isolation 16 can be formed easily.

As described above, the control circuit section 20 is provided with a logic element, a small signal element for control, a resistor, etc., and is provided with a circuit for protecting the vertical element for high power from overcurrent or overvoltage or a circuit for resetting. It is formed. This is formed by a normal IC manufacturing process. FIG. 1 shows only the transistor 21 in which the emitter region 22, the collector contact region 25, and the base region 23 of the small signal transistor are formed.

In the high power vertical element portion 30, elements such as a bipolar transistor and a power MOSFET through which a current flows from the front surface side to the back surface (sub substrate side) of the semiconductor substrate 10 are formed. Although FIG. 1 shows a diagram in which two D-MOS FET cells are formed, a large number of these cells are formed in parallel according to the required current. For example, about 1000 to 1500 pieces are provided to obtain a current of 1 A, and about 5000 to 6000 pieces are provided to obtain a current of 5 A. In FIG. 1, 31 is an n ⁺ type source region and 32 is p
In the mold region, the narrow surface side of the end is the channel region 33 and the second layer 15 is the drain region, and the drain electrode (not shown) is provided on the back surface side of the sub-substrate 11. A gate electrode (not shown) is provided on the surface of the semiconductor substrate 10 provided with the channel region 33 via an insulating film, and is turned on / off according to a control signal from the control circuit unit 20.

Next, a method of manufacturing the semiconductor device of the present invention will be specifically described.

First, as shown in FIG. 2 (a), an n ⁺ type of silicon or the like having a high impurity concentration of, for example, about 10 ¹⁸ to 10 ¹⁹ atms / cm ³ and a thickness of about 550 to 650 μm. A first layer 12 of an n ⁻ type epitaxial layer having an impurity concentration of, for example, about 10 ¹⁴ to 10 ¹⁶ atms / cm ³ is epitaxially grown on the sub-substrate 11 to a thickness of about 25 to 30 μm. Epitaxial growth of silicon or the like is performed in the same manner as that used for manufacturing a normal semiconductor device.

Next, as shown in FIG. 2B, impurities with a small diffusion coefficient, such as antimony or arsenic, are introduced into the vertical element portion for high power of the first layer 12 by ion implantation to 1200 to 1230 ° C. A heat treatment is performed for about 18 to 25 hours to diffuse the impurities to form the n ⁺ -type high impurity concentration region 13.

Next, as shown in FIG. 2C, p
Type impurities such as boron are ion-implanted, and 1100-
Heat treatment is performed at about 1150 ° C. for about 2 to 5 hours to form the lower bottom portion 16a of the isolation. Then, Figure 2
As shown in (d), in order to form the sidewall lower layer portion 16b around the lower bottom portion 16a, p-type impurities such as boron are ion-implanted.

Next, as shown in FIG. 3 (e), n
The third layer 14 of the ⁻ type epitaxial layer is formed in the same manner as the first layer.
Epitaxially grow to a thickness of about 5 μm. At this time, the lower bottom portion 16a of the isolation, the high impurity concentration region 1
The impurity of No. 3 diffuses slightly to the third layer 14, but the impurity concentration for the sidewall lower layer portion 16b is the highest and diffuses to above the third layer 14.

Next, as shown in FIG. 3F, the buried layer 24 of the control small signal element portion is formed by introducing impurities such as Sb and As. After that, the n ⁻ -type epitaxial layer is grown again to form the second layer 1 of the epitaxial layer.
5 is provided (see FIG. 3 (g)). At this time, the p-type impurity introduced around the lower bottom portion 16a further diffuses to the second layer 15 to form the sidewall lower layer portion 16b for isolation, and the impurity for the buried layer 24 also exists on the second layer 15 side. A buried layer 24 is formed on the lower bottom portion 16a of the isolation by diffusion.

Next, as shown in FIG. 3 (h), p-type impurities such as boron are introduced into a portion corresponding to the periphery of the lower bottom portion 16a, and the temperature is set to 8 ° C. at 1200 to 1230 ° C.
By performing a heat treatment for about 14 hours to form the isolation side wall portion 16c and connecting it to the lower layer portion 16b,
The isolation 16 including the side wall lower layer portion 16b, the side wall portion 16c, and the lower bottom portion 16a is formed, and the second layer 15 of the control circuit portion is separated and formed in an island shape.

After that, each element of the control circuit section 20 and each element of the vertical type element section for high power are formed by a normal IC manufacturing process, so that a semiconductor device having an IPD as shown in FIG. 1 is formed. Is formed.

Although the n ⁺ -type sub-substrate is used in the above-mentioned embodiment, a p ⁺ -type sub-substrate may be used, in which case the n-type and the p-type may be replaced with each other. In addition, as described above, the third layer of the epitaxial layer does not necessarily have to be provided, and the side wall lower layer portion 16b of the isolation 16 and the buried layer 24 are not essential and can be omitted.

Further, by forming the first layer 12 of the epitaxial layer into a plurality of layers and diffusing the impurities in the respective thin layers, the high impurity concentration region 13 can be formed more reliably. In addition, the high impurity concentration region 13
If the first layer 12 is epitaxially grown after the impurities are previously introduced on the sub-substrate 11 at the formation location of, the reliable high impurity concentration region 13 can be formed more easily.

[0041]

According to the semiconductor device of the present invention, in the IPD having the high power vertical element and the control circuit portion, the lower layer side of the high power vertical element has few crystal defects and has a sufficiently low resistance. Therefore, the on-resistance is small and a large current easily flows. Furthermore, since the isolation is formed in the low impurity concentration layer, a sufficient void region can be obtained, and the breakdown voltage of the pn junction due to the isolation can be kept sufficiently high.
An IPD with high characteristics and high reliability can be obtained.

Further, according to the method of manufacturing a semiconductor device of the present invention, since the epitaxial layers on the sub-substrate are all formed of the same conductivity type as the sub-substrate, the on-resistance of the vertical element portion for high power is reduced. Impurity diffusion for forming a high impurity concentration region for reduction can be easily performed, the manufacturing period can be shortened, and the cost of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional explanatory view of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a manufacturing process of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a diagram showing a manufacturing process of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a perspective explanatory view showing an example of a configuration of a conventional IPD.

FIG. 5 is a cross-sectional explanatory diagram showing an example of the configuration of a conventional IPD.

[Explanation of symbols]

 10 Semiconductor Substrate 11 Sub-Substrate 12 First Layer of Epitaxial Layer 13 High Impurity Concentration Region 14 Third Layer of Epitaxial Layer 15 Second Layer of Epitaxial Layer 16 Isolation 16a Lower Bottom 16b Sidewall Lower Layer 16c Sidewall 20 Control Circuit Section 30 Vertical element for high power

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8249 29/78 H01L 27/06 321 E 9055-4M 29/78 656 B

Claims (6)

[Claims] 1. A semiconductor device in which a vertical element for high power and a small signal element for control are monolithically formed on a semiconductor substrate, wherein the semiconductor substrate is a first conductivity type sub-substrate having a high impurity concentration. And a first-conductivity-type, low-impurity-concentration epitaxial layer provided on the sub-substrate, the epitaxial layer being composed of at least two layers, a first layer and a second layer. Sub-board side first
A semiconductor device in which the layer is a first-conductivity-type high-impurity-concentration region, and a second-conductivity-type isolation is formed around the formation region of the small signal element in the epitaxial layer. 2. The semiconductor device according to claim 1, wherein the high impurity concentration region of the first layer is formed of an impurity having a small diffusion coefficient. 3. The epitaxial layer has a third layer between the first layer on the sub-substrate side and the second layer on the front side,
3. The semiconductor device according to claim 1, wherein a buried layer for the small signal element is formed in the small signal element forming region of the third layer. 4. A first layer of an epitaxial layer of the first conductivity type and a low impurity concentration is grown on a sub-substrate of the first conductivity type and a high impurity concentration, and (b) for high power in the first layer. A portion corresponding to the formation region of the vertical element is made into a high impurity concentration region by introducing the first conductivity type impurity, and a second layer is formed on the surface layer portion of the portion corresponding to the formation region of the control small signal element in the first layer. A lower bottom portion of the isolation is formed by introducing a conductivity type impurity, and (c) a first bottom portion is formed on the first layer.
A second layer of an epitaxial layer having a conductivity type and a low impurity concentration is grown, and (d) a second conductivity type impurity is introduced around a region where the small signal element is formed in the second layer to form a sidewall portion of isolation. And forming a region for forming the small signal element into a second region by connecting to the lower bottom of the isolation.
(E) A control circuit is formed in the formation region of the small signal element, and a large power vertical element is formed in the second layer on the high impurity concentration region of the first layer. And a method for manufacturing a semiconductor device. 5. The step (f) of forming the lower bottom portion of the isolation in the step (b), and then introducing the second conductivity type impurity for the sidewall lower layer portion of the isolation into both ends of the lower bottom portion. A method for manufacturing the semiconductor device described. 6. The third epitaxial layer having the first conductivity type and the low impurity concentration after the step (b) or the step (f).
6. The semiconductor device according to claim 4, wherein a layer is formed, and impurities are introduced into the surface of the third layer above the lower bottom portion of the isolation to form a buried layer having a high impurity concentration of the first conductivity type. Manufacturing method.