JPH0818054A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To materialize a semiconductor device high in performance and reliability by improving the shape of the end of the SOI of an SOI-structure substrate being made by semiconductor substrate lamination method, and preventing the field concentration at the end of a channel. CONSTITUTION:After lamination of semiconductor substrates, the surface of one semiconductor substrate is polished, and then for removing the damage of polishing, a sacrificed oxide film is made and it is removed, whereupon an SOI layer 2 is made being projected from the surface of a silicon oxide film 3a constituting an interelement isolating area. Here, the concentration of electric fields at the end of a channel can be prevented by tapering the shape of the SOI layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an SOI (Se
miconductor On Insulator or Silicon On Insulato
r) The present invention relates to a semiconductor device formed on a structural substrate and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a method of manufacturing an SOI structure substrate by a wafer bonding method, as disclosed in Japanese Patent Application Laid-Open Nos. 1-226166 and 2-5545, an oxide film ( There is a method of forming a single crystal Si layer (SOI) in which the periphery is separated by an insulating film to form a single SOI film with a uniform SOI film thickness. There is an advantage that the SOI layer can be thinned down to about 0.1 μm.

[0003]

However, since the selective polishing has a stronger mechanical action than the conventional polishing method, a polishing damage layer remains on the surface of the formed SOI layer, and reliability is a problem even when a semiconductor element is formed. Occurs. In order to solve such a problem, it is effective to thermally oxidize the polishing damage layer (this oxidation is referred to as sacrificial oxidation) to remove the silicon oxide film.

However, in this sacrificial oxidation, an oxide film grows on the surface of the SOI layer, but almost no oxide film grows in the field portion. If the oxide film on the SOI is removed by normal wet etching, the field oxide film also grows. Since it is etched by the amount, the SOI layer has a protruding structure. For this reason, it is necessary to secure a sufficient thickness of the field oxide film, and the LOCOS (Local Oxidation
of the SOI layer formed by this method, the tips of both ends of the SOI layer formed by this method are sharply pointed, and after the sacrificial oxide film is removed, the SOI end portion is field-oxidized into a projection shape. It is exposed from the surface of the film.
That is, as shown in FIG. 12a, after the field oxide film 3c is formed by the LOCOS method to polish the surface of the SOI layer 2 in which element isolation has been performed, the polishing damage layer is thermally oxidized to silicon oxide as shown in FIG. 12b. Forming membrane 3b, FIG.
The silicon oxide film is removed as described above, but at that time, the SOI end portion is exposed like a protrusion like the portion shown by A in the figure.

From this state, as shown in FIG. 12d, since the gate oxide film (gate insulating film) 6 and the gate electrode 7 are formed, the projection shape at the SOI end portion at the channel end portion causes electric field concentration, so that the gate is formed. There is a problem that the reliability of the oxide film is lowered. The present invention has been made in view of the above problems, and has a structure that improves the shape of the end portion of the single crystal Si layer, prevents electric field concentration at the end portion of the channel, and realizes a semiconductor device with high performance and reliability. And its manufacturing method.

[0006]

In order to achieve the above object, the present invention provides, in the invention as set forth in claim 1, an insulating isolation on a semiconductor substrate with a dielectric layer interposed therebetween. The island-shaped single crystal semiconductor layer is formed,
A semiconductor device having an insulated gate field effect transistor configured by forming a source and a drain on the single crystal semiconductor layer and further forming a gate electrode on the gate and an insulating film. The outermost surface of the layer is formed above the surface of the dielectric layer forming the surrounding element isolation region, and the outermost surface width W of the single crystal semiconductor layer is equal to the element isolation region surface position. W for width W '
It is characterized in that they are formed to have a relationship of ≦ W ′.

According to a second aspect of the present invention, a step of forming a groove having a shape in which the groove width is narrowed upward from the bottom surface to a predetermined height in the semiconductor substrate, and a dielectric is embedded in the groove to form an element. Forming an inter-element isolation region and using the semiconductor substrate as the inter-element isolation region forming substrate, bonding another semiconductor substrate to the inter-element isolation region forming substrate, and separating the inter-element isolation region forming substrate from the back surface. From the above to form the island-shaped single crystal semiconductor layer whose periphery is insulated and separated by the dielectric until the embedded dielectric is exposed, and the surface of the single crystal semiconductor layer exposed on the polished surface is once oxidized. Then, a step of removing the formed oxide film to remove a polishing damage layer on the surface of the single crystal semiconductor layer by the polishing treatment, and an insulated gate field effect transistor on the re-exposed single crystal semiconductor layer. It is characterized by a step of forming a.

The invention according to claim 3 is characterized in that, in the invention according to claim 2, the formation and removal of the oxide film is repeated a plurality of times. In the invention according to claim 4, a step of forming a groove in the semiconductor substrate,
A step of embedding a dielectric in the groove to form an element isolation region and using the semiconductor substrate as an element isolation region forming substrate; and a step of adhering another semiconductor substrate to the element isolation region forming substrate, Polishing the inter-element isolation region forming substrate from the back surface until the embedded dielectric is exposed to form an island-shaped single crystal semiconductor layer whose periphery is insulated and separated by a dielectric; and Forming a protective layer,
Exposing the surface of the single crystal semiconductor layer so that a protective layer remains on the dielectric in the element isolation region, and temporarily oxidizing the surface of the single crystal semiconductor layer in the exposed state,
A step of removing the formed oxide film to remove a polishing damage layer on the surface of the single crystal semiconductor layer by the polishing treatment; and a step of forming an insulated gate field effect transistor on the exposed single crystal semiconductor layer again. It is characterized by that.

According to a fifth aspect of the invention, in the fourth aspect of the invention, the protective layer is made of polycrystalline silicon or amorphous silicon. According to the invention of claim 6, in the invention of claim 5,
The step of exposing the single crystal semiconductor layer so that the polycrystalline silicon or the amorphous silicon is left on the dielectric in the element isolation region includes removing the remaining polycrystalline silicon or the amorphous silicon from the single crystal. It is characterized in that it is tapered from the surface of the crystalline semiconductor layer.

The invention of claim 7 is characterized in that, in the invention of claim 4, the protective layer is a silicon oxide film. In the invention according to claim 8, a step of forming a groove in the semiconductor substrate, and a step of filling the groove with a dielectric to form an element isolation region, and using the semiconductor substrate as an element isolation region forming substrate. And a step of adhering another semiconductor substrate to the inter-element isolation region forming substrate, and polishing the inter-element isolation region forming substrate from the back surface until the embedded dielectric is exposed, and the periphery is insulated by a dielectric. A step of forming an island-shaped single crystal semiconductor layer, a step of forming an oxide film on the surface of the single crystal semiconductor layer, and a step of forming a protective layer on the element isolation region,
A step of removing the oxide film formed on the single crystal semiconductor layer by using the protective layer as a mask to expose the single crystal semiconductor layer, and forming an insulated gate field effect transistor on the exposed single crystal semiconductor layer again. And a step of performing.

According to a ninth aspect of the invention, in the eighth aspect of the invention, the protective layer is a resist film. A tenth aspect of the invention is characterized in that, in the eighth aspect, the protective layer is a silicon nitride film.

[0012]

In the invention described in claim 1,
In an island-shaped single crystal semiconductor layer in which a dielectric layer is provided on a semiconductor substrate and whose periphery is insulated and separated by a dielectric layer, the outermost surface width W of the single crystal semiconductor layer is the inter-element isolation region surface width W ′. However, since the sacrificial oxide film is formed and removed on the surface of the single crystal semiconductor layer after the polishing process during the formation of the semiconductor device, the outermost surface of the single crystal semiconductor layer is , The edge of the single crystal semiconductor layer does not form a projection at an acute angle even if it is formed above the surface of the dielectric layer forming the surrounding element isolation region It is possible to prevent the electric field from being concentrated, and it is possible to solve the problem of the breakdown voltage deterioration of the gate oxide film. As a result, it is possible to realize a semiconductor device having high performance and reliability.

In the invention described in claim 2, there is an effect that the semiconductor device described in claim 1 can be manufactured. In the invention according to claim 3, since the sacrificial oxidation and the removal of the oxide film are performed a plurality of times,
The shape of the end portion of the single crystal semiconductor layer is rounded, and the effect of preventing electric field concentration at the end portion of the channel can be improved.

In the invention described in claims 4 to 7,
Before removing the sacrificial oxide film formed on the surface of the single crystal semiconductor layer, a protective layer is formed on the dielectric in the element isolation region. Therefore, it is necessary to increase the film thickness of the element isolation region by the protective layer formed on the dielectric of the element isolation region and prevent the single crystal semiconductor layer surface from protruding from the dielectric surface of the element isolation region after removing the sacrificial oxide film. Can be prevented. As a result, it is possible to realize a semiconductor device with high performance and high reliability in which electric field concentration at the channel end is prevented.

In particular, when polycrystalline silicon or amorphous silicon is used as the protective layer as described in claim 5, since it is simultaneously oxidized at the time of subsequent sacrificial oxidation, the dielectric of the element isolation region is formed. Can be made thicker, and as described in claim 7, the thickness of the dielectric in the element isolation region can be made thicker even when a silicon oxide film is used.

Further, in the invention described in claim 6,
Since the polycrystalline silicon and the amorphous silicon are tapered from the surface of the single crystal semiconductor layer, the field oxide film and the single crystal formed by oxidizing the polycrystalline silicon and the amorphous silicon during the subsequent sacrificial oxidation. The continuity with the sacrificial oxide film formed on the surface of the semiconductor layer can be improved. This has the effect of being advantageous for flattening the interlayer insulating film.

According to the present invention, the protective layer functioning as a mask is formed on the dielectric in the element isolation region before removing the sacrificial oxide film formed on the surface of the single crystal semiconductor layer. I am trying to do it. Therefore, the protective layer formed on the dielectric in the element isolation region functions as a mask at the time of removing the sacrificial oxide film in a later step, and prevents the dielectric film in the element isolation region from being thinned. As a result, it is possible to prevent the surface of the single crystal semiconductor layer from protruding from the dielectric surface of the element isolation region after removing the sacrificial oxide film, and to provide a semiconductor device with high performance and high reliability that prevents electric field concentration at the channel end. It can be realized.

Since the protective layer functions as a mask when the sacrificial oxide film is subsequently removed, from this point of view, the step of forming an oxide film on the surface of the single crystal semiconductor layer and the isolation of the protective layer between elements are performed. In the step of forming on the region, either one may be performed first.

[0019]

The present invention will be described in detail with reference to the accompanying drawings. 1a and 1b are respectively a plan view of a MOS transistor as an insulated gate field effect transistor according to the present invention and a sectional view taken along the line LL '.

This embodiment is characterized by the fact that in the SOI layer 2 for forming the active layers as the source and drain regions, the outermost surface width W of the SOI layer 2 and the field surface position (field oxide film 3a). Position of the surface)
The width W'of W is equal to or smaller than W '. In addition, the SO of the part embedded from the field surface position
The shape of the I layer 2 does not matter. Further, as the shape of the SOI layer 2, in addition to the shape shown in FIG. 1b, the shape shown in FIGS.

The process of forming the MOS transistor shown in FIG. 1 will be described below with reference to FIGS. First, an element isolation region is formed as shown in FIGS. 3a and 3b. Therefore, as shown in FIG. 3a, for example, a silicon oxide film 3 having a thickness of 400 nm is formed on the single crystal Si substrate 1 having a p-type (100) specific resistance value of 14 to 22 Ω · cm to form an element. Pattern so that it remains in the area. The silicon oxide film 3 is an etching mask layer for forming the element isolation trenches 4 in the Si substrate 1, and may have a film thickness that can maintain the mask function due to its etching rate. It should be noted that the etching mask layer may be a substance having a large etching selection ratio with respect to the Si substrate 1, and there is another material such as a silicon nitride film. Alternatively, polycrystalline Si may be deposited to form a sacrificial layer.

Next, using the silicon oxide film 3 as a mask layer, S
The i-substrate 1 is etched to a depth of 200 nm, for example, to form an element isolation groove 4 (FIG. 3b). At this time, as shown in FIG. 5a, the groove is formed in a reverse taper shape so that the bottom width W1 thereof is larger than the opening width W2. For example, etching gas;
HBr / SF6 / He-O2 = 40/5 / 18sccm, vacuum degree; 100mTo
This shape can be realized by dry etching with rr, RF power: 400 W, magnetic field: 15 Gauss. The etching depth may be determined in consideration of the final film thickness of the SOI layer and the film loss due to some subsequent oxidation processes.

Next, the etching products adhering to the silicon oxide film 3 and the groove 4 are removed by wet etching with dilute hydrofluoric acid or the like, and then C having a thickness of 600 nm, for example.
A VD silicon oxide film 3a is formed on the entire surface and the inter-element isolation trench 4 is buried (FIG. 3c). At this time, since a layer in which the crystal lattice is disturbed exists on the Si etching surface when the element isolation trench 4 is formed, a thermal oxidation step is added before forming the CVD oxide film 3a in order to remove this damaged layer. Good. The silicon oxide film formed by thermal oxidation may be removed by wet etching with diluted hydrofluoric acid, or may be left as it is and C
The VD silicon oxide film 3a may be embedded.

Next, a 10 μm thick polycrystalline Si5 for bonding is formed on the CVD silicon oxide film 3a,
Polycrystalline Si5 is mechanically or chemically polished to flatten the joint surface. It is desirable that the film thickness of the polycrystalline Si5 is thin in order to reduce the manufacturing cost and the manufacturing time, but the film thickness may be comprehensively determined in consideration of the final film thickness and the restrictions on the manufacturing process (FIG. 3d). .

Next, for example, a p-type (100) single crystal Si substrate 1'is newly prepared, and a bonding surface of polycrystalline Si5 and Si are prepared.
The substrate 1 ′ is washed with H ₂ SO ₄ —H ₂ O ₂ to form a natural silicon oxide film of about 1 nm on the washed surface. By bringing both cleaned surfaces into close contact with each other and subjecting them to a high temperature heat treatment at, for example, 1150 ° C. for about 1 hour, the natural silicon oxide films are dehydrated and condensed and chemically bonded to complete the bonding (FIG. 3e).

After this bonding, the CVD silicon oxide film 3a is exposed by selective polishing from the back surface of the Si substrate 1 in which the element isolation region is formed, and the SOI layer 2 in which the CVD silicon oxide film 3a is embedded in the element isolation region. To complete the structural substrate (FIG. 4a). Next, the polishing damage layer on the surface of the SOI layer 2 is changed to a thermal silicon oxide film and removed. First, a thermal silicon oxide film 3b having a thickness of 100 nm, for example, is formed on the SOI layer 2 (FIG. 4b). At this time, the conditions under which the SOI layer 2 can be uniformly oxidized, for example, high temperature dry oxidation at 1000 ° C. or higher is advantageous. At low temperature (for example, 950 ° C. or lower) thermal oxidation, the end portion of the SOI layer 2 is exposed to SiO ₂ during thermal oxidation.
Causes a compressive stress to be applied to the oxide film due to the volume expansion of about 2 times, thereby suppressing the diffusion of oxygen molecules in the oxide film and suppressing the oxidation reaction at the Si / SiO ₂ interface.
For this reason, the end portion of the SOI layer 2 tends to have a thin oxide film formed and has a sharp shape. In high temperature oxidation at 1000 ° C. or higher, SiO ₂ is softened and flows, so that stress is relaxed and oxidation progresses uniformly. The oxide film thickness to be formed may be determined from the final film thickness of the SOI layer 2.

Next, the sacrificial oxide film 3b is removed by wet etching using diluted HF or the like to expose the SOI layer 2 again (FIG. 4c), and then an element is formed by a normal Si gate process. A gate oxide film 6 having a thickness of 13 nm, for example, is formed by thermal oxidation, and then a polycrystalline Si film is formed on the gate oxide film 6. Impurities are injected by a diffusion method in a POCl ₃ atmosphere at 900 ° C. and patterned to form a gate electrode. 7 (FIG. 4d). Next, impurities are ion-implanted into the source / drain formation regions by self-alignment to form an interlayer insulating film, and then heat treatment is performed at 950 ° C. for about 20 minutes to remove SO
A source / drain diffusion layer is formed in the I layer 2. After forming a contact hole on the diffusion layer and the gate electrode to form a metal wiring, a final protective film is formed to form a MOS transistor.

As described above, the shape of the element isolation trench 4 is controlled so that the SO protruding from the field surface after removal of the sacrificial oxide film
It is possible to obtain a tapered structure in which the shape of the I end does not sharpen at an acute angle, and it is possible to prevent electric field concentration at the channel end. When the shape of the SOI layer 2 is as shown in FIGS. 2A to 2C, as shown in FIGS. 5B to 5D, the element isolation trenches 4 corresponding to each are formed and the manufacturing method described above. To form a semiconductor element. The inter-element isolation groove 4 shown in FIG. 5 can be processed by, for example, dry etching, wet etching, mechanical processing, or a combination thereof.

Next, the structure shown in FIG. 2d in which the end portion of the SOI layer 2 is rounded in order to improve the electric field concentration preventing effect at the end portion of the channel is taken as a second embodiment of the present invention, and its forming process is shown in FIG.
It demonstrates using ac. First, the structure shown in FIG. 4c is formed in the same manner as the method described in the first embodiment. Then, the exposed SOI layer 2 is again subjected to sacrificial oxidation (FIG. 6a). At this time, in order to round the ends of the SOI layer 2, the thermal silicon oxide film 3b having a thickness of 100 nm, for example, is formed by high temperature dry oxidation of, for example, 1150 ° C. similar to the first sacrificial oxidation condition. By repeating the thermal oxidation, the ends of the SOI layer 2 gradually round. The oxide film thickness of the second time is determined so that the oxide film thickness of the field portion does not become thin after the oxide film on the SOI layer 2 is removed.

Next, the sacrificial oxide film 3b is removed by wet etching with dilute hydrofluoric acid or the like to expose the SOI layer 2 again (FIG. 6b), and then the gate oxide film 6 and polycrystalline silicon are formed by a normal silicon gate process. The gate electrode 7 and the like are formed in the same manner as the method described in the first embodiment to form a MOS transistor (FIG. 6c). According to the second embodiment, since the sacrificial oxidation and the removal of the oxide film are performed twice, the SOI layer 2 is further projected, but the shape of the end is rounded. S like this
The round process at the end of the OI layer 2 is more effective in preventing electric field concentration at the end of the channel. Other than thermal oxidation, for example nitric acid /
The SOI layer 2 exposed by the hydrofluoric acid mixture solution is wet-etched to obtain a structure with rounded ends.

Next, after the sacrificial oxide film is removed, the SOI edge shape protruding from the field surface is not only controlled by controlling the shape of the element isolation groove 4, but is also finished by a combination with sacrificial oxidation and polishing to a desired shape. As a third embodiment of the present invention, the forming process thereof will be described with reference to FIGS. First, for example, after forming the element isolation trench 4 having a shape as shown in FIG. 7a, the silicon oxide film 3a polycrystalline Si5 is formed in the same manner as the method described in the first embodiment, and then another Si substrate is formed. 1'is bonded (FIG. 7b) and polished until the silicon oxide film 3a is exposed to form an SOI substrate having a structure shown in FIG. 7c.

Next, the exposed SOI layer 2 is subjected to sacrificial oxidation at the broken line mm 'shown in FIG. 7c or more (FIG. 7d). After the oxidation, the sacrificial oxide film 3b is removed by wet etching with, for example, dilute hydrofluoric acid (FIG. 7e), and then the gate oxide film 6, the polycrystalline silicon gate electrode 7 and the like are described in the first embodiment by the normal silicon gate process. A MOS transistor is formed in the same manner as the method (FIG. 7).
f).

Here, since the sacrificial oxide film 3b to be formed becomes relatively thick and the field oxide film is also considerably etched by wet etching, the sacrificial oxide film 3b is removed beforehand by mechanical or chemical polishing. After thinning 3b, a method of removing it by normal wet etching or the like is also effective. . When the structure shown in FIG. 7b is formed and then mechanically polished up to the broken line l-l ', the SOI structure substrate having the structure shown in FIG. 4a is obtained. Similar to the first embodiment, this embodiment also provides a structure in which the shape of the SOI end exposed from the field surface after removing the sacrificial oxide film is not sharply sharpened, and electric field concentration at the channel end is prevented. You can

Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, the SO is bonded by the wafer bonding method.
After forming the I-structure substrate, polycrystalline silicon (or amorphous silicon) is formed as a protective film on the field oxide film, and the oxide film in the element isolation region is grown during sacrificial oxidation.
The surface of the SOI layer is prevented from protruding when the sacrificial oxide film is removed.

The manufacturing method of the fourth embodiment will be described below with reference to FIG.
This will be described with reference to FIG. 8a to 8e correspond to FIGS. 3a to 3e and are basically the same manufacturing method. However, in the process illustrated in FIG.
They are different from those shown in b. In order to obtain such a shape of the element isolation trench 4, in the step shown in FIG. 8B, for example, an etching gas; HBr / Cl2 / He-O2 = 30/10
/ 4 sccm, vacuum degree: 20 mTorr, RF power: 150 W, magnetic field: 75 Gauss are dry-etched to achieve the groove shown in the figure.

Then, from the state of FIG. 8E, CV is selectively polished from the back surface of the Si substrate 1 in which the element isolation region is formed.
D The silicon oxide film 3a is exposed and C is formed in the element isolation region.
A structural substrate of the SOI layer 2 in which the VD silicon oxide film 3a is embedded is completed (FIG. 9a). Next, a polycrystalline Si layer 8 is formed on the field oxide film. First, a polycrystalline Si film 8 having a thickness of 40 nm, for example, is formed on the entire surface (FIG. 9b) and patterned so as to remain on the field oxide film (FIG. 9c). For patterning, for example, the polycrystalline Si 8 on the SOI layer 2 is removed by dry etching or wet etching using a photoresist mask.

At this time, the SOI layer 2 is formed by sacrificial oxidation in a later process.
In order to make the continuation of the upper sacrificial oxide film 3b and the oxide film in the field portion into a flatter shape, the side surface shape of the end of the polycrystalline Si8 is preferably tapered as shown in FIG. 9c. For example, etching gas: Cl2 = 80sccm, vacuum degree: 100mTorr,
RF power: 300 W, magnetic field: 75 Gauss. For this purpose, it is not necessary to align the position of the end of the polycrystalline Si layer 8 with the position of the end of the SOI layer 2 including the pattern alignment margin.
It may be overlapped with the SOI layer 2 by about the film thickness.

Before forming the polycrystalline Si film 8 on the entire surface, a silicon oxide film having a thickness of 15 to 20 nm may be formed on the SOI layer 2. This silicon oxide film serves as an etching stopper when the polycrystalline Si film 8 is patterned. Next, the polishing damage layer on the surface of the SOI layer 2 and the polycrystalline Si film 8 are changed to a silicon oxide film by thermal oxidation. That is, a 100 nm thick thermal silicon oxide film 3b is formed on the SOI layer 2 (FIG. 9d). At this time,
Conditions under which the SOI layer 2 can be uniformly oxidized, for example, 1000 °
High temperature dry oxidation above C is advantageous. The oxide film thickness to be formed may be determined from the final SOI layer film thickness.

Next, as in FIG. 4c, the sacrificial oxide film 3b is removed by wet etching using diluted HF or the like to remove the SOI layer 2.
After exposing again (FIG. 9e), the gate oxide film 6, the polycrystalline silicon gate electrode 7, etc. are formed by the same silicon gate process as in FIG. 4d in the same manner as in the first embodiment. A transistor is created (Fig. 9
f).

The purpose of this embodiment is to prevent the surface of the SOI layer 2 from protruding from the surface of the field oxide film after the sacrificial oxide film is removed. Therefore, the polycrystalline Si 8 formed on the field oxide film is prevented. The film thickness is required to be ¼ or more of the sacrificial oxide film thickness 3b in the post-process (assuming that the silicon oxide film expands in volume two times due to thermal oxidation). In addition, polycrystalline S
i8 is not oxidized, but the sacrificial oxide film thickness is set to 1 from the beginning.
/ 2 or more CVD oxide film (silicon oxide film)
May be used as the deposited layer.

In the present embodiment, the polycrystalline Si film 8 formed on the field oxide film is simultaneously oxidized at the time of sacrificial oxidation to grow the oxide film in the element isolation region, and the thin film of the field oxide film at the time of removing the sacrificial oxide film. Of the SOI layer, and thus the protrusion of the surface of the SOI layer can be prevented. As a result, SOI
It is possible to solve the problem of deterioration of the breakdown voltage of the gate oxide film due to the electric field concentration at the end (channel end).

Next, a fifth embodiment of the present invention will be described. In this embodiment, after the SOI structure substrate is formed by the wafer bonding method, the silicon nitride film 9 is formed on the field oxide film, and the silicon nitride film 9 is used as an etching mask for removing the sacrificial oxide film to reduce the film thickness of the field oxide film. Prevent,
The surface of the SOI layer is prevented from protruding.

The manufacturing method of the fifth embodiment will be described below with reference to FIG.
Will be explained. First, the structure shown in FIG.
It is formed in the same manner as the method described in the embodiment. Then, for example, a silicon nitride film 9 having a thickness of 150 nm is formed on the entire surface,
Patterning is performed so as to remain on the field oxide film (FIG. 10a). Next, sacrificial oxidation is performed to remove the polishing damage layer on the surface of the SOI layer to form a silicon oxide film of, for example, 100 nm (FIG. 10b). Using the silicon nitride film 9 as an etching mask, the sacrificial oxide film 3b is removed by wet etching with diluted hydrofluoric acid or the like to expose the SOI layer 2 again (FIG. 10c). After removing the silicon nitride film mask 9, a gate oxide film 6, a polycrystalline silicon gate electrode 7 and the like are formed by a normal silicon gate process in the same manner as in the first embodiment to form a MOS transistor (FIG. 10d). ).

According to this embodiment, the silicon nitride film on the field oxide film serves as an etching mask during the wet etching for removing the sacrificial oxide film, and it is possible to prevent the reduction of the field oxide film. In this embodiment, the manufacturing process is performed by sacrificial oxidation after forming the silicon nitride film mask, but the order may be changed such that the silicon nitride film mask is formed after the sacrificial oxidation.

Next, a sixth embodiment of the present invention will be described. In this embodiment, the photoresist 1 is used when removing the sacrificial oxide film.
A mask of 0 prevents the field oxide film from being reduced and prevents the surface of the SOI layer from protruding. Hereinafter, the manufacturing method of the sixth embodiment will be described with reference to FIG.

First, the structure shown in FIG. 9A is formed in the same manner as the method described in the fourth embodiment. And the SOI layer 2
Sacrificial oxidation is performed to remove the polishing damage layer on the surface, and an oxide film having a thickness of 100 nm, for example, is formed on the SOI layer 2 (FIG. 11a). Next, the field oxide film is masked with the photoresist 10 (FIG. 11b), and the sacrificial oxide film is removed by, for example, wet etching with a hydrofluoric acid / ammonium fluoride mixed solution (FIG. 11c). At this time, the opening width of the resist is preferably equal to or smaller than the width of the SOI layer 2 in consideration of the pattern alignment margin.

After removing the photoresist, the gate oxide film 6, the polycrystalline silicon gate electrode 7 and the like are formed by the ordinary silicon gate process in the same manner as in the method described in the first embodiment to form a MOS transistor (FIG. 11d). According to this embodiment, like the silicon nitride film mask of the fifth embodiment, it is possible to prevent the reduction of the field oxide film.
Furthermore, the process can be simplified by using a photoresist as the etching mask.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view of an insulated gate field effect transistor showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing various shapes of an SOI layer 2.

FIG. 3 is a process drawing showing a manufacturing process of the former half of the configuration shown in FIG. 1;

FIG. 4 is a process drawing showing a manufacturing process of the latter half of the configuration shown in FIG. 1;

FIG. 5 is a configuration diagram showing a shape of a groove formed in a semiconductor substrate.

FIG. 6 is a process drawing showing a second embodiment of the present invention.

FIG. 7 is a process drawing showing a third embodiment of the present invention.

FIG. 8 is a process drawing showing the manufacturing process of the former half of the fourth embodiment of the present invention.

FIG. 9 is a process drawing showing the manufacturing process of the latter half of the fourth embodiment of the present invention.

FIG. 10 is a process drawing showing a fifth embodiment of the present invention.

FIG. 11 is a process drawing showing a sixth embodiment of the present invention.

FIG. 12 is a process chart showing a manufacturing process when the sacrificial oxide film is formed and removed by a normal manufacturing method.

[Explanation of symbols]

 1 Si substrate 1'Si substrate for bonding 2 SOI layer 3 Silicon oxide film 3a CVD silicon oxide film as a field oxide film 3b Thermal silicon oxide film 3c Thermal silicon oxide film as a field oxide film 4 Isolation groove 5 Bonding Si 6 gate oxide film 7 polycrystalline Si gate electrode 8 polycrystalline Si film 9 silicon nitride film 10 photoresist

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 27/12 F 21/336 9056-4M H01L 29/78 311 Y (72) Inventor Kazuhiro Tsuruta Kariya city, Aichi prefecture 1-chome, Showacho Nihon Denso Co., Ltd.

Claims (10)

[Claims] 1. An island-shaped single crystal semiconductor layer is formed on a semiconductor substrate with a dielectric layer interposed therebetween and the periphery of which is insulated and separated, and a source and a drain are formed in the single crystal semiconductor layer. In the semiconductor device having an insulated gate field effect transistor formed by further forming a gate electrode via a gate insulating film, the outermost surface of the single crystal semiconductor layer is a surrounding element isolation region. Which is formed above the surface of the dielectric layer forming the structure, wherein the outermost surface width W of the single crystal semiconductor layer is W ≦ W ′ with respect to the inter-element isolation region surface width W ′. A semiconductor device characterized by being formed. 2. A step of forming a groove having a shape in which a groove width is narrowed upward from a bottom surface to a predetermined height on a semiconductor substrate, and a dielectric is embedded in the groove to form an element isolation region, A step of using the semiconductor substrate as an element isolation region forming substrate, a step of adhering another semiconductor substrate to the element isolation region forming substrate, and a step of exposing the embedded dielectric from the back surface of the element isolation region forming substrate To form an island-shaped single crystal semiconductor layer whose periphery is insulated and separated by a dielectric, and to oxidize the surface of the single crystal semiconductor layer exposed on the polishing surface to remove the formed oxide film. And then removing a polishing damage layer on the surface of the single crystal semiconductor layer by the polishing treatment, and forming an insulated gate field effect transistor on the re-exposed single crystal semiconductor layer. The method of manufacturing a semiconductor device according to claim. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the formation and removal of the oxide film is repeated a plurality of times. 4. A step of forming a groove in a semiconductor substrate; a step of embedding a dielectric material in the groove to form an element isolation region, and using the semiconductor substrate as an element isolation region forming substrate; Bonding another semiconductor substrate to the isolation region forming substrate, and polishing the inter-element isolation region forming substrate from the back surface until the embedded dielectric is exposed to form an island shape in which the periphery is insulated and separated by the dielectric. A step of forming a single crystal semiconductor layer, a step of forming a protective layer on the entire polishing surface, and exposing the surface of the single crystal semiconductor layer so that the protective layer remains on the dielectric of the element isolation region. The step of once oxidizing the exposed surface of the single crystal semiconductor layer and removing the formed oxide film to remove the polishing damage layer on the surface of the single crystal semiconductor layer by the polishing treatment, and the exposed single crystal semiconductor layer again. crystal And a step of forming an insulated gate field effect transistor in the semiconductor layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the protective layer is polycrystalline silicon or amorphous silicon. 6. The step of exposing the single crystal semiconductor layer so that the polycrystalline silicon or the amorphous silicon remains on the dielectric in the element isolation region includes the remaining polycrystalline silicon or the amorphous silicon. The method for manufacturing a semiconductor device according to claim 5, wherein silicon is made to have a tapered shape from the surface of the single crystal semiconductor layer. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the protective layer is a silicon oxide film. 8. A step of forming a groove in a semiconductor substrate; a step of embedding a dielectric material in the groove to form an element isolation region, and using the semiconductor substrate as an element isolation area formation substrate; Bonding another semiconductor substrate to the isolation region forming substrate, and polishing the inter-element isolation region forming substrate from the back surface until the embedded dielectric is exposed to form an island shape in which the periphery is insulated and separated by the dielectric. A step of forming a single crystal semiconductor layer, a step of forming an oxide film on the surface of the single crystal semiconductor layer, a step of forming a protective layer on the element isolation region, the single crystal semiconductor using the protective layer as a mask And a step of exposing the single crystal semiconductor layer by removing an oxide film formed on the layer, and a step of forming an insulated gate field effect transistor in the exposed single crystal semiconductor layer again. The method of manufacturing a semiconductor device according to. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the protective layer is a resist film. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the protective layer is a silicon nitride film.