JPH08180001A - Communication system, communication method and network interface - Google Patents

Abstract

PURPOSE: To provide a network protocol and an interface for the communication of low overhead accompanied by a protective mechanism in the network of a multi-user computer using a direct deposit message. CONSTITUTION: A transmission side computer 270 prepares a message composed of control information and data, a send command 101 is provided with a connection identifier, the address of the data, the control information and the amount of the data to be sent and the message is directly sent out from an end point 66 to the network. In a reception side computer 272, the network is taken out from the network to this network interface and the network interface separates the message, directly places the data in the end point 79 and interrupts a processor according to circumstances.

Description

Detailed Description of the Invention

[0001]

This invention relates to computer network interfaces and protocols and more particularly to interfaces and protocols for low overhead communication. The invention is particularly applicable to asynchronous transfer method (ATM) networks and local area networks (LAN).

[0002]

[Prior art]

Conventional example 1. Communication systems are an important division of modern computer systems. The overhead for communication is
This is a basic feature for such a communication system.
Low overhead communication (as defined below, communication with low latency and low impact to the host computer) allows parallel, distributed, real-time computer
Of particular importance to the system.

Two basic characteristics generally contribute to the overhead in communication systems. The first is the passing of data, and the second is the message action. In particular, passing data requires addressing the receiving computer and message actions require interrupts to trigger the message action at the receiving computer. Thus, communication involves passing data and message actions. Data passing occurs when transferring data from a sending computer to a receiving computer. Message actions involve some special action when the data arrives at the receiving computer, eg, synchronization. The message action requests an interrupt from the receiving computer processor.

Communication systems can be classified according to whether the load is shared by the sending computer or the receiving computer. In receiver-based systems, the information that controls data passing and message actions resides on the receiving computer. On the contrary, in the sender-based system, the sender computer plays a more direct role by describing information in each message in order to control data passing and message actions.
In this case, the key information for passing data is
This is the destination address of the data. In receiver-based addressing, the sending computer cannot enter the message directly at the final address where it will be placed. That is, the sending computer can specify the buffer of the receiving computer, but the receiving computer automatically stores the message at a position unknown to the sending computer by, for example, ordering the pointers. In sender-based addressing, on the other hand, the address of the receiving computer that stores the message can be directly specified by the sending computer in each message. Receiver-based addressing introduces significant overhead compared to sender-based addressing. However, sender-based addressing presents protection issues.

The key information for a message action is whether to generate an interrupt upon arrival of a message. In a system using receiver-based interrupt, the receiving computer generates an interrupt each time a message arrives. In the case of a system using sender-based interrupts, the sender computer writes information about whether or not the arrival of the message causes an interrupt in each message.

Many conventional communication systems are receiver-based systems, such as Ethernet networks using the Internet Protocol. Similarly, many open and public local
Many area networks (LANs) use this type of protocol.

FIG. 13 shows a typical computer system including a first computer (hereinafter referred to as a sender computer) 50 and a second computer (hereinafter referred to as a receiver computer) 52. Either the sending computer or the receiving computer may be 50 or 52. The sending computer 50 and the receiving computer 52 are interconnected by a network via respective network interfaces 84 and 86. 2 in FIG.
Although two computers (i.e., sending computer 50 and receiving computer 52) are shown, the system is not limited to two. It may be a plurality of sending side computers and one receiving side computer, or one sending side computer and a plurality of receiving side computers, or a plurality of sending side computers and a plurality of receiving side computers. Further, each computer may be composed of processors connected to each other. That is, the transmitting side computer and the receiving side computer may be composed of mutually connected processors in a single computer such as one parallel computer. The term node as used below means either the sending computer or the receiving computer. Also assume that each node has its own virtual address space, independent of other nodes. That is, it is assumed that the node has virtual memory.

Networks may be used by multiple independent users. Each node may be used by more than one user. Therefore, a typical protection mechanism is provided to protect one user's process from accidentally or maliciously disturbing another user. Here is an example: 1) Prevent sending unauthorized messages to other users. 2) Prevent unauthorized access to the memory of other users. 3) Exclude access to the receiving computer by pretending to be an authorized user. These protection mechanisms are commonly found in standard scalable networks that interconnect multiple users. These protection mechanisms are rarely found in closed, proprietary networks.

The sending computer 50 is a processor 5
Including 4. The processor 54 is connected to the network interface 84 and is programmed to be compatible with the desired operating system 56. The operating system 56 manages node resources such as memory, processor time, network access, and arbitrates and protects requests from applications. Operating system 56 also controls interactions between applications 58 and 60 of FIG. 13 and applications such as processor 54. The operating system 56 has message buffers 62 and 64. Message buffers 62 and 64 are used to send messages to recipient computer 52 via network interface 84. Each application 58, 60 operates using memories 66 and 68, respectively. Memories 66 and 68 are referred to as endpoint buffers or simply endpoints. Similarly, the receiving computer 52 includes a processor 70 connected to a network interface 86. Processor 7
0 is programmed to match the desired operating system 72, as shown in FIG.

The operating system 72 and the receiving computer 52 are similar to the sending computer 50.
Message buffers 74 and 76 for Applications 78 and 80 also have memory portions 79 and 81
Associated with. Memory potions 79 and 81
Is called the endpoint buffer or simply the endpoint. Generally, the sending or receiving computer may include other processors, such as a network coprocessor or other coprocessor. To avoid ambiguity, processors 54 and 70 will be hereinafter referred to as "host processors." The message 83 in the conventional system includes a header. The header is used by the network 82 and network interfaces 84, 86 to direct the message to the appropriate node and endpoint. Applications (eg, 58) at the sending computer 50 and the receiving computer 52 communicate with each other by sending messages over the network 82. The message can be any data, including a procedure call.

As shown in FIG. 14, conventional communication includes at least the following steps. In step 99, the application 58 issues a send command. One way for application 58 to issue a send instruction is by executing the command described by "send" command 67. The command is an identifier (I
D), the source address from which the message data is retrieved and a size indicating the amount of data to be sent.
Part of the identifier is used to identify the receiving computer. Then, in step 100, the operating system copies the message from the application memory, such as endpoint 66, to a message buffer, eg 62, in operating system 56 of sending computer 50. This step
It is often optimized by mapping locations in the application memory to locations in the message buffer 62 to avoid the actual copying operation. if,
If necessary, in step 102 the operating system 56 executes the protocol. That is, the data sent is converted to the appropriate format as required by network 82. If the amount of data is large, it is divided into several messages, and the messages are
At 04, it is sent to the network 82 via the network interface 84. In step 106, the message normally arriving at the receiving computer causes an interrupt to processor 70. The operating system 72 then retrieves the message directly from the network (meaning network and network interface) and copies it into a message buffer 74 in the operating system. Alternatively, in a system with suitable hardware, the operating system may set up a direct memory access (DMA) with a network interface and use the DMA to retrieve the message and copy it to the message buffer 74.

In some communication systems, an intelligent network interface is proposed.
That is, the receiving computer 52 has a second processor (for example, Intel Paragon).
a communication coprocessor in n), and the second processor retrieves the message from the network 82 and copies the message into the message buffer 74. The operating system 72 executes the protocol, if necessary, at step 108. Then, in step 110, the operating system 72 copies the message from the message buffer 74 of the receiving computer 52 to application memory, such as endpoint 79. Normal operating system 7
2 copies this data to the application memory in response to an apparent receive request by the application, such as a "receive" command 77. The command contains an ID. A part of the ID is used to specify the message buffer 74, for example. The data is then received from the designated message buffer 74. The command further includes a receive address to which the message is copied and a size indicating the amount of data. The previously stored state information allows the operating system to automatically copy data from the message buffer 74 to the endpoint 79 without a request from the application for receipt. Also, like the sending computer, the copy operation is often performed by mapping a location in the application memory to a location in the message buffer 74 to avoid the actual copy operation.

Communication systems have overhead. The overhead includes the communication delay and the effect on the sending computer 50 and the receiving computer 52 processors 54 and 70. For simplicity of explanation, the communication delay time and the communication overhead will be simply referred to as delay time and overhead here. The delay time is defined as the total amount of time to move a message from application memory at the sending computer 50, such as endpoint 66, to application memory at the receiving computer 52, such as endpoint 79. Impacts on the processor include interrupt handling, data flow control and protocol handling. In order to reduce the delay time and influence in the host processor, it is necessary to reduce the overhead by optimizing each step described in FIG.

Small overhead is important for parallel, distributed computer systems and applications requiring fast response such as real-time control systems. In the parallel computer system, the small delay time is indispensable for reducing the processing time in the transmitting computer 50. The processing time at the sending computer 50 is the time to wait to read the data from a remote memory, such as the application memory 79 of the receiving computer 52. Or (for example, to get a lock,
The delay time for remote synchronization operations (such as releasing). Client-server in a distributed computer system
Model performance is often limited by the time required to execute a remote procedure call (RPC). The execution time of this remote procedure call is sensitive to the delay time. The importance of low latency is most apparent in real-time systems. Excessive delays in real-time systems will cause major accidents. Even in applications where low delay time is not very important, low delay time expands the application range of the application and expands the freedom of system configuration.

In a parallel computer system, a better computer system can be effectively developed with a small delay time. Also, parallelism can be increased. In a distributed computer system, a sufficiently low delay time can be paged by the sending computer 50, for example, through the network 82 to the memory of the remote node of the receiving computer 52. And this (not shown)
Can be faster than paging to local disk.
That is, it helps to realize a flexible real-time computer system in a client-server computer system with a small delay time. Reducing the impact on the host processor increases the predictability of the processor being in use and the availability of the processor, which is important for improving the execution efficiency of applications. Predictable processor utilization is especially important for real-time tasks performed by the host processor. Such an application used in real time,
It is important to isolate from unrelated asynchronous network events and ensure real-time execution.

The current-generation parallel computer system having an exclusive network is 1 μsec to 100 μse.
It operates with a delay time in the range of c. Local area
The delay time in the network is preferably less than 1000 cycles. For a 1 GHz processor that will be possible in the future, 1000 cycles is 1 μsec. Conventional 10 Mbps Ethernet
In the case of a net) LAN, the delay time is typically about 1 msec. The 100 Mbps first generation ATM network operates using conventional network protocols and interfaces with a delay time of approximately 250 μsec. Since the increase in network speed does not necessarily reduce the delay time, the improvement of the operating system, the network interface and the network protocol is required to reduce the delay time.

In order to clarify the obstacles for obtaining communication without overhead, the conventional method will be described in more detail. In a conventional communication system, for example, a distributed system such as TCP-IP or a parallel computer machine such as Intel Paragon, the conventional communication system handles a large amount of stream data. In such systems, messages are often large in size. The message is a buffer identifier (buffer I
D) and data. The interface hardware and operating system software separate the message arriving from the network into consecutive locations in the message buffer specified by the buffer ID (eg, message buffer 74). In many cases, the network interface will generate an interrupt to the host processor. The operating system copies the data directly from the network interface to the message buffer 74. The message buffer 74 may reside in the operating system. Alternatively, the operating system may set up a DMA transfer that copies such a message.

As mentioned above, this message buffer 74 is in the operating system 72 so that the operating system 72 at the receiving computer 52 copies the data from the message buffer 74 to application memory, such as the endpoint 79. Must. One way to eliminate the buffering overhead incurred for such a copy is to map the application memory of the endpoint 79 to the message buffer 74. Another way to eliminate the buffering overhead caused by the copy is to copy the data from the network interface directly into the application memory. Regardless of the implementation, the message is stored in contiguous locations in the operating system's message buffer. Alternatively, the message is divided and stored in successive locations in the message buffer of the application memory (if directly copied from the network interface to the application memory).

The location where the message is stored in the message buffer is automatically determined. For example, they are sequentially positioned by the pointer. Generally, each message received causes an interrupt to the receiving computer's processor and operating system. This interrupt is to retrieve a message from the network into a message buffer. The sending computer does not directly control the final address of the message. Alternatively, the sending computer does not directly control the interrupt status of the sending computer that received the message. Such a message processing method is called receiver-based addressing.
It is common for such conventional network protocols to process applications and message processing in a multiplexed manner on one processor.
However, this multiplexing introduces considerable overhead. Because, it requires many cycles for interrupt processing. First, an interrupt request is made to the operating system kernel, and then many cycles are used for interrupt parsing and branching. Finally, interrupt processing is performed. The overhead caused by this multiplexing causes delays in message delivery. In addition, the processing of the application in the receiving computer is delayed.

Interrupts caused by the arrival of asynchronously generated messages have the property that they cannot be predicted. This unpredictable interrupt handling is a problem for real-time systems. Also, there is a problem that repeated interrupts further delay the application. Addressing is done as follows in early multi-computers such as Intel iPSCs. The operating system kernel at the receiving computer separates the message from the network into message buffers, and the application separates the buffer contents into application memory. The processing by the kernel of such an operating system is performed by the IBM (International)
It is used as a current technology as shown in the technical field of parallel workstations such as SP1 developed by Al Busines Machines.

Another method used in conventional communication protocols is to add another processor, such as a communication coprocessor. For example, Intel Paragon
Handles the arrival of asynchronous messages. Such a communication coprocessor has a complicated gather-sc
It is also useful for atter operations. Complex gat
The her-scatter operation occurs when large size messages are used. The use of such coprocessors results in redundant hardware and is expensive.
In the receiving computer, there is a method that does not take a method of increasing resources such as using a coprocessor. That is, instead of adding significant resource or complexity to the receiving computer to determine where to put the message and how to process the message, the sending computer may make this decision. .

FIG. 15 shows a block diagram of another conventional system in which the sending computer takes the initiative. In this system, a sending computer 87 and a receiving computer 88 are connected by a network 82 via network interfaces 89 and 90. Operating systems 91 and 92 respectively
Does not need to have a message buffer. In this system, the sending computer specifies where on the receiving computer to put the message. FIG. 15 shows an example of the command. The "send" command 95 also indicates where the message is located on the receiving computer by including the receiving address in the command. Message 94
From the sending computer 87 to the receiving computer 8
Sent to 8. The message 94 includes, in addition to the header and data, the address where the message should be placed at the receiving computer 88. The sending computer may directly specify whether the receiving computer should generate an interrupt when the message arrives at the receiving computer.

FIG. 16 is a flow chart describing the general operation of the system of FIG. Step 111
In, first, the sending computer determines to which address of the receiving computer to put the message.
Create a send command with this address. Step 1
At 12, the message is sent directly from the application memory to the network. On the other hand, in the conventional system shown in FIG. 14, a message is sent from the message buffer of the operating system. In step 113, the message is retrieved from the network. In step 114, the message is separated from the network interface directly into the receiving address in the message. The conventional system shown in FIG. 14 fetches a message into the operating system message buffer. In this system, FIG.
It does not copy message data between the application memory and the operating system message buffer as shown in steps 100 and 110 of FIG. Rather, the message is copied directly from the application memory of the sending computer to the application memory of the receiving computer. The interrupt to the processor may or may not be specified by the message. The interrupt status is specified by the receiving computer. Various implementations of such a system depend on the presence, extent, and details of the protection mechanism, as shown in FIGS.

Such a network protocol and interface is available from Cray Res.
arch Inc. of Minnesota) Te
ra3D and DASH match of Stanford University
It is mainly used for parallel machines such as ine.
Such parallel machines with a global address space often use messages of small size (eg words or catch blocks). This message carries the receiving address and data. The data is stored directly at the receiving address contained in the message. In this way, the separation at the receiving computer is done as a normal process. The sending computer specifies all the information. Therefore, this method of message processing is called sender-based addressing. Similarly, the term "sender-based interrupt" is used for the method of interrupt generation.

Since such a parallel machine presupposes that a single user or a plurality of honest related users use the machine, the protection mechanism is internal to a network system exclusively connected to a plurality of related processors. So, it is not considered so much. That is, FIG.
Often, the protection mechanisms 97, 98 are omitted.

Next, an example of a system using pure sender-based addressing will be described. For example, there is a system called "Hamlyn""Hamlyn". For examples of "Hamlin" hardware, see "Hamlin: Interface for sender-based communication" Hamlyn: An.
Interface for Sender-Base
d Communication "(John Wilkes) Technical
Report HPL-OSR-92-13 Hew
lett-Packard Laboratories
(November 1992). The difficulty with publications on Hamlin is that there is little mention of the examples, but merely a high level design overview. In this system, protection mechanisms for a multi-user LAN environment are well described. However, the publication about Hamlin does not mention that this protection mechanism can be applied to any network. The publication on Hamlin only describes the protection mechanism for the unspecified network of "private multi-computer interconnects",
This protection mechanism is similar to other protection mechanisms for parallel computers.

As another system similar to Hamlin,
"Effective Support for Multi-Computers in ATM Networks""Effective Supp
ortfor Multicomputing on
ATM Networks "(C. Tecker et al. (C.T.
hekkath et al. ) By Technica
l Report TR93-04-03 Dept.
of Computer Science and E
ngineering, Univ. of Washi
ngton, Seattle, Washingto
n April 12, 1993). This system is a pure sender-based addressing software-based emulation for an ATM LAN. This system is designed for distributed system applications. Tecker et al. Did not mention hardware support for sender-based addressing.

Systems using pure sender-based addressing often suffer from the problem that the state of the receiving computer determines the position at which the receiving computer will place the data. For example, when an incoming message is queued at the receiving computer, the final position in the queue depends on the state of the receiving computer. Complete sender-based
For the addressing system to process the queue,
The sending computer needs to know the state of the receiving computer. The sending computer must keep track of this position. In this case, it becomes difficult to send data from a plurality of transmitting side computers to the same receiving side computer. Alternatively, the sending computer must use an additional message to know the state of the receiving computer, which raises the issue of atomicity of processing. Whichever of these two is selected, the delay time in both the host computer of the transmitting side computer and the receiving side computer is increased and it has an influence. Moreover, this increased knowledge of the sending computer about the receiving computer creates protection problems. Similarly, sender-based interrupts also have problems. The sender-based features limit the possible interrupts. For example, if the interrupted state of the receiving computer is caused by only one function of the states handled by the transmitting computer,
It becomes difficult for the receiving computer to prioritize the interrupt schedule.

Whether it is pure sender-based communication or pure receiver-based communication, in order to solve the overhead problem in the communication system, sender-based addressing is required in the new parallel machine. Many use variations of receiver-based addressing. For example, Meiko CS-2 (the Mei
ko CS-2, of Waltham, Massa
Chusetts) is a conventional transmitter / receiver system using receiver-based addressing and a remote read / receiver system using sender-based addressing.
Both light models are used. Like many machines, this CS-2 is designed for large data transfers,
It has a coprocessor for data separation and DMA to memory. Although this DMA can scatter / gather, it is often a constant stride and therefore runs short of sender-based addressing. Sender-based addressing and receiver-based addressing are combined exclusively with each other. Sender
In other new parallel computers that use base-based addressing and receiver-based addressing, these are mutually exclusive combinations. MI
T Ale Wife Machine (the MIT Alewi
fe machine) and the Stanford flash machine (the Stanford FLASH ma
In the cache), the cache block for common memory traffic uses sender-based addressing, and the receiver-based addressing is used for transmitting and receiving a large amount of data.
Generally, sender-based addressing is used for random access communication and receiver-based addressing is used for protected cross-domain communication.

Similarly, in a system in which sender-based addressing and receiver-based addressing are combined, "Active Message: Integrated Communication and Computing Mechanism""Active M
messages: A mechanism for
Integrated Communicationa
nd Computation "(" International Computer Architecture Symposium "Int'l Sy
mpodium of Computer Archit
image 256-266 T.W. von eiken et a
l. ) Work May 1992). In this system, the sending computer attaches to each message the address of the interrupt handler at the receiving computer. When the interrupt handler receives a message, it extracts the message from the network and places and processes it where desired. This message also contains other arguments. The length and action of the interrupt handler are bound, and the interrupt handler is
It is executed using the host processor in the address space of the receiving computer. Therefore, there is no cost to switch context for new threads. A major drawback of this system is that it is limited to single-user applications, at least without hardware support. Context switching is required to make it available to many users. Another problem with this system is that at the receiving computer, every message requires an interrupt, which does not reduce the impact on the processor.

Yet another related technique is the message driven processor system by William Dally. References include "Architecture of Message-Driven Processors,""Architecture of a Massa."
ge-Driven Processor "(Darry,
W. J. (Dally, WJ) et al. "International Computer Architecture Symposium" Inter
national Symposium on Comp
uter Architecture (1987),
"Message Driven Processor: Integrated Multi-Computer Processing Element""The Message Drive
en Processor: An Integrat
ed Multicomputer Processi
ng Element "(Darry, WJ (Dall
y, W. J. ) Proceedings of "The minutes of the 1982 IEEE International Computer Design Conference"
of the 1982 IEEE Internet
Ional Conference On Compu
ter Design: VLSI In Compu
ters & Processors, Cambridge, Massachusetts, October 11-14, 1992),
"Fine grain concurrent computing""Fine
-Grain Current Computi
ng "(Dally, WJ) et al.," Research Direction in Computer Science, "Resea
rch Directions in Compute
r Science: AnMIT Perspect
ive Albert Meyer
er) edited by MIT Press 1991).
In a message driven processor system, a host processor different from the conventional one executes a communication action by using a built-in communication primitive without using a separate network interface. The basic problem with this system is that it lacks a separate network interface and therefore cannot be used with conventional processors. This system also provides multi-user systems, especially multi-user systems such as user-to-user level communication.
I have not touched on the protection issues in the system. Also, this system is not compatible with ATM networks due to the incompatibility of message formats.

Local Area Network (LA
In a multi-user network environment such as N), communication is a global resource and a protection mechanism is needed to isolate the user from accidental and deliberate interference from other users of other processors. Becomes Similarly,
If the node is multi-user, a protection mechanism is needed to isolate multiple users on the same processor from each other. In such a multi-user network or multi-user processor environment, little research has been done to reduce the overhead.

[0033]

SUMMARY OF THE INVENTION In order to overcome the above-mentioned problems and limitations of the prior art, the present invention provides a network of multi-user computers using direct deposit messaging, which involves the overhead of a protection mechanism. Provides network protocols and interfaces for less communication.

[0034]

A communication system according to the present invention connects a sending computer and a receiving computer via a network, and the receiving computer has a network interface connected to a processor controlled by an operating system. In a communication method of a computer system, the sending computer sends to the receiving computer a message including an operand, an identifier of an action to be performed, and a reference to information stored in the receiving computer. Means, receiving means for receiving a message at the network interface, and means for operating by receiving the message at the network interface, the means being operable at the receiving computer. Means for deciding whether execution of the action is permitted, and means for operating when the action of the action is permitted in the network interface, wherein the processor of the receiving computer and the operating system are separate. In addition, there is provided an executing means for executing an operation based on the operand of the message and the information stored in the receiving computer and executing the action according to the operation.

In the communication system according to the present invention, the operand indicates an address of the memory of the receiving computer, and the executing means is based on the address of the message and the information stored in the receiving computer. It is characterized in that a message storage means for storing a message is provided at a predetermined position in the memory of the receiving computer.

In the communication system according to the present invention, the operand indicates an address register in the network interface which stores the address of the memory of the receiving computer, and the information stored in the receiving computer is the address register. The communication system further includes means for obtaining an address from an address register indicated by an operand,
It is characterized in that a means is provided for storing a message in the memory based on the obtained address.

In the communication system according to the present invention, the operand further indicates an offset,
The above communication method is further characterized by including means for modifying the address of the address register by the offset.

In the communication system according to the present invention, the execution means is a comparison means for comparing the operand and the information stored in the receiving computer, and the message requests immediate execution according to the comparison result of the comparison means. If it is determined that the processor is interrupted, the processor is provided with an interrupting unit for generating an interrupt.

The communication system according to the present invention is further characterized by further comprising updating means for updating the information stored in the receiving computer.

The communication system according to the present invention further comprises queuing means for queuing a message in a queue when it is judged from the result of the comparison by the comparing means that the message does not require immediate execution. It is characterized by having.

In the communication system according to the present invention, the operand represents an offset and an address register provided in a network interface for storing the address of the memory of the receiving computer. The information stored in is the address stored in the address register, and the communication method is further based on the means for obtaining the address from the address register indicated by the operand and the value indicated by the offset from the obtained address. It is characterized by comprising means for storing a message in the memory.

In the communication system according to the present invention, a processor that requests message transmission, and a processor that is connected to the processor, store an operand, an instruction of a desired action, and a receiver computer based on the request from the processor. A computer having a network interface that creates a message including a reference to the information provided, a processor controlled by the operating system, and a computer having a network interface connected to the processor;
A network for connecting a network interface of the sending computer and a network interface of the receiving computer, and for converting a message between the sending computer and the receiving computer, wherein the network interface of the receiving computer is
When receiving a message and performing the action indicated in the message, if the receiving computer is allowed to perform the action, perform the action based on the operand and the information stored in the receiving computer. Is characterized by.

In the communication system according to the present invention, the operand indicates the address of the memory of the receiving computer, and the action is based on the address contained in the message and the information stored in the receiving computer. Then, the message is stored at a predetermined position in the memory of the receiving computer.

In the communication system according to the present invention, the operand indicates an address register for storing the address of the memory of the receiving computer, and the information stored in the receiving computer is the address stored in the address register. The receiving computer is characterized by comprising means for obtaining an address from an address register indicated by an operand and means for storing a message in a memory based on the obtained address.

In the communication system according to the present invention, the operand further indicates an offset, and the communication system further comprises means for modifying the address stored in the address register with the offset.

In the communication system according to the present invention, the receiving side computer has a comparing means for comparing the operand and the state managed by the receiving side computer,
When it is determined that the message requires an immediate action based on the comparison result by the comparison means,
It is characterized in that an interrupting means for generating an interrupt is provided.

The communication system according to the present invention is characterized by further comprising updating means for updating the information stored in the receiving computer.

The communication system according to the present invention further comprises queuing means for queuing the message in the queue when it is determined from the comparison result of the comparing means that the message does not require an immediate action. It is characterized by that.

In the communication system according to the present invention, the operand indicates an offset and an address register provided in a network interface for storing the address of the memory of the receiving computer. The stored information is the address stored in the address register, and the communication method further includes means for obtaining the address from the address register indicated by the operand and memory based on the value indicated by the offset from the obtained address. And a means for storing a message.

The communication method according to the present invention is a communication of a computer system in which a sender computer and a receiver computer are connected by a network, and the receiver computer has a network interface connected to a processor controlled by an operating system. A method for transmitting a message from a sending computer to a receiving computer over a network, the message including operands, an instruction of an action to be performed, and a reference to information stored in the receiving computer; The receiving computer receives the message, the receiving computer confirms whether the action requested by the transmitting computer is permitted, and the above-mentioned confirming action is executed. If it is determined that possible,
It is characterized in that the processor and the operating system are separately provided with an execution step of executing an action in the receiving computer based on the operand of the message and the information stored in the receiving computer.

In the communication method according to the present invention, the operand indicates the address of the memory of the receiving computer, and the execution step is based on the address of the message and the information stored in the receiving computer.
It is characterized by comprising a message storing step of storing the message in a predetermined position of the memory of the receiving computer.

In the communication method according to the present invention, the operand indicates an address register in the network interface that stores the address of the memory of the receiving computer, and the information stored in the receiving computer is the address register. Stored in the address register, the communication method further comprising obtaining an address from an address register indicated by an operand,
The method is characterized in that a step of storing a message in a memory based on the obtained address is provided.

In the communication method according to the present invention, the operand further indicates an offset,
The above communication method is characterized by further comprising the step of modifying the address of the address register with the offset.

In the communication method according to the present invention, the execution step is a comparison step for comparing the operand and the information stored in the receiving computer, and the message requires immediate execution according to the comparison result of the comparison step. In this case, an interrupt process for generating an interrupt to the processor is provided.

The communication method according to the present invention is characterized by further comprising an updating step of updating the information stored in the receiving computer.

The communication method according to the present invention further comprises a queuing step of queuing the message in the queue when the result of the comparison in the comparison step does not require immediate execution. And

In the communication method according to the present invention, the operand indicates an offset and also an address register provided in the network interface for storing the address of the memory of the receiving computer. The stored information is an address stored in an address register, and the communication method further includes obtaining an address from the address register indicated by the operand and a memory based on a value indicated by an offset from the obtained address. And storing a message.

A communication system according to the present invention is a network communication system of multi-user computers, which comprises a transmitting side computer and a receiving side computer, and the receiving side computer has a processor and a memory. In the communication method assigned to the application program executed by the processor, the section sends a message including the operand, the reference of information stored in the receiving computer, and the data to be delivered to the application program to the network in the sending computer. Transmitting means for transmitting to the receiving side computer through the receiving side computer, and means for operating in the receiving side computer by receiving the message, at a predetermined position of the memory allocated to the application program. The predetermined position is independent of the storage position of the data of the message received before the message, and is the predetermined position determined by the state of the sending computer and the information stored in the receiving computer. Direct storing means for directly storing the message data, and means for operating in the receiving computer by receiving the message, wherein the processor is based on the state of the sending computer and the information stored in the receiving computer. On the other hand, it is characterized in that an interrupting means for conditionally generating an interrupt is provided.

The communication system according to the present invention further accesses the information stored in the receiving computer when the receiving computer does not allow the receiving computer to access the information in the receiving computer. It is characterized in that it is provided with a means for preventing this.

The communication system according to the present invention is a means that operates by receiving the message in the receiving computer, and changes the information stored in the receiving computer based on the state of the transmitting computer. It is characterized by having means.

A network interface according to the present invention is a network communication system of multi-user computers, and includes a sending side computer and a receiving side computer, and the receiving side computer has a processor and a memory. The section is assigned to an application program executed by the processor, and the sending computer uses an operand indicating a state of the sending computer, a reference to information stored in the receiving computer, and data to be passed to the application program. In a network interface for transmitting a message including a message to a receiving computer through a network, the receiving computer is a means that operates by receiving the message. A predetermined position of the memory allocated to the application program, the predetermined position,
It is a position independent of the storage position of the data of the message received before the message, and is a predetermined position determined by the state of the sending computer and the information stored in the receiving computer, and before the message. A direct storage means for directly storing the data of the message at a predetermined position that is determined independently of the position used for storing the received message, and means for operating by receiving the message, It is characterized in that an interrupting means for conditionally generating an interrupt to the processor based on the state of the side computer and the information stored in the receiving side computer is provided.

The network interface according to the present invention further comprises means for preventing access to the information stored in the receiving computer when the sending computer is not permitted to access the information. It is characterized by having.

The network interface according to the present invention further comprises means for operating upon receipt of the above message, and means for changing the information stored in the receiving computer based on the state of the transmitting computer. Characterize.

[0064]

According to the communication system of the present invention, the execution means operates independently of the processor and operating system of the receiving computer, and the action specified in the message is performed based on the operand of the message and the information stored in the receiving computer. Does not place any load on the receiving computer's processor and operating system. Therefore, the communication method has a small overhead.

Further, in the communication system of the present invention, the message to be transmitted is stored in the address of the memory designated by the operand by designating the memory address of the receiving computer as the operand.

Further, in the communication system of the present invention, by designating the address register of the receiving computer as the operand, the transmitted message is stored at the address stored in the address register indicated by the operand.

Further, in the communication system of the present invention, the operand is provided with an offset value, and the message is stored in the address obtained by the modification by the offset.

In the communication system of the present invention, the comparing means determines whether or not the sent message is urgent, and if the message is urgent,
The processing is immediately performed by the interruption means.

In the communication system of the present invention, the updating means updates the information stored in the receiving computer.

Further, in the communication system of the present invention, the message is queued in the queue when it is judged by the comparison means that the sent message does not require an emergency.

Further, in the communication system of the present invention, the offset and the address register are designated by the operand. The receiving computer adds the offset value to the address of the designated address register, and stores the message in the memory based on the obtained address.

In the communication system of the present invention, the sending computer and the receiving computer each have a processor and a network interface, and the network interface of the receiving computer executes the action indicated by the message. Check if the action is an action that can be performed on the receiving computer. Then, when the execution is permitted, the action is executed based on the operand of the message and the information recorded in the receiving computer.

Further, in the communication system of the present invention, the address of the memory of the receiving computer is designated by the operand. Then, the message sent to the address designated by the operand is stored.

Further, according to the communication system of the present invention, by designating the address register of the receiving computer as the operand, the transmitted message is stored at the address stored in the address register indicated by the operand.

In the communication system of the present invention, the operand is provided with an offset value, and the message is stored in the address obtained by the modification by the offset.

In the communication system of the present invention, the comparing means determines whether or not the sent message is urgent, and if the message is urgent,
The processing is immediately performed by the interruption means.

Further, in the communication system of the present invention, the information stored in the receiving computer is updated by the updating means.

Further, in the communication system of the present invention, the message is queued in the queue when it is judged by the comparison means that the sent message is not urgent.

Further, in the communication system of the present invention, the offset and the address register are designated by the operand. The receiving computer adds the offset value to the address of the designated address register, and stores the message in the memory based on the obtained address.

In the communication method of the present invention, the execution step operates independently of the processor of the receiving computer and the operating system, and based on the operand of the message and the information stored in the receiving computer, the action specified in the message. Does not place any load on the receiving computer's processor and operating system. Therefore, the communication method has a small overhead.

Further, in the communication method of the present invention, the memory address of the receiving computer is designated in the operand, and the message to be transmitted is stored in the memory address designated by the operand.

In the communication method of the present invention, the address register of the receiving computer is designated as the operand to store the transmitted message at the address stored in the address register indicated by the operand.

Further, according to the communication method of the present invention, the operand is provided with an offset value, and the message is stored in the address obtained by the modification by the offset.

Further, in the communication method of the present invention, it is judged in the comparing step whether or not the message sent is urgent, and if the message is urgent,
The process is immediately performed by the interrupt process.

Further, the communication method of the present invention updates the information stored in the receiving computer in the updating step.

Further, the communication method of the present invention queues the message in the queue when it is judged by the comparison step that the sent message is not urgent.

Further, in the communication method of the present invention, the offset and the address register are designated by the operand. The receiving computer adds the offset value to the address of the designated address register, and stores the message in the memory based on the obtained address.

According to the communication system of the present invention, the message sent from the sending computer is directly stored in the memory of the receiving computer. Then, if necessary, the action specified in the message is immediately executed by the interrupting means. In this way, a communication system with less overhead can be obtained.

The communication system of the present invention also has a protection function by preventing unauthorized access.

Further, in the communication system of the present invention, the changing means changes the information of the receiving computer based on the state of the transmitting computer.

Since the network interface of the present invention stores the message directly in the memory allocated to the application program, a system with reduced overhead can be obtained. The location where the message is stored is also independent of the location of the previously stored message. When an urgent message is sent, the interrupting means immediately executes the process.

The network interface of the present invention has a protection function by preventing unauthorized access.

Further, in the network interface of the present invention, the changing means changes the information of the receiving computer based on the state of the transmitting computer.

[0094]

【Example】

Example 1. This embodiment describes network protocols and interfaces for low overhead communication in a network of multi-user computers with direct deposit messaging. First, the features of the invention described in this embodiment will be described.

In direct deposit messaging, a message to be directly separated is specified. You can also use a direct
Deposit messaging puts data and control information directly where it is needed. In such a system, the host processor divides events as necessary to control the events that occur asynchronously. Data passing events, such as placing data directly in user memory, are handled directly without the use of a host processor. The events that the host processor needs to handle are mainly synchronous events, but they are divided into actions that require immediate processing and deferrable actions that can be processed at a convenient time. . Because data and events are separated in this way, it is not necessary to add the resources needed to bypass all events, only enough resources to bypass events not associated with the host processor.

In order to efficiently separate these events,
The receiving computer processes the message using the information in the message from the sending computer. The response of the receiving computer to the message depends on both the information from this sending computer and the information stored on the receiving computer. The message contains instructions for the operation desired by the sending computer. That is, it includes one or more operands specified by the sending computer and one or more operands for the state of the receiving computer. The receiving computer checks whether the required action is permitted, and if so, executes the action according to the operand specified by the transmitting computer and the state of the receiving computer.

The action executed by the receiving computer is passing a message. In that case, the operands in the message specify values used for various addressing modes such as direct, indirect, post-increment, and index modes. Data is directly written to and read from such addresses while protecting multiple users and without the intervention of the host processor or operating system. The action of the receiving computer may also be a conditionally generated interrupt. In that case, the operand determines whether the message requires an immediate action or a deferrable action, also considering the state of the receiving computer. The actions of the receiving computer may also occur at special memory locations called address registers in the network interface. This network interface is particularly effective for an asynchronous transfer method (ATM) network. Within that network, the messages are the basic data units of certain standards called cells.

The interface design of the present invention also supports the multi-cell format. In the multi-cell format, the first cell in the stream of cells is the control cell and the following cells are pure data. In this way, the bandwidth is expanded.

Further, in the present invention, overlapping end points are provided so that the end points can be freely shared. Access to the address registers is limited to contiguous register blocks called windows. Like the endpoints, the address register window allows overlap and nesting with other address register windows. As a result, sharing of the address register window can be freely controlled. The present invention also includes a protection mechanism for the address register so as to prevent access to different registers of the sending computer.

Further, in the present invention, various other strengthening measures are adopted. For example, integrating exception handling and flow control, paging connection and endpoint tables, adding global registers, and using hybrid mapping to reduce translation lookaside buffer misses.

Also, an instruction pointer is described in the operation field of the message, the instruction memory makes the instruction memory of the receiving computer accessible, and the instruction memory can be implemented in the portion of the instruction memory accessible by the instruction pointer. It is also possible to have high level operations. As a result, the sending computer is isolated from the knowledge of the receiving computer. Thus, full spectrum operation of sender-based addressing and receiver-based addressing is obtained.

According to this system, the sending computer can specify the necessary action for the message as much as possible. On the other hand, the receiving computer can control the reception of messages for protection. Also, message reception can be controlled for operations associated with the receiving computer. By doing so, communication overhead can be reduced. Further, since the message is directly separated into a necessary place by using the information of both the sending computer and the receiving computer, the delay time can be reduced. The receiving computer's processor operates only when synchronization is required. That is, interrupts can be screened to see if they are needed for each message. Interrupts occur only if the message requires immediate action, so the processor is less impacted. Thus, the combination of asynchronous event control and direct deposit messaging adds flexibility.
It provides a system with low overhead, which allows for the separation of control and data and can be accompanied by a complete protection mechanism. This network interface and protocol can be widely applied to various networks and in parallel, distributed, and real-time computers.

The above is the features of the invention described in this embodiment, and the invention will be described more specifically with reference to the drawings. FIG. 1 is a block diagram of the communication system of this embodiment. The transmission side computer 270 and the reception side computer 272 have network interfaces 274 and 27.
Network 82 via 6. The sending computer 270 and the receiving computer 272 have the desired operating systems 278 and 280, respectively.
Processors 54 and 7 programmed to suit
Has 0. To describe the present invention, the terms endpoint and connection are used below. The invention is adaptable to many types of computer networks, and the endpoints and connections described below are not limiting of the invention. In this example, an endpoint shall refer to a contiguous area of virtual memory. The two endpoints are coupled by a virtual channel set up to communicate. This combination may be one-to-many or many-to-one multicast. That is, the combination of endpoints of 1: 1 or n: n is not limited. Applications 58 and 60
Are executed on the sending computer 270, and the applications 78 and 80 are executed on the receiving computer 272. These applications are assigned one or more endpoints. For example, endpoints 66, 68, 79, 81. The operating systems 278 and 280 have connection state information and mapping information 282 and 284. These indicate the states of the sending computer 270 and the receiving computer 272. This information is stored in 286,288 on the network interfaces 274,276.

The message 290 is sent from the receiving computer 270 to the transmitting computer 272 together with the control information and data. The control information may include an indication of the operation to be performed, one or more operands indicating the state of the sending computer, and one or more references to information stored in the receiving computer. This information stored in the receiving computer is called the state maintained by the receiving computer or the receiver state.

FIG. 2 is a flow chart of the general operation of the system shown in FIG. In step 115,
The sending computer first generates control information and data separately and assembles a message. As with the example command 101 shown in FIG. 1, a "send" command includes a connection identifier, data address, control information, and the amount of data sent. In step 112, this message is sent directly from the application memory to the network. In step 113, the message is retrieved from the network to the network interface. In step 116, the network interface separates the message and places the data directly in memory. And / or interrupt the processor as the case may be.

The message from the endpoint 66 is
Bypasses the operating system and host processor of the sending computer. In order to determine whether to interrupt the processor 70 and the receiving computer 272 in some cases, at the receiving computer,
Operands may also be compared to connection state information. Also, these operands may be associated with connection, state, and mapping information. The mapping information determines, for example, the address of the endpoint 79 on the memory for storing the message data.

In this way, copying the message data from the message buffer of the operating system to the application memory is omitted. further,
Interrupts are occasionally generated depending on the state of both the sending computer and the receiving computer. The address where the message data is placed is determined by the state of the sending computer and the state of the receiving computer. As such, the sending computer need not have undue information about the receiving computer.

This system is based on the idea that sending a message should be simple. However, since the nature of receiving messages is asynchronous,
Receiving messages is complicated. Message processing at the receiving computer should separate message passing and message action execution. By separately processing in this way, even if messages arrive asynchronously, they can be dealt with. The events of passing messages and executing message actions can be identified by the need of the host processor of the receiving computer. Events such as message passing do not need to be processed directly by the host processor. Other events, primarily for synchronization purposes, require interaction with the host processor. Other events are further divided into actions that need to be processed immediately and actions that may be delayed. Those that may be delayed may be collected and processed at a time convenient to the host processor. Due to the separation of data and events as described above, the resources to be added are not the resources required to bypass all events, but only the resources that bypass events not related to the host processor.

Passing a message means placing the message at a desired location in the memory on the receiving computer. For example, there is remote write or direct memory access (DMA). A message action is to do something in response to receiving a message. For example, returning a value, performing a read, notifying a task that data has arrived, or making a task in the scheduler's queue ready for execution (where the scheduler's queue is the processor It is a data structure that indicates that it is a task that is executed by) or the execution of an arbitrary interrupt process. A specific example is the execution of a remote procedure call (RPC). Whether to perform the processing immediately or later depends on the following. 1) The remote process is requesting an action,
Are you waiting for the outcome of the requested action? (Hereinafter, this remote process is called a waiting task. This waiting task does not always exist in the sending computer.) 2) Priority of action and priority of other processing of receiving computer How is your relationship with Examples of processing that must be executed immediately include read processing in which the waiting task needs the result of execution,
This is a synchronous process. Alternatively, it is a control process having a high priority such as a process of an operating system. An example of a process that may be delayed normally is one in which a task is notified that data has arrived, or a task in a queue of a scheduler can be processed. Relayed messages are another type of message that does not have to be processed immediately.

In many cases, the system is configured so that it does not need to respond immediately. For example, the remote node performs other tasks while waiting for a response from the message action. Even if a message arrives for a waiting task that is not currently executing, such as notifying an inactive process that the data has arrived, the action on the response to that message may be delayed. When processing is delayed, it may be queued for processing later at a more convenient time for the receiving computer. Messages that may be delayed in this way become synchronization events. Enqueuing a message means sending the message and updating the queue pointer.

This type of protocol is referred to herein as direct deposit messaging. To implement direct deposit messaging, the message contains connection and control information and data. A connection is an identifier that implicitly identifies the endpoint of the receiving computer. Control information refers to the action to be performed and one or more operands. Each operand may be an address used by the receiving computer. Alternatively, each operand may be a parameter used to determine whether the action should be performed immediately or may be delayed. Or it could be the name of the state of a receiver. The address is coded as an offset from the base of the endpoint. It is essential that the offset is a logical address of the network. By using the logical address of the network, for example, the receiving computer and the sending computer take into consideration the details of address space size, mapping between virtual space and real space, and page size. You don't have to. Therefore, it is easy to change the address and accommodate a heterogeneous node. Moreover, the offset can be encoded in the message with a smaller number of bits, as it need not indicate the full range of virtual or real addresses.

Simple actions, ie, normal operations, are provided that are simply performed without the intervention of a host processor or operating system. More complex actions are processed by the host processor. A simple action here means a simple data movement. That is, a conditional interrupt for reading or writing to the position of the end point, or processing which may be delayed or immediate is issued to the host processor. A simple operation is a data transfer such as a direct read or write issued by the sending computer. The sender specifies the source data by offset from the base of the sender's endpoint for direct writing, and the receiver's position by the offset from the base of the receiver's endpoint. . The message is
Includes offset and data on the receiving side. For reading, the sending computer sends a message with a request for a direct write to the receiving computer. This message is specified by the offset on the receiving computer and the offset for reading the data on the transmitting computer for reply. The message includes an indication in the response connection if the connection is not capable of full duplex communication.

Action execution is one of the functions of the states of the receiving computer and the transmitting computer. To enable the action to be performed, the receiving computer of each connection maintains a state. In other words, the operand of the message stores information whose name is the name or obtains the address of the receiving computer. For simplicity, this state shall be stored in a register at a special address, called the "address register" here. This state is not a special register and can generally be stored in memory. Thus, a message action is an operational function specified by the sending computer. A message action is also an operation function, such as the contents of an address register, specified by an operand indicated by the state of the sending and receiving computers. Here is an example of a primitive operation that uses the states of the sending and receiving computers. (1) Generation of address 1 Direct addressing: effaddr = operand 2 Indirect addressing: effaddr = <addreg _i > 3 Indexed addressing: effaddr = <addreg _i > + operand (2) Register operation 1 addreg _i ← operand 2 add _i ← unary-op <addreg _i > 3 addreg _i ← <addreg _i > binary-op <addreg _j > i and j need not be different. (3) Conditional operation _{1 if (<addreg i> compare} -op operand) then generate interrupt at end 2 if (<addreg i> compare-op <addreg j>) then generate interrupt at end i and j is necessary to differ Absent.

One example of the "address generation" in the above (1) is to calculate an effective address (effaddr). The effective address is an address for reading and writing data. <X> means the contents of memory location X. ”
"operand" is data in the message or another operand. The message operation controls whether a read or write occurs in the memory. The message operation controls the selection of the primitive operation and its execution order. To do.
The “conditional operation” of (3) above occurs at any time, but it is desirable that the interrupt occurs at the end of the combined operation. By combining these basic primitive operations, you can create a variety of free compound operations. For example, the indirect write with post-increment can be created by the indirect process with the register operation of (2) above. <Addreg _i > ← MSG addreg _i ← <addreg _i > + operand The last step is addreg _i ← <addreg _i >
+ <Addreg _j > may be used.

Considering cells as a unit, this composite operation is equivalent to a DMA whose increasing value is equal to the slide. But changing operands or <add
reg _i > results in various slides. As another example, priority queuing and interrupts can be created by the following instruction combinations.

[0116] _{<addreg i> ← MSG addreg p} ← <addreg p> + <addreg s> if (operand greater than <addreg j>) generate interrupt at end addreg i ← <addreg i> bitwise-or operand

If "operand" indicates the priority of the message, addreg _p indicates the end of the queue to which the message of this priority is added. addre
g _s includes the size of MSG. addreg _i has the priority level of the receiving computer. Where p,
i and s have different values. p, i, s are
It is used as an index of operands and registers, and is specified by the message. Complex compound operations like queuing with this priority consist of a number of compound operations. For example, to perform priority queuing, two complex operation messages are required if the receiving computer performs one register operation per message.

A final example will be given. You may want to add a message to one of several different queues without interrupting it. In this case, maintain a non-empty queue bit vector. This mechanism can generally be implemented in the same manner as priority based interrupts, but the most significant bit of addreg _i is used to block the interrupt. This method of implementation is
It assumes both unsigned comparisons and that there are fewer queues than addreg _i bits. The second assumption that there are fewer queues than addreg _i bits can be relaxed by using multiple address registers. The message may be added to a queue within a particular endpoint within the operating system. In this case, the deferred action is executed by the operating system.

As another example, fetch and increment, read modify write, compare
Various atomic operations, such as AND-SWAP, can be performed by using one or more address registers for the destination location and performing register operations for increment and compare.
Barrier synchronization can also be performed in this way. When the process reaches the barrier point,
Toggle the bits in the specified address registers of all processes with "barrier set." Then wait for a conditional interrupt when all bits are set (or cleared).

The protocol of this example provides at least the following benefits. First, the protocol of this embodiment makes the state of the sending computer, the state of the receiving computer and the combination of both operations very powerful. The protocol of this embodiment has the full functionality of both conventional receiver-based addressing and sender-based addressing. The protocol of this embodiment can carry various requests of what the sending computer knows. Alternatively, various requests for knowledge separation between the sending and receiving computers can be transmitted. Further, the protocol of this embodiment can change the information mixed between the sending computer and the receiving computer for each message. The use of indirect operations eliminates the drawback that the sending computer has too much knowledge about the receiving computer, thus adding a protection mechanism by isolating the sending computer from the receiving computer. There is. The actual storage address is an address that the sending computer does not know and may be determined by some of the address functions of the receiving computer. Similarly, the interrupted state may be part of the receiving computer's information (via a message) generated by a process that the sending computer does not know its existence. A mechanism may be provided to protect the register from being accessed by the sending computer, as described below. This protection mechanism prohibits the sending computer, for example, from reading, writing, or setting or changing the state content of the designated receiving computer to the address register of the receiving computer.

Secondly, according to the protocol of this embodiment,
Real-time systems can add significant predictability. Predictability can be increased by limiting interrupts at well-coordinated points. The protocol of this embodiment removes asynchrony and uncertainty from the events of an asynchronous network. Thirdly, the protocol of this embodiment allows the action handling to be more effective and reduce the overhead. This is because the interrupt overhead is gradually amortized over many actions. Combining polling with the above protocol, hybrid interrupt
A polling method may be used. .

Finally, according to the protocol of this embodiment,
More complex operations include multiple commands
It can be created by combining the results of message operations. As described above, the protocol of this embodiment is based on the endpoint and the connection. Endpoints and connections are placed and relocated by kernel calls. It is desirable to relocate the endpoint on a page-by-page basis. in this way,
Page protection in host virtual memory is used for endpoints. A connection can be established between any combination of endpoints, including endpoints on the same node. The protocol for establishing the connection is Berkeley UNIX socket (Barkere).
It is very similar to the session establishment used in y UNIX sockets). Prepare an out-of-band mechanism, such as boot time, used for kernel endpoints and connections, and use this out-of-band mechanism to arrange the endpoints and connections on the receiving computer.

An endpoint may have multiple originating connections and / or multiple terminating connections. The connection may be simplex or duplex, or multicast. Multiple connections starting from one endpoint or ending at one endpoint share the same mapping information. However, endpoints can be overlapping or nested to form more complex protection patterns. For example, connection A can create a first endpoint in the virtual address domain (v _l , v _u ). Connection B can create a second endpoint. The second endpoint is a portion of the connection A within the domain of the first endpoint.
Connection A can access all of the endpoints of connection B, but connection B can access only part of the endpoints of connection A. Alternatively, the connection B is the area of the connection A (v _l ,
You may create endpoints that partially overlap v _u ). Thus, both the connection A and the connection B can access only the limited shared area without the one end point affecting all the other end points. Alternatively, different protection mechanisms can be implemented by mapping the physical pages of the endpoints to virtual address areas with different types of page protection mechanisms.

Network protection is provided as follows. Access to the network through out-going connections is controlled by the per-connection state maintained by the kernel. The arrival of a message from the network determines whether to allow it in the receiving computer's connection state maintained by the receiving computer's kernel. Permission to receive a message from an incoming connection means to write the message to the associated endpoint. However, the recipient's address must be mapped to the appropriate endpoint's address. This operation is allowed by page-wise access rights. A protection mechanism may be provided to the system by the receiving computer verifying that the requested operation and the address used by the receiving computer are appropriate.
For example, a memory area is designated for each application. If the address where the data is written is not in the specified area, access is denied.

Next, an embodiment of this system in the ATM network will be described. The following is an example and the invention may be implemented in different ways for other networks. FIG. 3 shows an example of the format of the 53-byte ATM cell 120 in this embodiment.
In its simplest format, a cell contains data and control information along with a standard network header and other information. The size of the data fields in the format of the diagram is merely an example and is not a limitation of the present invention. In FIG. 3, ATM header field 13
2 includes link routing and traffic control information. Link routing indirectly specifies the receiving computer. This A
The TM header field is 5 bytes and is standard A
Suitable for processing by TM switch. Although not shown, the connection number described below is encoded in the virtual channel / virtual path identifier (VCI / VPI) field in this header.

The data field 122 is a 32-byte field. The control data attached to each cell 120 described below is 16 bytes. The size of data field 122 is 32 bytes memory block size and cache block size.
It matches the size. As a result, the execution speed becomes faster and the hardware implementation becomes effective. The mask field described below is used to remove unnecessary message data in the receiving computer. A 2-byte Cycle Redundancy Check (CRC) field 124 may be provided at the end of the cell 120, corresponding to the data field 122. This field is used to prevent false messages from being considered as valid messages. The other 2 bytes are unused.

The control information is an operation of 4 bytes.
The field 130 is included. The operation field 130 specifies the type of operation performed on the receiving computer. The operation field 130 includes a mask field 131 and an opcode field 129. Opcode field 129 specifies the operation. The mask field is used to block the reading and writing of a 4-byte word in the block when the data field 122 is blocked. That is, bit i of the mask field indicates whether data word i is read or written. This function is useful for updating a location within a block with the value of the location adjacent to that location, for example without changing the variable. A 4-byte operand field 126 is prepared. The operand specified by operand field 126 is a 32-bit direct source operand (offset or data). On the other hand, the destination operand is a 4-byte index field 1
3 separate registers encoded at 28
Specified by index. These three index fields are indicated by 121, 123 and 125 in the figure. The check field 127 holds a simple checksum of the preceding control field so that control information decoding can be started without waiting for the entire cell to arrive.

For read requests to remote nodes, the data field 122 is write
Contains control fields for replying to messages. A multiple cell message format with multiple cells is used for block transfers. The first cell in this format is the "control" cell with the write format shown in FIG.
The cells that follow are standard AAL5 (ATM adaptation layer 5, ATM signaling standard) cells. All block transfers are 1 to avoid confusion of cell boundary, length and CRC in the last AAL5 cell.
Divide into 6 bytes each.

As described above, the communication system of this embodiment is characterized in that it is a model for directly placing a message, and this model is based on the use of endpoints and connections. That is, the application allocates endpoints, sets up connections between the endpoints, and then sends messages over these connections. In order to support the operation of storing such a direct message, the operating system of each node maintains the following data structure. In order to enable high speed operation, as described in detail in FIG. 5 described later,
On hardware, some or all of these data structures may be cached.

The endpoint table has an entry for each endpoint at that node (eg, the sending computer). The endpoint table can be searched by endpoint number. Each entry in this table stores the base memory address of the endpoint, the endpoint size, virtual to physical mapping information, and access information. The memory address of the endpoint is, for example, the receiving computer
At 72, the start addresses of memory 79 and 81 are shown. The access information indicates, for example, whether the endpoint is a private memory, a read-only memory, or a shared memory. Each entry in the table also stores all available connections to the endpoint and the processes associated with the endpoint. The connection table contains an entry for each connection that begins or ends at that node and can be searched by connection number. Each entry in this table stores the endpoint number, the base and area of the address register, the connection state information and the response connection information.

A node address table is also used. Each entry in the node contains the name of the remote node and the connection number. The connection number is for a direct or indirect connection to the remote node's operating system. The index to the table is a unique and global identifier for each node.
This table is used to contact the remote node when setting up a connection. The table may include naming information for going through some other signaling mechanism, such as an Internet Protocol (IP) address. The data is sent to the endpoint. The interrupt is sent to the operating system. In particular, the data is not sent to the process associated with the endpoint, but to the endpoint of the receiving computer specified in the connection. The interrupt is not sent to the specified process, but to the operating system running on the receiving computer. The operating system then sends an interrupt to the designated processor.

The operation flow of such a system is shown in the flowchart of FIG. In step 200, the sending computer 270 first allocates an endpoint in the sending computer's virtual address space. Find or create a matching slot in the endpoint table, write the base address of the endpoint into the open slot, and write the virtual to physical mapping information. In step 201, the sending computer contacts the intended receiving computer via a connection.
A connection is a Transport Control Protocol / Internet Protocol (TCP /
A dedicated operating system connection, such as an IP) connection, or other network. The sending computer then issues a request to the receiving computer to set up the connection with the appropriate endpoint buffer size. In step 203, the receiving computer allocates in its virtual address space a buffer area of the requested endpoint buffer size. Then, it finds or creates an empty slot in the endpoint table, and writes the buffer base address and virtual-to-physical mapping information. The receiving computer then authorizes the connection. In a multicast connection, the above processing is repeatedly performed in each set of the sending-side computer and the receiving-side computer that are the targets of multicast. In step 204,
A message containing the offset from the base of the endpoint is sent from the sending computer to the receiving computer via the established connection.

This protocol may be implemented on hardware other than special purpose hardware. So this protocol is
It can be realized by using a commercially available computer and a computer program for network interface. For example, two DEC Station 5000 /
240 Workstation (Digital Equ
It can be carried out using the equipment Corporation). Each workstation has a Fore System
It has an ems TCA-100 ATM network interface and is connected to the "TURBOchannel" I / O bus, and the two workstations are connected back to back, not via an ATM switch. DECSt
ation 5000 / 240s is 40MHz MI
PS R3000 processor and 64K bytes, direct mapped off-chip instructions
It has an AND data cache and 32MB of main memory. The main memory and I / O subsystem are equipped with a 32-bit word TURBO channel and operate at 25 MHz. Fore TCA-100
Is a very simple interface with two FIFO queues, one for the transmit FIFO and the other for the receive FIFO, and some control and status registers. There are 14 32 ATM cells
It is sent to the TCA-100 interface over the TURBO channel by a processor that creates data in bit words. ATM cells have an expression format of 5
It has an ATM header of bytes, an ATM payroll of 48 bytes and padding of 3 bytes. 14 ATM cells
Is received by a processor that reads the data in thirty-two bit words. The TURBO channel supports DMA, but TCA-100 does not use DMA. When a cell arrives, the TCA-100 will generate a TURBO channel interrupt. Or the receive cell counter of the TCA-100 is polled to determine if a cell has arrived. The data rate of the fiber connecting the TCA-100 is 140 Mbps. DECStation is a Carnegie Mellon University (CMU) microkernel based operating system Mach 3.0 (MK83, U
X41) works. The source code of this operating system is CMU (Pittsburgh, P
Ennsylvania) is already available.

The simple remote write function was experimentally implemented on this system. The 32-byte block of transmission data is given at an arbitrary offset from the endpoint of the transmitting computer.
This 32-byte block of data is delivered to the end point specified by the sending computer of the receiving computer at the offset position given by the sending computer. Data, offset and buffer information can be put in one cell. Data block
Size is equal to cache block size 32
It is a byte, and the offset is restricted to match a 32-byte block for ease of implementation. At the sending computer, the low level Mach kernel exception handling code is modified to send cells by illegal instruction traps. At the receiving computer, the Mach microkernel is modified to partially optimize the interrupt path. Specifically, the TCA-100 handler is called directly from the kernel interrupt trap handler.

The following experiment was conducted using the above apparatus. From the user level, a block of data stored in advance in the workstation, which is the sending computer, is sent to the receiving computer. A user level process is kept running at the receiving computer and this user level program tests the arrival of data at the endpoint area. Once the data arrives at the receiving endpoint, the receiving process sends it back to the sending workstation. On this sending workstation, another user-level process is running,
Testing the arrival of data. In this way, the total round trip time was measured. This measurement result includes two one-way remote writes, loop overhead, and measurement overhead. The loop overhead includes the overhead because the round trip is repeated 20 times. The measurement result is shown in FIG.

The first row of FIG. 10 is the average time for cell transmission by illegal instruction trap send. The second line is the round trip send-receive time corrected for loop overhead and measurement overhead. The first column in FIG. 10 shows the time taken for the first iteration. The second column is the average of the next 19 repeat times. First two
After the repetitions, there were very few variations in the measurement results. The first iteration is a cache miss or translation lookaside buffer (TLB)
Contains mistakes. Therefore, the send-receive time at the first repetition takes much longer than the measurement result at the subsequent repetitions. (But it's not clear why the send-receive time took such a long time on the first iteration. The send overhead on the first iteration is more than expected.)
Eventually, cache miss, TLB miss, and other temporary factors disappeared, and round trip time was 49.1μ.
It became sec. This means the following: The one-way send-receive time for remote write is at best about 24.5 μsec. This is about 80 times faster than similar tests with Fore System's AAL3 / 4 running on Ultrax 4.3 on the same hardware.

FIG. 11 shows the bandwidth measurement result when continuous remote lights are transmitted. Block size is the number of consecutive remote lights. Bandwidth increases as block size increases. However, since the interrupt overhead is amortized with more data, the bandwidth increases asymptotically as the block size doubles or quadruples. The TCA-100 interrupt handler uses the receiving F of the receiving computer.
Read cells from the receive FIFO until the IFO is empty. Thus, if cells are sent in time, one interrupt is needed to read all cells. That is, one pass to the interrupt trap handler. Sending cells is fast because it uses the illegal instruction trap method, even when consecutive blocks are sent using a regular "for" loop. As a result, the interrupt overhead is immediately amortized with more data being amortized.
The asymptotically increasing bandwidth shown in FIG. 11 is a measure of the degree of overhead for each cell when processing the cell from the FIFO of the receiving computer.

The above-mentioned 24 Mbps in this embodiment.
The bandwidth is for 32 data bytes / cell. 44 data bytes / cell, approximately 48 Mb using AAL3 / 4 format, using the same hardware
The peak bandwidth of ps has been reported by others. This cell rate translates into a peak bandwidth of (48 Mbps / 44) × 32 = approximately 35 Mbps when using 32 data bytes / cell. The partially optimized single cell remote write of this example has a peak bandwidth of 24 Mb, which is obtained with 32 data bytes / cell.
This corresponds to ps / 35 Mbps = about 68%. Also, the 24 Mbps bandwidth obtained in this example is
Fore Sy with the same hardware running on 4.3
14 Mb measured using a system's AAL3 / 4
Much better than ps peak bandwidth.

FIG. 12 shows what kind of elements the delay time of 24 μsec is composed of. Since the TCA-100 ATM interface does not have DMA, all access to the interface for sending and receiving cells uses programmed I / O. Programmed I / O on the TURBO channel is slow. As a result, the delay time (7 μsec) in the TURBO channel is equal to the total delay time (24 μs).
Approximately one third of μsec) is spent. The ATM cell time (3 μsec) is the time required for the receiving computer connected to the fiber having the transfer rate of 140 Mbps to obtain the entire 53 bytes (1 cell). 24 μs
The remaining time (14 μsec) of ec is the CPU time and memory time of the sending computer and the receiving computer, which is 14 μsec / 24 μ of the total delay time.
sec = 58%. Therefore, optimizing the interrupt handler code by 20% to improve CPU time and memory time is a total delay time of 24 μs.
ec of about 3 μsec (14 μsec × 20% = 2.
8 μsec) only. From the above points, the minimum delay time for remote writing on commonly used hardware is approximately 20 μsec (24 μs).
It may be concluded that it is ec-3 μsec).

Looking at the results of these experiments, special purpose hardware should be used to reduce the load on the processor and reduce memory and I / O bus time. This special purpose hardware provides a protection mechanism as well as a mechanism for putting data directly into memory. This hardware support reduces the total delay time for ending a single cell time. The cell time is 2.7 μsec at a data rate of 155 Mbps and 0.68 μsec at a data rate of 622 Mbps. Reducing the processor load is also important for servers such as file servers in distributed systems with heavy communication loads. Changes in the delay time are also reduced, and the worst case delay time is improved. Such hardware implementing the network interface architecture according to the present invention will be described. Normally, a node acts as both a receiving computer and a sending computer, so the network interface for the node should handle both inbound and outbound functions. Receiving computer 272 functions include address mapping, protection mechanisms, address registers, data and address path control, and flow control. The function of the sending computer is described below.

The embodiment is divided into the following two parts. The first part is the front-end architecture for address mapping, address register control mechanism. This part can be implemented in several ways, all of which have the same function. FIG. 4 shows a general block diagram. The second part is the back end that connects the network interface and the host memory. This part can also be implemented in several ways. For example, three methods will be described below: direct connection to main memory, traditional I / O bus connect, and direct connection to secondary cache.

The front end architecture will be described with reference to FIG. 210 is a front end of the network interface. Front end 21
0 connects to the host memory 212 via the bus 214. The connection of the bus 214 to the host memory 212 is called the back end, which will be described in detail later. The reception side of the front end 210 comprises a reception buffer memory 216 with flow control. This receive buffer is preferably a first in first out (FIFO) memory. Header separation check unit 2
18 processes the input cells and stores the information in VCI / VP
It is decomposed into an I mapping unit 220, a control decoder 222 and a data separation check unit 224. The data separation check unit 224 passes the block of data to the block transfer unit 226. The block transfer unit 226 passes the data to the host memory via the bus 214. VCI / VPI mapping
Unit 220 determines the connection number. The connection number is used by the operation logic 230. The operation logic will be described later in more detail with reference to FIG.

The control decoder 222 decodes the control information of the input cell. The control information determines the index and the operand to be passed to the operation logic 230, respectively. The index and operand are the same as those shown for the ATM cell in FIG.
The control decoder 222 outputs the operation code in the ATM cell to the receive controller 228. Receive controller 228 provides operation logic 230 with control information. The operation logic 230 outputs an address, state information, a condition code, a connection number for response, and an interrupt. Addresses and interrupts go to the backend. The response connection number is passed to the VCI / VPI mapping unit 232 on the transmission side of the front end 210. Also, on the transmission side of the front end 210, there is a send controller 234. Send
Controller 234 receives information from the host processor via bus 214, provides control information to operation logic 230, and provides a connection number to VCI / VPI mapping unit 232. The send controller 234 uses the send register 2
36 is provided. The send register 236 provides the operation code, operand, and index information to the control encoder 238. The control encoder 238 writes these pieces of information in the corresponding fields of the ATM cell shown in FIG.

The block transfer unit 240 on the transmission side is
Data is transferred from the host memory to the data buffer 242. The cell forming unit 244 receives connection information, control information and data from the data buffer 242 and creates a cell with appropriate header information. The cell is sent to the transmit buffer and flow control 246. The transmit buffer and flow control 246
It is preferably a FIFO memory. Instead of receiving the message data from the data buffer 242,
It may be retrieved from a data register, which is one of the send registers 236. Receive controller 2
28, send controller 234 and operation
The remaining functional blocks other than the logic 230 are standard for network interfaces or have relatively simple functions. Therefore, the description of the remaining functional blocks is omitted.

The operation logic 230 of FIG. 4 will be described in more detail with reference to FIG. Latches between elements and control signals have been omitted for simplicity of illustration and illustration. The signal input from the left side of the figure is a signal coming from the data field of the ATM cell described with reference to FIG. For example,
Connection number is VC of ATM cell header
Obtained from I / VPI. Operation logic 230
Has a connection table 140. The operation logic 230 is the connection table 1
Cache all or part of 40. Also, the connection table 140 is stored by the operating system. For each connection, the connection table 140 has an entry 1
Hold 42. The entry 142 includes an endpoint number 146, address register information, connection state information 150, and a response connection 151. The address register information is the address register base 148 and the address register area 149. The use of these fields will be described in more detail below.

The endpoint table 160 is a cache of all or part of the above-mentioned endpoint table. The endpoint table 160 is maintained by the operating system. For each endpoint, this endpoint table 160 comprises an entry 162 indexed by endpoint number.
The entry 162 includes the endpoint base 164,
It consists of an endpoint area 166 and address mapping information 168. The address mapping information is for referencing the page map structure for the endpoint stored in host memory. This endpoint information is stored in a separate table so that multiple connections using the same endpoint can share the same information.

The operation logic 230 also includes an address register 170. The method of realizing the address register 170 can be selected from many methods. The address register 170 is preferably dedicated to each connection in order to avoid a plurality of activities competing for use of limited resources.
Any address in the endpoint can be used as a register corresponding to an indirect address. However, such generalization creates access speed issues and protection issues. The problem of access speed is shown below. Indirectly addressed messages require access to host memory on the first pass on the critical path to determine where to store the message, and second time on post-increment mode to store the updated index. Request access to host memory. Therefore, the access speed becomes slow. The problem of protection arises because the location specified by the indirect address can contain any address. By translating this address, the protection issue can be solved. However, two address translations are needed in the critical path. One is translation of an address indicating an indirect position, and the other is translation of an address to an indirect position. For these reasons, it is better to limit the indirect designation to the address register provided exclusively for each connection on the interface memory. By doing so, although it is inconvenient because a separate name space is required, it is possible to avoid access to the host memory on the critical path that occurs due to indirect designation. Each connection arranges registers in a number of contiguous locations as a register "window". For ease of use and flexibility, each connection can be dynamically assigned a window size at connection setup. Connection table entry 142
The base 148 and area 149 of the window point to the start and end of this window, respectively. According to such a specification, overlapping and nesting of register windows can be allowed. In this way, the register windows can be shared and protected differently.

When using the address register, a problem arises if the receiving computer wants to limit the access of the sending computer to certain address registers. An example of this is when the receiving computer does not want to allow the transmitting computer to directly increase or decrease the pointer to the queue. Therefore, the address register 170
Comprises a protection bit 144. Protection bit 144 indicates the type of access that the sending computer is allowed to access to the data in these registers. Protects the address register from these accesses such as read, write and indirect. When making an indirect access, the sending computer cannot determine the value of this information, but this information can be used by the sending computer. For example, an indirect address operation with post-increment, even if the sending computer is not allowed to read or write the register directly,
You can read the value of a register or increment the value of a register by a specified value. However, if the sending computer specifies an operation that involves accessing the address register in an unauthorized way,
There is an exception. The host processor can directly access the register at this time.

Because of the protection of the address registers, the receiving computer is allowed to restrict access to the sending computer, but nevertheless, when the sending computer specifies an operation, the sending computer has all operands. Can be specified. Thus, another protection problem arises because the receiving and sending computers are not completely independent. It is still possible for the sending computer to specify conflicting operands, for example, the priority of the operands and the priority queue do not match, or the wrong register is specified. In order to solve this problem, the operand name is made available only to the receiving computer, and the transmitting computer and the receiving computer are separated.

In order to separate the sending computer and the receiving computer in this way, the receiving computer
It is only necessary to find the operand of the receiving computer from the received operand and decode it, or execute the interrupt to the host processor. However, this causes additional overhead for the host processor, whether it is decoding the operands or performing the interrupt. The receiving computer side must be programmable control so that the operands can be used freely. The receiving computer is complicated by this, but a fairly simple embodiment will be described later. Indirection with post-increment is very often used, but in order to support this, the following special case is added to the above primitive operation. effaddr = <addreg _i >; addreg _i ← <addreg _i > + <addreg _{i + 1} > To use this special indirect addressing mode, the sender computer only needs to specify the index i in the operand. . The receiving computer uses the address register i for indirection and automatically uses the next address register i + 1 as a post-increment amount.

The connection table 140, the endpoint table 160 and the address register 170 are
It may be arranged in the memory of the network interface. The memory on this network interface is
Static Random Access Memory (SRA
M) or dynamic random access memory (DRAM). Conventional translation
The lookaside buffer (TLB) 180 is used to relocate the address specified in the message to the physical address (PA). The TLB is preferably a Fully Associative Cash. Since multiple endpoints may use the same virtual address (VA), the TLB finds the physical address by matching the endpoint's VA with the bits that specify the endpoint. The TLB also stores whether or not the physical address may be accessed.

Connection table 140, endpoint table 160, and address register 170
And the relationship between the TLB 180 will be described. connection·
The endpoint number 146 output from entry 142 of table 140 is used as an input to endpoint table 160. connection·
Base 148 and area information 149 from table 140
Are provided to the adder 156 and the comparator 158, respectively. The adder 156 also receives the index 128 (see FIG. 3) from the received ATM cell. The output from the adder 156 is also given to the comparator 158. Comparator 158 sends the appropriate address to address register 17
Acts as a filter for giving 0. If the comparator 158 determines that it is not appropriate, an error trap will occur.

The endpoint table 160 outputs the base 164 and the area 166 of the endpoint. The base 164 and the region 166 are connected to the adder 172 and the comparator 174, respectively. The adder 172 receives the received ATM cell from the operand field 126 (see FIG. 3).
See also). Multiplexer 1
76 receives the output of adder 172, the base 164 from endpoint table 160 and the offset from the received ATM cell. The output of the multiplexer 176 is an Arismetic Logic Unit (ALU)
178 is input. The value read from the address register 170 is also input to the ALU 178. ALU17
8 outputs the condition code and the result. This condition code is the receive controller 228
(See FIG. 4). In addition, the result from the ALU 178 is the demultiplexer 179 and the address register 1
Given to 70. Demultiplexer 179 receives the output from adder 172 as another input. The output of the demultiplexer 179 becomes another input of the comparator 174. The comparator 174 outputs an error or an address within the area that the endpoint can take. In the latter case, the address is input to TLB 180.

The receive controller 228 controls the multiplexer 176, the ALU 178, the demultiplexer 179, and the address register 170.
Used to control reading and writing of. At this time, the connection
State information from table 140 and received ATM
Control is performed according to the operation code / control information from the cell and the condition code from the ALU178. There are various methods for the functions supported by the receive controller 228 and how to realize these functions. If implemented with only the five basic addressing modes described above, this mode is so simple that it can be implemented with a hardware circuit using a finite state machine. FIG. 6 shows an implementation method using a table. The sender controller 234 can be implemented in a manner similar to the receive controller 228.

FIG. 6 is a diagram showing a case where the receive controller 228 is operated with a table inside. The condition code 184, the state 186, and the operation code 188 are input to the table 190. Condition code 184, state 186, opcode 1
88 is used as an index of the table 190. The output from the table 190 is the control signal 1
92, new state information 196, and mask 194. The control signal 192 is sent to the multiplexer 17
6, output to the demultiplexer 179, the ALU 178 and a latch (not shown). The use of these outputs will be described in further detail below. In FIG. 4, all of these outputs are represented together by the arrow labeled "Control" which is output from the receive controller 228 towards the operation logic 230.

Although not shown in FIG. 5, the connection table 140 and the endpoint table 1
60, an address register 170, and a data bus for returning data to the TLB 180. Therefore, the host processor can read and write the contents of these various tables. This allows the operating system to manage the contents of tables and TLBs, and allows applications to access the address registers. However, if the application directly accesses the address register,
Problems arise in terms of protection. The simplest way to solve this problem is to prohibit the application from accessing the address register directly and only allow the address register to be accessed by an operating system system call. But,
This solution comes at the cost of many access to address registers. Another way to solve the protection problem is to map the address registers into the virtual address space that the application has. That is, the address register of each connection is mapped to a different physical address area. By providing an additional circuit, the additional circuit extracts the connection number from this physical address, and the address register 170 is stored using the base 148 and the area 149 of the address register stored in the connection table 140. You will definitely be able to access the area. According to this solution, operating system system calls are only required to generate the mapping. Once the mapping is created, the application can access the address register using the address register base and area used in the received message.

In the above description, the endpoint base has been described as a virtual address, but it may be a physical address. If the endpoint base is a physical address then the mapping is simplified. That is, it is only necessary to check the area. However, this method has two drawbacks. The first drawback is that if the endpoint size is larger than the size of a page with a certain size, the endpoint will be placed across multiple physically contiguous pages. The second drawback is that the address register can store either a relative address or a physical address. In order to avoid these two drawbacks, it is necessary to use an endpoint base as a virtual address and perform mapping from this virtual address to a physical address. The first drawback mentioned above limits the use of host memory. In particular, it is not preferable when the size of the endpoint dynamically changes. The second drawback also means that the application cannot fully use the indirect address pointer. Alternatively, if the pointer is stored in the address register, it means that the operating system must be activated in order to map the pointer to the physical address.

Next, the function of the operation logic 230 will be described below. The connection number is the number extracted from the message. The connection number is used as an index of the connection table 140. A protection mechanism is provided to check whether the connection number is within the table size of the connection table. That is, the comparator 150 checks whether the connection number is proper.

The adder 156 adds the index value from the ATM cell and the address register base obtained from the connection table 140. Comparator 158
Compares the added value with the area 149 obtained from the connection table 140. If the added value is less than or equal to the area, the added value is sent as an address to the address register 170. If the added value is larger than the area, it is determined that there is an error, and the error trap processing is executed. In this way, the value stored in the address register is obtained from the address register, and the obtained value is sent to the ALU 178.

The endpoint number obtained from the connection table 140 is the endpoint table 1
Used to search the endpoint base 164 at 60. The endpoint base 164 is retrieved and then sent to the adder 172. The adder 172 is
Searched endpoint base 164 and received A
The offset value extracted from the TM cell is added. The added value is sent to the multiplexer 176 and the demultiplexer 179. The multiplexer includes an endpoint base 164, a value added by the adder 172, and A
The offset value extracted from the TM cell is input.
The multiplexer 176 is controlled to select one from these values and send it to the ALU 178. ALU
178 is controlled to perform an operation based on the value received from address register 170 and the output from the multiplexer. Multiplexer to ALU
The condition code and address are output to 178. The operations executed by the ALU 178 include operations relating to the contents of the address register, such as addition processing in the post-increment mode, logic operations, and comparison operations such as conditional interrupts. However, the operation of the ALU 178 is not limited to the above-mentioned operation. ALU 178 is used to perform various other operations regarding the contents of address registers. If the operations on conditional interrupts and address registers are not restricted to the address mode of not using the address registers, then the memory used for the address registers is preferably a multi-port memory. Alternatively, the memory used for the address register is the operation logic 230.
It is desirable to operate at a faster clock than the other parts in.

The processing result by the ALU 178 may be sent to the address register 170. The demultiplexer 179 is controlled to select either the added value of the adder 172 or the processing result of the ALU 178. The output from the demultiplexer 179 is compared by the comparator 174 with the region 166 retrieved from the endpoint table 160. This is part of the protection function.

The address output from the comparator 174 is T
It is output to the LB 180. The TLB 180 also has a protection function. It is checked whether the address output from the comparator 174 conforms to the TLB 180. If the address output from the comparator 174 does not match the entry of the TLB, the TL
When the B miss occurs, exception handling is requested to the operating system. This TLB miss occurs because the address mapping based on the address output from the comparator 174 does not exist in the TLB. Alternatively, this TLB miss is caused by not having the access right. Although processing the TLB miss as an exception processing by the host processor requires almost no hardware, the TL
There is a disadvantage that it interferes with the processing of arriving cells while the B miss exception processing is being executed. It is desirable that these arriving cells be limited in number or stored in a buffer when exception processing is performed. However, there are cases where they are discarded. As an alternative to handling TLB misses, the network interface may have hardware to handle TLB misses. Alternatively, the network interface may have a dedicated mapping for each endpoint in order to reduce TLB misses or eliminate TLB misses. When the network interface adds hardware, the processing becomes inflexible because it depends on the hardware. Also, despite processing with hardware,
Since the mapping information has to be accessed from the host memory, a delay occurs, which causes a delay in cell processing. On the other hand, the method of having a dedicated mapping for each endpoint allows one or two mapping entries for each endpoint.
This is possible if the endpoint table is extended. However, such expansion causes an increase in memory space and a decrease in performance.

The receive controller 228 decodes the opcode 129. Further, the receive controller 228 determines the action to be performed on the arrived ATM cell by using the condition code output from the ALU 178 and the state information 150 output from the connection table 140. The control signal output by the receive controller 228 is determined by the operation code and the condition code. These control signals are used to activate the desired addressing mode. It is also used to store data. Mask 19 shown in FIG.
The output of 4 is used to select which element of the data is actually stored in the memory of the receiving computer. For example, the mask selects data in units of 4 bytes. The mask requires 4 bits for a 32-byte data block,
As shown in FIG. 3, the mask 131 can be obtained directly from the 4 bits assigned to the opcode mask.

The state information 150 of the connection table 140 is used for a multiple cell message in which the message is composed of a plurality of cells.
The state information 150 records connection addressing information for these plural cells. The first cell when a multiple cell message is received is called the control cell. This control cell contains information for selecting the addressing mode. Also,
The offset and index are specified. The information of this control cell is stored in the state information 150 of the connection table 140. Subsequent cells included in the same multiple cell message need not include these control information and can carry more data. For example, the first cell can have 32 bytes of data while the subsequent cells can have 48 bytes of data. This is the case with the AAL5 format. Subsequent cells use the control information stored in the state information 150 of the connection table 140. The end of this multiple cell message can be identified by storing the cell count in the state information 150. Alternatively, the standardized AAL5 format can be used to identify the final cell. According to the AAL5 format, the last cell of the multiple cell message is supposed to transmit the length and the CRC, so that it is possible to determine the last cell by identifying these. All received cells are checked by whether the CRC of the finally received cell is correct. Assuming that the multiple cell message ends with CRC, [2/3 (N-1)] + 2 cells are used to transmit N (N> 1) blocks with 32 bytes as one block. Become. By using this method, it becomes possible to send data in approximately 2/3 of the number of cells as compared with the case of sending one block in which one block is 32 bytes in one cell.

Various functions can be added in addition to the functions described above. The addition of this function is done by the addition of an opcode interpreted by the receive controller 228.

Processing of error traps reported to the operating system is done by discarding cells. Alternatively, it is done by adding the cell to the error queue and requesting exception handling from the operating system.

Up to now, the reception side of the front end has been described, but the transmission side of the front end will be described below. Control information and data must be prepared in order to transmit a cell. Control information can be obtained from the set of send registers 236. Each connection has a set of send registers 236 for transmitting cells. The first three registers of this set of send registers 236 store control information. That is, the operation code, operand, and index stored in the cell are stored. On the other hand, data for transmission is obtained from the endpoint associated with the connection. Alternatively, the data for transmission can be obtained from a special block in the send register. If the data comes from a special block of send registers, it is very convenient in forming a read request.

The send register provided for each connection includes a status register, a mode register and a go register. The status register stores the number of cells transmitted. If the value of the status register has been initialized to 1 beforehand, its value is set to 0 when the network interface actually sends the cell. As described above, when the status register is used, it is convenient because it can be used as confirmation that the cell to which the status register is to be transmitted has actually been transmitted by leaving the network interface. This is because cells are not always delivered immediately due to flow control and exception handling. On the other hand, the mode register has two functions as described later. Further, the go register is a register used for actually transmitting the cell, as described later.

As mentioned above, various options are possible for each part of the front end. Several different embodiments will now be described below. The configuration of the first front end is a case where minimum hardware is used as shown in FIG. The operation of the address register is limited to reading and writing at most one address register for one cell. Also, the endpoint page is bound to physical memory and has a buffer. Remote reads are processed by the host processor via interrupts. The operation of the address register described above is limited to one address register, which means that all operations that can be performed on the address register are performed on the same address register. Binary operations also mean getting one argument from the message operands. In this way, the post increment value for the indirect addressing operation is specified by the message. In such a state, it cannot be said that the state of the receiving computer is completely independent from the state of the transmitting computer.
Therefore, as an alternative, it may be possible to configure a desired function with continuous messages. For example, the post-increment value may be specified by addition to the register specified in the subsequent message.
The fact that the page of the endpoint is limited by the physical memory described above prevents the size of the endpoint from increasing, and also reduces the size of the endpoint, resulting in many endpoints. It prevents that. Therefore, limiting the size of the endpoint by physical memory helps simplify the structure.

The receiving side of this embodiment has the above-mentioned configuration. This example is characterized in that the page of the endpoint is specified by the physical memory, so that the endpoint table 160 stores the physical address as the endpoint base. Since the physical pages are not always arranged continuously, the TLB 180 is used for conversion from the physical page to the physical address. The TLB 180 stores a mapping for converting an address in a cache. The TLB 180 converts the value described as VA in FIG. 5 into a corresponding physical address. This VA is a value obtained by adding the endpoint base address and the offset. In this example, the endpoint base address points to the page of endpoints. If the size of the endpoint is one page or less, the physical address stored in the TLB 180 may be directly stored in the entry 162 of the endpoint base 164 of the endpoint table 160. In this way, when the physical address is stored in the endpoint base 164, the direct mapping bit is added to all the entries 162 of the endpoint table. By using this direct mapping bit, it is possible to determine whether or not the physical address is directly described in the endpoint base 164, and the endpoint base can be correctly interpreted. If the size of the endpoint is larger than the size of one page, the endpoint
Adding a mapping entry to the table allows handling larger sized endpoints.

The operation of the transmitting side will be described below. The endpoint for sending is limited by the page size. Each connection has its own unique virtual mapped command area in order to allow transmission for a particular connection without calling the kernel. This command area is provided at a position apart from the virtual page used for the endpoint by a predetermined offset. For example,
Of the bits indicating the virtual address, the higher order bit can be used as the offset value. The size of this command area is the same as the size of the endpoint. These command areas are mapped to the network interface without being cached. The send register 236 described above is mapped to a page below the base of this command area.

In order to transmit one block of data, which is separated from the base of the endpoint on the transmission side by an offset, to the network using the connection C, a write operation is executed. This write operation is performed for locations that are the same offset away from the base of the command area for connection C. The value written by the write operation in this case is ignored. The lower bits of the physical address indicate the physical address of the data block of the transmitting end point. Alternatively, as described later, the lower bit may indicate an offset. The upper bits of the physical address mean the connection number. The transmit controller extracts the control information from 236 into the send register for that connection. Also,
Read a block of data to make up a cell. Alternatively, the data may be obtained from a special block of send register 236.

Some host processors do not have a sufficient number of bits to indicate both the physical address of the data block and the connection number. Alternatively, some host processors may not have a sufficient number of bits to indicate the address used by the send controller 234. In such a system, the following two plans can be considered. The first alternative is to replace the physical address of the data block with an offset from the endpoint base. When the physical address is thus replaced with the offset from the base of the endpoint, the send controller 234 must be configured to make the base address of the endpoint accessible. In addition, it is desirable to continuously arrange the physical pages of the endpoints.

The second method is to shift the cell address of the data block to the right. The simplest way is to shift right by 5 bits. 3 data blocks
Since 2 bytes can be accessed as one unit, the lower 5 bits of the physical address are not used.
This is premised on the case where the computer carries out addressing in byte units. By shifting to the right by 5 bits in this way, a margin of 5 bits is created. By using the free 5 bits, it becomes possible to display the connection number and the address used by the transmission controller 234. However, this shift to the right has the following drawbacks. Since the page offset is not changed even by the virtual memory mapping, the virtual address where the command area of the endpoint is stored and the physical address where the data block is stored are linked by the following restrictions. The upper 5 bits indicating the offset of the virtual page of the command area of the endpoint correspond to the lower 5 bits of the physical page storing the data block. Such restrictions have the following consequences. First, the size of the endpoint command area is smaller than the endpoint and is a multiple of 32 bytes. In this way, the command area is mapped to the base address of one data block. Each block of 32 consecutive pages in the endpoint can thus have similar memory protection. Second, the endpoint size is a multiple of 32 pages. This drawback is
It does not matter as long as the send controller 234 can access the endpoint base and its size. Third, the endpoint is mapped into a contiguous chunk of 32 pages allocated in the 32 page memory area.

The mode register in the send register has two functions for transmitting cells. First of all, the operand is obtained from the value actually written in the command area prepared for the connection. Secondly, when the status value is a value other than 0, exception processing occurs when an attempt is made to transmit. In this embodiment, the go register is not used and will not be described.

The state information 150 stored in the connection table 140 is not updated until the operation is completed. Completion of this operation is determined by the absence of a TLB miss that could result in the last exception handling. For example, the write processing to the address register is regarded as completed when it is determined that the TLB miss does not occur, and the state information 150
Will be updated. Cell is a FIF provided for input
It is temporarily stored in O. Once the cells originating from the connection have been stored in the FIFO, they are stored in the FIFO until needed by the post processor. FI
The cells stored in the FO go through the last exception handling as described above, and when the processing is committed, the FIFO
Taken from.

Next, the second embodiment will be described below. In this second embodiment, the three restrictions mentioned in the first embodiment are removed. That is, in the second embodiment, (1) the endpoint is not restricted by the page unit. (2) Remote read does not require interrupt processing by the host processor. (3) The operation related to the address register can be performed more freely.
In order to prevent the endpoint of (1) above from being affected by the page size, the endpoint table 16
0 stores a virtual address. The TLB also maps virtual addresses to physical addresses. This improvement creates new problems. That is, a page fault may occur that refers to a page other than the assigned page as the endpoint page. Due to the occurrence of this page fault, exception handling different from the past must be provided. And these page faults must be handled by the host processor. The host processor manages a virtual mapping table, and this virtual mapping table performs exception handling of page faults. In this embodiment, the operating system is responsible for maintaining the memory mapping information. This mapping information should be compatible with the memory state of the host processor.

Further, the address mapping for the read data must be calculated in order to process the remote read without using the interrupt processing of the host processor of the above (2). To do this calculation, a receiving computer with mapping function is used. That is, when a cell requesting remote read is transmitted, the address is calculated using its own mapping function in order to calculate the address of the data to be read. Therefore, the operation logic 23
0 must perform both receiver and sender functions. In this example, the operation
Logic 230 is used for all transmissions, not just for transmitting requests by remote reads. As a result, in this embodiment, there is no need to use the virtually mapped command area used for protection. However, in this embodiment, virtually mapped send registers are required.
The offset value is written into the go register in order to transmit the data block located at a position offset by the offset value from the sender's endpoint base. By writing the offset to the go register, the data indicated by the offset is read and transmitted as cell data. 32 data blocks
The bytes are arranged as one unit, and the offset is used to read one data block in the byte. The read data, together with the control information, form a cell and are output. The control information is stored in the operation code register, operand register and index register. It is also possible to specify the multiple send mode. By setting the number of cells in the status register, the specified number of cells can be continuously transmitted from the specified offset.

In this embodiment, three basic operations can be executed for each message as a more free operation than the case of the above (3). The three basic operations are address generation, register operation, and condition setting. Opcodes control the selection and ordering of these basic operations. Examples of opcodes are read, multiple read, write, multiple write, and software exception handling. The software exception process is a process that causes an interrupt to the host processor. In the instruction used in this embodiment, three registers can be designated as operands in addition to the operands directly designated. All register operations are performed at three times the clock speed to allow all multiple accesses to the address register 170. Like this 3
By performing the register operation using the double clock speed, there is a drawback in that the method of returning the state when exception processing occurs becomes more complicated.

There are cases where it is desired to have more flexible functions than the control functions and cell processing functions provided by the first and second embodiments. For example, a locking operation or a swap and compare operation may be desired. Alternatively, for some applications, the cell handling protocol may be customized. Flexibility depends on being free to program. And flexibility is always a trade-off between complexity and cost. One way to increase flexibility over the two embodiments described above is to make the receive controller 228 and send controller 234 writable. A second method of increasing flexibility is to process cells with a programmable finite state machine. The receive controller 228 and the send
As a method for making the controller 234 writable,
The following can be considered. The first word following the header of the ATM cell is used as the index. This index is used as an index of the control memory inside the receive controller and the send controller. This control memory is writable, and the control memory stores information for interpreting the remaining fields of the cell. Further, all control signals are set in this control memory. This control memory has a processing function of cells connected by hardware. Alternatively, it has a programmable cell processing function. These functions perform processing depending on the connection and can have various kinds of cell processing functions. Alternatively, a microprocessor may be used from the viewpoint of providing flexibility.

From such a viewpoint, in the third embodiment, an example using a commonly used microprocessor will be described. This microprocessor is for controlling the entire processing of the front end, and is preferably a coprocessor for communication, for example. By using a microprocessor, the hardware can be simplified. This is because all the control logic inside the microprocessor can be used, and the TLB of the microprocessor itself can be used as it is as the above-mentioned TLB 180. The endpoint number may be expressed by using the upper bits of the virtual address. Also, the use of a microprocessor allows for fully programmable cell processing and cell control.

According to this third embodiment, 155 Mbp
It provides sufficient flexibility even at speeds of s, but may not be available for microprocessors in all cases. If you have to handle high-level operations, it makes sense to use a microprocessor. For example, using a microprocessor is very effective in relieving the host processor from read operations. Even when such a microprocessor is used, using an address generation connected by hardware or a mapping circuit connected by hardware is effective in reducing the load on the microprocessor.

Next, the fourth embodiment will be described. Fourth
Embodiment uses a programmable cell interpreter. That is, the fourth embodiment shows a mixed case of the hardware control described in the first and second embodiments and the microprocessor control described in the third embodiment. Complex decoding and complex operations are handled by either the host processor or coprocessor. In this fourth embodiment, the various functions are preferably provided by a programmable gate array. This programmable gate array executes various functions in cooperation with a DRAM that stores various tables. The functions provided by the coprocessor to the front end may be included in the functions provided by the programmable gate array. Since the gate array includes the function performed by the coprocessor, the load on the coprocessor can be reduced. Reducing the coprocessor load in this way is very important both in terms of efficiency and flexibility when dealing with high data rates such as 622 Mbps or 1.2 Gbps.

In the above-described first to fourth embodiments, the pipeline processing is performed as much as possible to achieve higher efficiency. However, 1
When using a data rate of 55 Mbps, the data arrival interval is about 50 nsec. This 50 ns
The ec interval is a sufficient time to complete the address setting and control. When performing pipeline processing, it may occur that memory is accessed hierarchically. In that case, in order to satisfy the access time for hierarchically accessing the memory, it may be necessary to temporarily store one word or the corresponding data in the buffer. When using a data rate of 622 Mbps, the pipeline processing need only be performed in a few stages.

The several embodiments described above describe embodiments of the front end 210. This front end is the bus 214 of the network interface.
(Also called the back end). The back end bus 214 is for connecting the front end to the memory of the host processor. As examples of the back end bus 214, three examples will be described below.

As a first embodiment, it is conceivable that the front end described above is directly connected to the main memory bus. A cache controller is prepared,
The cache controller monitors the main memory bus to maintain cache coherency. As a second embodiment, it is possible to use a general-purpose bus interface. The method of connecting the front end directly to the main memory bus shown in the first embodiment is attractive in terms of performance, but it is an option. In this embodiment, a general-purpose bus such as a PCI bus is used to connect the front ends. By using such a general-purpose bus interface, this system can be adapted to a more open market. The disadvantage of using a general purpose bus, such as the PCI bus, is that it introduces delay.
This delay occurs to gain control of the bus. Contention with other devices connected to the general-purpose bus occurs, and a delay occurs to take control of the bus. Due to such a delay, data may need to be buffered in some cases. Buffering the data may increase the delay even further.

As a third embodiment of the back end bus, an interface directly connected to the cache memory can be considered. This method does not require modification of the processor. In this embodiment, the network connects directly to a cache external to the processor. By connecting the network directly to the cache, the work of copying the message data can be eliminated. In order to prevent network caches from unnecessarily weakening the function of this cache and, consequently, reducing the performance of the processors connected to that cache, FIG. As shown, a separate message cache 252 may be provided and this message cache may be connected to the network.

In FIG. 7, the message cache 2
52 via the bus 256 to the microprocessor 250
It is connected to the. The message cache 252 is connected to the data cache 254 and the main memory (or host memory, not shown) via the bus 258. Mapping unit 260 connects message cache 252 to the network via bus 262.

The message cache 252 is constructed as a part of a hierarchical memory. That is, the message cache 252 exists in the same layer as the data cache 254, and exists between another layer called the main memory and the microprocessor 250.
The message cache 252 is the data cache 254
Bus 256 and bus 258 exist in the same layer as
It is clear that both exist during the period. Therefore, once the data is written to the message cache, it is not necessary to copy the data from the message cache to the memory in another layer. In other words, by writing data in the message buffer,
The process can access the data. The interface to the message cache 252 can be achieved by diverting the interface of the data cache prepared in advance. Thus, there is no development expense, no special purpose modifications or changes are required, and no processor customization is required. For example, if the block size of the cache is 32 bytes, each block of the cache is automatically updated for each block by adding a restriction that the size of the message is equal to the block size of the cache. You have good cache access. That is, by making the message size equal to the cache block size, the complicated and slow process of updating a part of the cache block can be eliminated.

A problem in using the interface for directly accessing the cache shown in FIG. 7 is how to reduce the overhead when the consistency between the message cache 252 and the data cache 254 is maintained. In order to solve this problem, the writing process to the message cache 252 is performed only from the network. By allowing writing only from the network in this way, the cache 25
Consistency issues between 2 and 254 are reduced. Each time there is a write to the message cache 252, it checks the corresponding block in the data cache 254 and invalidates that block. This check is performed by the message cache 252 and the data cache 254.
Is performed by using the matching tags provided in each. The adverse effect caused by checking the data cache 254 is the data cache 25
It is minimized by checking the shadow copy of the 4 cache tag. For details on the interface to access the cache directly,
It is described in "Low Latency Network Interface" (Randy Osbourne), filed with the United States Patent Office on Nov. 16, 1993.

Various modifications and variations can be made to the various embodiments of the network interface described above. For example, the above-mentioned exception handling and flow control may be executed in the front end. Exception handling includes error traps, protection violations,
Raised by unscheduled operations, TLB misses and page faults. This exception handling delays the processing of cells in the system. And the flow of cells
It adversely affects control. Also, cell processing may be interrupted to ensure atomicity when the host processor accesses the system memory. Especially in the exception handling, when an error trap occurs, this problem can be completely eliminated by immediately discarding the abnormal cell. Alternatively, the problem can be solved by putting the abnormal cell in the queue for exception processing. The cells queued for exception handling are examined by the operating system at any time. The method of discarding an abnormal cell in this way is not used for exception processing other than the error trap. This is because even if the abnormal cell is discarded, a message for retry is sent from the sending computer. When a message for retry is sent in this way, the faulty situation must be repaired before the next process is performed. During the repair work, the arriving cells are either discarded or temporarily stored in a buffer. Alternatively, it limits the arrival of cells.

The above case applies to cells belonging to a failed connection. For other cells belonging to the connection in which no failure has occurred, the status of the failure is saved and then the processing is continued immediately. Cells belonging to the failed connection are not processed. Even if the failure does not affect the cell, it is not processed. For example,
Even if the newly arriving cell itself does not cause a TLB miss or page fault, those subsequent new cells are not processed. This is because the arrival order of ATM cells may have to be guaranteed depending on the application. The guarantee of the arrival order is performed for each channel. This channel is the one established in the connection in this system. Therefore, there is no problem in continuing the processing of the cell belonging to the failed endpoint and the other connection connected to the same endpoint. However, there is a possibility that these cells will cause new failures.

Measures for dealing with exception processing will be described below. First of all, you need to remove the offending cell from the front end as soon as possible. The cell that causes the error trap can be discarded or queued. Other problematic cells are temporarily stored in the input FIFO. The failed connection is marked as the failed connection. Then, for the connection in which the problem occurs, the flow control that suppresses cell transmission is activated for the transmitting computer that is transmitting the cell. By the time flow control is up, cells arriving at the failed connection are temporarily stored in a buffer. On the other hand, the other connections that have not failed continue to process cells normally. When an error trap occurs, only the above-mentioned cell discard process is performed. In the case of other exceptional processing in which the system is temporarily suspended due to the access processing by the host processor, data transmission suppression and buffering are performed for all connections. The data transmission suppressing process and the buffering process are both equivalent processes from the viewpoint of performing cell flow control.

When the size of the TLB becomes very large, hybrid address mapping may be used. This hybrid address mapping refers to a case where mapping is performed using both the endpoint table 160 and the TLB 180. Each endpoint-based entry 162 of the endpoint table 160 is made to store one or two mappings and the TLB is stored the remaining mappings. The concept of this hybrid address mapping is a general extension of the one described in the first embodiment of the front end.
In the first example of the front end, in order to obtain the page of the endpoint directly from the endpoint base 164 of the endpoint table 160 when the page size of the endpoint is less than or equal to one page size. The case where the mapping of is stored is explained. This hybrid address mapping is a concept that combines both such a concept and the concept using TLB. The mapping process of the endpoint base 164 of the end table 160 may be performed by an application. When the application does the mapping, it can always store the mapping that is likely to be used by the application soon.

The connection table 140 and the endpoint table 160 may be localized. If you have many connections, and many endpoints,
The sizes of the table 140 and the endpoint table 160 are increased. One way to reduce the size of a table is to achieve locality by paging out entries from the table. In the case where a page fault occurs by accessing the table having the thus achieved locality, the network interface removes the cell having the page fault from the processing pipeline and temporarily stores it in the buffer. . Then, for the connection in which the page fault has occurred, flow control of the arriving cell is performed. The host processor pages the table and restores the state. Then, processing of the cell of the connection in which the page fault has occurred is restarted.

Also, some configurations may be added to provide appropriate access to the network and to prevent network deadlock.
By adding such a structure, it is possible to prevent a plurality of processes from interfering with each other. When multiple processes are executed, the network is blocked or the network is congested. In the worst case, deadlock may occur.
The newly added configuration is to prevent these failures. Further, in order to keep the access to the network fair, permission control for permitting the access may be performed. This admission control limits the period during which one connection can send data to the network when another connection is pending operation. That is, this admission control prevents the generation of traffic for which flow control is not performed. From the viewpoint of performance, it is possible to give priority to the traffic of the operating system. In order to prevent deadlock, several steps as described above are required. First of all, each connection must have independent flow control. Normal standardized A
When using a TM network or a standardized interface, independent flow control can be performed for each VCI / VPI. Secondly, when an exceptional process that interrupts the process of all cells occurs, the period of the exceptional process must be limited. Third, the cells requesting a reply from the network must be removed. Do not output cells requesting a reply, even if the response connection is flow controlled. The cell requesting this reply can be removed by providing a connection for transmitting the reply and providing a buffer for each connection for this reply. This is done, for example, by preparing a flow-controlled buffer for each connection for reply and assigning a separate VCI / VPI to each cell. Also, the admission control for the transmission should have a higher priority for the traffic of the reply transmission than for the new transmission.

In order for the operating system itself to always be able to continue processing, it should have a connection for itself. Access to pages used by the operating system should be performed on a page-by-page basis, regardless of the type of page. A page used by the operating system stores a connection table, an endpoint table, and address registers. This information is not stored across pages. This is because if the data is stored across pages, a delay occurs due to the access processing across the pages.

A global address register may be used in the front end. In the various embodiments described above, the address register 170 is a private one provided for each connection. When the address register is provided for each connection as described above, it is inconvenient when a plurality of connections are connected to the same end point and a plurality of connections use a common queue. As a method to solve such inconvenience,
A global address register commonly used for the endpoint is provided. This global address register is not assigned for each connection. The endpoint table 160 outputs the endpoint base and area to the global address register. The global address register can be created in the same memory as the local address register.

The fragmentation of the buffer may be performed in the front end. In the case of multiple cell messages, matching a 48-byte payload with ATM AAL5 to a power-of-two size memory and matching a 48-byte payload to the size of a cache block can cause buffer fragmentation problems. Cause If 32 bytes make one block, 1
6-byte fragmentation can be used. Both the sending and receiving computers can use fragmentation buffers to partition or combine data into blocks of 32 bytes. This size can be anything depending on the size of the memory and cache block. However, supporting the already existing segmentation and reassembly on the standard ATM interface seems to be the most effective way.

The addresses of the sending computer and the receiving computer may not match the memory block and the cache block. Assuming the sending and receiving computers have the same alignment, the sending computer will send the aligned blocks and the receiving computer will mask and remove the unwanted parts. Thus, the removal of unnecessary data does not lead to effective use of cells. However, data transmission due to misalignment is rare. Another possible performance flaw is that under some architectures, sub-block addressing is prohibited. In that case, the entire block must be read, masked, and selectively written to the sub-block. Such mask operation or scatter operation is performed by the receiving computer. Alternatively, the transmitting computer may perform masking. If the sending computer performs a masking process, the process is optional unless it has a gather function. It is very effective in terms of security to prevent the data of a certain field from being output to the network. But,
Such processing has no merit in terms of efficiency.

In some cases, the address to be transmitted may not match in terms of the boundary of the block and the address of the receiving computer. In such a case, the problem can be dealt with by performing masking and shifting. An alignment shifter should be prepared to solve this problem.

The front end may use the prefetch queue. Fetching data in advance is effective in preventing delay. The system described above already supports prefetch queues. To provide full prefetch, a processor capable of using prefetch should be used. For example DE
Use a processor such as C alpha. Further, in order to perform prefetching, hardware for decoding a prefetch request from a processor and actually performing a fetch based on the request must be prepared. It is difficult to mount such prefetch hardware in an interface using a general-purpose bus. But it is not impossible, as was done by Cray Tera 3D. In such cases,
The design will be such that the network interface is directly connected to the data bus. The return address of the fetch is simply stored at the back of the queue if some way is set up to trigger execution of the fetch. If the queue storing the return address is not empty, normal interrupt processing can be used to notify that the return address remains in the queue.

Further, in an application,
It may be desirable to maintain a high degree of independence between the sending and receiving computers. In the method of directly sending a message to the receiving computer as described above, the sending computer writes an instruction and an operand in the message. The operands written in this message may be directly referenced values. Or it may be a reference to a state stored in the receiving computer (stored in an address register). The receiving computer executes the instructions written in the message. As mentioned above, the restricted access to the address register can maintain some protection and independence. However, that independence is, for some applications,
It may not be enough. Because the sending computer cannot access the operands, it must specify all of the operands. One method for solving the problem of wanting to secure the independence is to generate an interrupt to the host processor when the action requiring the independence is executed. By thus generating an interrupt to the host processor of the receiving computer, the independence of the transmitting computer and the receiving computer is established, and an addressing system based on the receiving computer can be created.

Another way to solve this independence problem is to
The instruction specified in the message is replaced by the pointer of the instruction stored in the receiving computer. That is, the message does not indicate the operation but records the instruction pointer prepared in the receiving computer. As described above, since the instruction to be actually executed is prepared on the receiving computer side, the instruction may directly refer to the operand on the receiving computer side that the transmitting computer side does not recognize. For example, the instruction of the receiving computer may refer to a field inside the address register which the transmitting computer does not recognize as an operand. Further, the message may store the operand directly executed, or may specify the operand of the receiving computer. However, the receiving computer does not have to use the operands specified in these messages. In this way, the independence of the receiving computer can be maintained.

An embodiment in the case of adopting the solution method using the above-mentioned instruction pointer will be described with reference to FIG. The feature of FIG. 9 is that a connection table 142, a pointer base 300 for instruction pointers, and an area 302 indicating the area of instruction pointers are provided. In addition, the instruction memory 304 is provided. The instruction pointer base 300 indicates the base address of the instruction memory 304, and the area 302 indicates the size of the instruction memory 304. To simplify the design, each instruction is composed of an operation and an operand, and the size of each instruction has a format exactly the same as the format used for the ATM cell as described above. The operation controls whether the operand should be obtained from the instruction memory 304 of the receiving computer or from the message. Instruction memory 3
04 has a protection bit. The protection bit is the protection bit 14 in the address register 170.
Works the same as 4. That is, the protection bits of the instruction memory 304 are used to determine which instruction is designated by the sending computer.

In the system as described above, the following three improvements can be considered. As the first improvement point, global instruction can be considered. It is possible that many connections commonly use the same operation. However, in that case,
Often use different operands. Under such circumstances, it is possible to add something called global instruction. This global instruction is an instruction that can be accessed from all connections. Global instructions allow the sending computer to operate only on the supplied operands. It would be confusing if the receiving computer were to be able to work with certain operands.

The second improvement is to have separate instruction and operand memories. If you want to separate instruction and operand memory,
It can save the memory capacity to be used, but has a drawback that the operation is complicated.

The third improvement is to provide a multiple instruction for executing a plurality of instructions for each cell. In this case, a sequencer must be provided so that multiple instructions can be executed for each cell. The first instruction of such a sequenced multiple instruction is treated as the entry point.

It is also conceivable to add conditional operations, subroutines, and the like. However, in order to keep the interface simple, more complex functions are desired to be achieved by interrupting the host processor or by adding a coprocessor such as a microprocessor.

The above-described embodiments are embodiments of the present invention, and modifications and variations to these embodiments are possible.
These modifications and variations are included in the scope of the present invention as long as they can be easily performed by those skilled in the art.

Here, the final summary of the present invention is as follows. Network protocols and interfaces using direct deposit messaging provide a low overhead communication system in a network of multi-user computers. In this system, information from both the sending and receiving computers is used to process the received message and store the data and control information directly. That is, the data is stored in the memory, and the host processor is conditionally / optionally interrupted by the control information.
Message processing is divided into passing data that does not require processing by the host processor and the operating system, and message actions that require or do not require host processor interaction. In this protocol, the message contains an indication of the operation desired by the sending computer,
The operand specified by the sending computer,
It includes an operand that refers to the information that the receiving computer has. The receiving computer checks if the action requested by the sending computer can be performed, and if so, according to the operands specified by the sending computer and the state of the receiving computer,
Take action. If the action is message passing, the operands in the message specify values for various addressing modes such as direct, indirect, post-increment, and index mode. If the action is a conditionally generated interrupt, the operand determines whether the message requires an immediate action, taking into account the state of the receiving computer. Actions may also be operations on network interface registers. It may also be an operation with other information stored by the receiving computer. The network interfaces and protocols of this invention can be used in local area networks. This interface and protocol are especially asynchronous transfer method (ATM)
It is suitable for the network. The network interface of the present invention includes an overlapping or nesting endpoint, an address register created by the overlapping or nesting window,
An address register protection mechanism and an integrated exception handling and flow control are provided.

[0212]

As described above, according to the present invention, the message sent from the sending computer can be processed without the intervention of the processor of the receiving computer and the operation.
Since it can be stored in the memory of the receiving computer, an efficient communication system with little overhead can be obtained.

According to the present invention, the message can be directly stored in the memory of the receiving computer by designating the memory address of the receiving computer as the operand of the message.

Further, according to the present invention, the message can be directly stored in the address indicated by the address register by storing the address register of the receiving computer in the operand of the message.

According to the present invention, by indicating the offset in the operand, the address of the address register can be modified with the offset, and the message can be directly stored in the modified address.

Further, according to the present invention, it is possible to immediately process a message which requires urgency.

Further, according to the present invention, the information of the receiving computer can be updated by the transmitting computer.

Further, according to the present invention, non-urgent messages can be queued and processed at any time.

Further, according to the present invention, by designating the address register and the offset from the sending side computer, the receiving side computer modifies the address stored in the address register by the offset, and then the memory is stored in the memory. Can store messages.

Further, according to the communication system of the present invention, if the receiving computer is permitted to execute the received message, the receiving computer receives the operand described in the received message. And processing based on the information stored in the receiving computer. In this way, processing with a protection function can be performed.

According to the present invention, by designating the address in the operand, the message can be directly stored in the address designated by the operand.

According to the present invention, by storing the address register of the receiving computer in the operand of the message, the message can be directly stored in the address indicated by the address register.

Further, according to the present invention, by indicating the offset in the operand, the address of the address register can be modified with the offset, and the message can be directly stored in the modified address.

Further, according to the present invention, it is possible to immediately process a message that requires urgency.

According to the present invention, the information of the receiving computer can be updated by the transmitting computer.

Further, according to the present invention, non-urgent messages can be queued and processed at any time.

Further, according to the present invention, by designating the address register and the offset from the transmitting side computer, the receiving side computer modifies the address stored in the address register with the offset, and then the memory is stored in the memory. Can store messages.

Further, according to the communication method of the present invention, when the receiving computer is permitted to execute the received message, the receiving computer receives the operand described in the message. And processing based on the information stored in the receiving computer. In this way, processing with a protection function can be performed.

Further, according to the present invention, the message sent from the sending computer can be stored in the memory of the receiving computer without going through the processing of the processor of the receiving computer and the operation, and the efficiency with less overhead can be achieved. It is possible to obtain a good communication method.

According to the present invention, the message can be directly stored in the memory of the receiving computer by designating the memory address of the receiving computer in the operand of the message.

Further, according to the present invention, the message can be directly stored in the address indicated by the address register by storing the address register of the receiving computer in the operand of the message.

Further, according to the present invention, by indicating the offset in the operand, the address of the address register can be modified with the offset, and the message can be directly stored in the modified address. Further, according to the present invention, it is possible to immediately process a message that requires urgency.

Further, according to the present invention, the information of the receiving computer can be updated by the transmitting computer.

Further, according to the present invention, non-urgent messages can be queued and processed at any time.

According to the present invention, by designating the address register and the offset from the sending computer, the receiving computer modifies the address stored in the address register with the offset, and then the message is stored in the memory. Can be stored.

Further, according to the communication system of the present invention, when the receiving computer is permitted to execute the received message, the receiving computer receives the operand described in the message. And processing based on the information stored in the receiving computer. In this way, processing with a protection function can be performed. Further, according to the present invention, the message can be directly stored in the memory assigned to the application program. If the message is urgent, it will be executed immediately by interrupt handling. In this way, a communication system with less overhead can be obtained.

Further, according to the present invention, since unauthorized access is denied, it is possible to provide a system to which a protection function is added.

Further, according to the present invention, the information of the receiving computer can be changed from the transmitting computer.

Further, according to the network interface of the present invention, a message can be directly stored in the memory allocated to the application program. If the received message is urgent, it is immediately executed by interrupt processing. In this way, a system with low overhead can be provided.

Further, according to the present invention, since unauthorized access is denied, it is possible to provide a system having a protection function.

Further, according to the present invention, the information stored in the receiving computer can be changed from the transmitting computer side.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication system using direct deposit messaging according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing flow of the communication system of FIG. 1 according to the embodiment of the present invention.

FIG. 3 is a 53-byte A according to an embodiment of the present invention.
The block diagram showing the suitable format of TM cell.

FIG. 4 is a block diagram of the network interface shown in FIG. 1 according to an embodiment of the present invention.

5 is a block diagram for explaining a protection mechanism and address generation in the operation logic on the receiving side shown in FIG. 4 in an embodiment of the present invention.

FIG. 6 is a block diagram for explaining the receive controller shown in FIG. 4 in an embodiment of the present invention.

FIG. 7 is a block diagram of a direct cache interface according to an embodiment of the present invention.

FIG. 8 is a flowchart showing the flow of processing for starting endpoint-and-connection-based communication in an embodiment of the present invention.

FIG. 9 is a block diagram showing another implementation method of the operation logic on the receiving side in the embodiment of the present invention.

FIG. 10 is a diagram showing a measurement result of a remote write delay time tested in an embodiment of the present invention.

FIG. 11 is a diagram showing the measurement result of the bandwidth obtained when transmitting the continuous remote light that was tested in the embodiment of the present invention.

FIG. 12 is a diagram showing a breakdown of delay time according to the embodiment of the present invention.

FIG. 13 is a block diagram of a communication system using receiver-based addressing in a conventional example.

FIG. 14 is a flowchart showing a processing flow of the communication system of FIG. 13 in the conventional example.

FIG. 15 is a block diagram of a communication system using sender-based addressing in a conventional example.

16 is a flowchart showing a processing flow of the communication system of FIG. 15 in the conventional example.

[Explanation of symbols]

50, 87, 270 Transmitting computer, 52, 8
8,272 receiving computer, 54,70 processor (host processor), 56,72,91,92,
278,280 operating system, 58,7
8 Application 1, 60, 80 Application 2, 62, 64, 74, 76 Message buffer,
66, 68, 79, 81 Endpoint (Endpoint buffer), 67, 95, 101 Send command, 77 Receive command, 82 Network, 8
3,94,290 messages, 84,86,89,9
0,274,276 network interface, 9
7,98 Protection mechanism, 282, 284, 286, 288
Connection state information and mapping information, 12
0 cell, 121, 123, 125, 128 index field, 122 data field, 12
4-cycle redundancy check (CRC) field, 126 operand field, 129
Opcode field, 130 operation field, 131 mask field, 132 AT
M header field, 140 connection table, 142 (connection table) entry,
144 protection bits, 146 endpoint numbers, 148 address register base,
149 address register area, 150 connection state information, 151 response connection, 15
2, 158, 174 Comparator, 156, 172 Adder, 160 Endpoint Table, 162 (Endpoint) Entry, 164 Endpoint Base, 166 Endpoint Area, 168 Address Mapping Information, 170 Address Register, 17
6 multiplexers, 178 Arismetic Logic Units (ALUs), 179 demultiplexers, 180 translation lookaside buffers (TLBs), 184 condition codes, 1
86 states, 188 opcodes, 190 tables, 192 control signals, 194 masks, 19
6 new states, 210 front end, 212 host memory, 214 bus, 216 receive buffer and flow control, 218 header separation check unit, 220,232 VCI / VPI mapping unit, 222 control decoder, 224 data separation check unit Unit, 226,240 Block Transfer Unit, 228 Receive Controller, 2
30 operation logic, 234 send controller, 236 send register, 238 control encoder, 242 data buffer, 244
Cell forming unit, 246 transmit buffer and flow control, 250 microprocessor, 252 message cache, 254 data cache, 256, 258, 262 bus, 260 mapping unit, 300 pointer base, 302
Area, 304 instruction memory.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04L 12/00 12/28 29/08 H04L 13/00 307 Z

Claims (30)

[Claims] 1. A communication system of a computer system, wherein a sender computer and a receiver computer are connected by a network, and the receiver computer has a network interface connected to a processor controlled by an operating system. A sending means for sending to the receiving computer a message containing an operand, an identifier of the action to be performed, and a reference to information stored in the receiving computer; and receiving the message at the network interface. Receiving means and means for operating in the network interface by receiving the message, and determining whether or not the receiving computer is allowed to execute the action. Means for operating in the network interface when the action is permitted to be performed, the operand of the message being stored in the receiving computer separately from the processor of the receiving computer and the operating system. A communication system comprising an executing means for executing an operation based on the information and executing the action according to the operation. 2. The operand indicates an address of a memory of the receiving computer, and the executing means stores the memory of the receiving computer based on the address of the message and the information stored in the receiving computer. 2. The communication system according to claim 1, further comprising a message storing means for storing the message at a predetermined position. 3. The operand is an address register in a network interface that stores an address of a memory of a receiving computer, and the information stored in the receiving computer is an address stored in the address register. 3. The communication system according to claim 2, further comprising means for obtaining an address from an address register indicated by an operand, and means for storing a message in a memory based on the obtained address. Communication method. 4. The communication system according to claim 3, wherein the operand further indicates an offset, and the communication system further comprises means for modifying the address of the address register by the offset. . 5. The executing means compares the operand and the information stored in the receiving computer, and the comparing result of the comparing means determines that the message requires immediate execution. 2. The communication system according to claim 1, further comprising interrupt means for generating an interrupt to the processor. 6. The communication system according to claim 5, further comprising update means for updating the information stored in the receiving computer. 7. The communication method further comprises queuing means for queuing a message in a queue when it is determined that the message does not require immediate execution according to the result of the comparison by the comparing means. The communication system according to claim 5, characterized in that. 8. The operand is provided in a network interface for storing an address of a memory of a receiving computer while indicating an offset,
The information stored in the receiving computer is an address stored in the address register, and the communication method further includes means for obtaining the address from the address register indicated by the operand. 6. The communication system according to claim 5, further comprising means for storing a message in a memory based on a value indicated by an offset from the address. 9. A processor requesting transmission of a message, a processor connected to the processor, and based on a request from the processor, an operand, an instruction of a desired action, and a reference to information stored in a receiving computer. A sender computer having a network interface for creating a message including a message, a processor controlled by an operating system, a receiver computer having a network interface connected to the processor, a sender computer network interface and a receiver computer And a network for converting messages between the sending computer and the receiving computer, the network interface of the receiving computer being connected. When receiving a message and performing the action indicated in the message, the action is based on the operand and the information stored in the receiving computer when the receiving computer is allowed to perform the action. A communication method characterized by executing. 10. The operand indicates an address in the memory of the receiving computer, and the action is based on the address contained in the message and the information stored in the receiving computer. The communication system according to claim 9, wherein the message is stored in a predetermined position of the memory. 11. The operand is an address register that stores an address of a memory of the receiving computer, and the information stored in the receiving computer is the address stored in the address register. 11. The communication system according to claim 10, further comprising means for obtaining an address from the address register indicated by the operand, and means for storing a message in the memory based on the obtained address. 12. The communication system according to claim 11, wherein the operand further indicates an offset, and the communication system further comprises means for modifying the address stored in the address register with the offset. . 13. The receiving computer determines that the message requires an immediate action based on the comparison result obtained by comparing the operand and the state managed by the receiving computer and the comparison result obtained by the comparing device. 10. The communication system according to claim 9, further comprising an interrupting unit that generates an interrupt when the communication is performed. 14. The communication system according to claim 13, wherein the communication system further comprises update means for updating information stored in the receiving computer. 15. The communication method further comprises queuing means for queuing the message in a queue when it is determined from the comparison result of the comparing means that the message does not require an immediate action. 14. The communication method according to claim 13, wherein: 16. The operand represents an offset and an address register provided in a network interface for storing an address of a memory of a receiving computer, and the information stored in the receiving computer is: An address stored in an address register, the communication method further includes means for obtaining an address from the address register indicated by the operand, and means for storing a message in the memory based on a value indicated by an offset from the obtained address. The communication system according to claim 13, further comprising: 17. A communication method of a computer system, wherein a sender computer and a receiver computer are connected by a network, and the receiver computer has a network interface connected to a processor controlled by an operating system. Sending a message containing an operand, an instruction of an action to be performed, and a reference to information stored in the receiving computer from the computer to the receiving computer via the network; and receiving the message at the receiving computer. The receiving step, the confirming step of confirming whether the action requested by the transmitting computer is permitted in the receiving computer, and the case where the action is judged to be executable by the above confirming step. In this case, the communication method is characterized in that the processor and the operating system are separately provided with an execution step of executing an action in the receiving computer based on the operand of the message and the information stored in the receiving computer. 18. The operand indicates an address of a memory of the receiving computer, and the executing step determines a predetermined memory of the receiving computer based on the address of the message and the information stored in the receiving computer. 18. The communication method according to claim 17, further comprising a message storing step of storing a message at a position. 19. The operand is an address register in a network interface that stores an address of a memory of a receiving computer, and the information stored in the receiving computer is an address stored in the address register. 19. The communication method further comprises the steps of obtaining an address from an address register indicated by an operand and storing a message in a memory based on the obtained address. Communication method. 20. The communication method according to claim 19, wherein the operand further indicates an offset, and the communication method further comprises the step of modifying the address of the address register with the offset. . 21. The executing step comprises a comparing step of comparing operands and information stored in a receiving computer, and a processor, if the result of the comparing step indicates that the message requires immediate execution. 18. The communication method according to claim 17, further comprising an interrupt process for generating an interrupt. 22. The communication method according to claim 21, further comprising an updating step of updating the information stored in the receiving computer. 23. The communication method further comprises a queuing step of queuing a message in a queue if the message resulting from the comparing step does not require immediate execution. The communication method according to claim 21. 24. The operand indicates an offset and an address register provided in a network interface for storing the address of the memory of the receiving computer, and the information stored in the receiving computer is: An address stored in an address register, the communication method further comprising: obtaining an address from an address register indicated by an operand; and storing a message in a memory based on a value indicated by an offset from the obtained address. 22. The communication method according to claim 21, further comprising: 25. A network communication system of multi-user computers, comprising a sending computer and a receiving computer, the receiving computer having a processor and a memory, part of the memory being executed by the processor. In the communication method assigned to the application program, the sending computer sends a message including the operand, the reference of the information stored in the receiving computer, and the data to be delivered to the application program to the receiving computer via the network. And a means for operating in the receiving computer to receive the message, which is a predetermined position in the memory allocated to the application program, and the predetermined position is The message data is directly stored in a predetermined position that is independent of the storage position of the data of the message received before the message and is determined by the state of the sending computer and the information stored in the receiving computer. Direct storing means and means for operating in the receiving computer by receiving the above message, and conditionally generating an interrupt to the processor based on the state of the transmitting computer and the information stored in the receiving computer. A communication method comprising an interrupting means for enabling 26. The communication method further comprises, at the receiving computer, accessing the information stored in the receiving computer when the transmitting computer is not permitted to access the information. 26. The communication system according to claim 25, further comprising means for preventing the above. 27. The communication system further comprises means for operating in the receiving computer by receiving the message, and means for changing information stored in the receiving computer based on the state of the transmitting computer. The communication system according to claim 25, further comprising: 28. A network communication system of multi-user computers, comprising a sending computer and a receiving computer, the receiving computer having a processor and a memory, part of said memory being executed by said processor. Is assigned to an application program to be stored in the network, and the transmission side computer sends a message including a operand indicating a state of the transmission side computer, a reference to information stored in the reception side computer, and data to be passed to the application program. In the network interface for transmitting to the receiving computer via the, the receiving computer is a means that operates by receiving the message, and is a memo assigned to the application program. , The predetermined position is independent of the storage position of the data of the message received before the message, and the state of the sending computer and the information stored in the receiving computer. A direct storage means for directly storing the data of the message in a predetermined position determined by the predetermined position determined independently of the position used for storing the message received before the message; , Means for operating upon receipt of the message, which comprises an interrupting means for conditionally generating an interrupt to the processor based on the state of the sending computer and the information stored in the receiving computer. A characteristic network interface. 29. The network interface further comprises: if the sending computer is not authorized to access the information by the receiving computer,
29. Means for preventing access to information stored in a receiving computer.
The listed network interface. 30. The network interface comprises:
29. The network interface according to claim 28, further comprising means for operating upon receipt of the message, the means including means for changing information stored in the receiving computer based on the state of the transmitting computer.