JPH08186976A - Driver of power semiconductor element - Google Patents

Abstract

PURPOSE: To improve ununiformity in sharing of a transitional current by changing a control voltage or a control current of a control gate terminal depending on a current flowing into a snubber circuit means during the period that the control voltage or control current is supplied to or removed from the control gate terminal. CONSTITUTION: When it is assumed that a current flowing into Q4 is divided into a current flowing into Le8 and a current flowing into Lc2 and Le4 when Q2 and Q4 have started to turn off, a current flowing into Lc2 and Le4 generates an induced voltage at the both ends of Lc2 with its di/dt. This induced voltage becomes a voltage difference between gates and emitters of Q2 and Q4 and thereby the current flowing into Q2 and Q4 becomes ununiform. In this case, the current flowing into Q2 and Q4 starts to reduce and a gate resistance becomes large immediately after a current flows into the snubber circuit to control variation of current di/dt of Q2 and Q4. With this control, an induced voltage of Lc2 is lowered. Thereby, a voltage between the gate and emitter of Q2 and Q4 becomes almost equal and ununiformity of current sharing by Q2 and Q4 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for driving a power semiconductor element, and more particularly to a power semiconductor element driving apparatus having first and second terminals for inputting / outputting a main current and a control gate terminal. .

[0002]

2. Description of the Related Art Insulated gate bipolar transistors (hereinafter referred to as IGBTs) have been widely used in high frequency inverter devices and power supplies in recent years. Further, in the future, it is expected that a MOS gate thyristor will be put into practical use in which an insulated gate structure is added to the thyristor, and a gate voltage is applied or removed to allow or prevent the current flowing through the thyristor to flow. These power semiconductor elements are characterized by a high switching speed and a small switching loss at turn-on and turn-off. However, high-speed switching requires a current change di / dt and a voltage change d.
This means that V / dt is large, and there are problems caused by these. At turn-off, the spike voltage generated when the current commutates to the snubber circuit increases, and transient non-uniform current sharing may occur when multiple power semiconductor devices are connected in parallel and driven. Can be mentioned. Further, at the time of turn-on, there is a problem that the current sharing becomes nonuniform when the current rises, and the recovery current when the diode recovers becomes large. Like this di / d
As a method for improving the problem caused by the large t and dV / dt, it has been studied to suppress the di / dt and dV / dt by relaxing the application or removal of the voltage to the gate terminal during switching. As an example, JP-A-5-33673
No. 2 describes a method of changing the gate resistance by detecting the collector voltage when turning off the IGBT. In the IGBT, the maximum value of the current that can flow with respect to the gate voltage (this is called the saturation current) is determined, and the decrease rate of the current can be slowed by slowly decreasing the gate voltage. Further, the drive circuit for removing the voltage of the gate is configured to discharge the electric charge charged in the gate capacitance inside the IGBT by the series circuit including the switch element and the resistor. When the resistance is increased, the gate voltage is reduced. It is possible to delay. In the above-mentioned known example, when the collector voltage is a predetermined value or more, the resistance of the drive circuit is increased to suppress the subsequent di / dt and dV / dt. In addition, as a similar publicly known example, an actual Kaihei 6-2439
No. 3 describes a method of detecting an output current of an inverter in an inverter circuit using an IGBT and varying a resistance in a gate drive circuit.

[0003]

Taking the case where the load is inductive such as a motor as an example, when the IGBT is turned off,
First, the collector voltage increases and reaches the voltage value of the main power supply, and then the collector current flowing through the IGBT decreases and the cutoff state is reached. In the method of the above-mentioned JP-A-5-336732, the resistance of the drive circuit is increased when the collector voltage is equal to or higher than a predetermined value, and dV / dt related to the increase of the collector voltage is increased.
Then, both di / dt when the current decreases thereafter can be made gentle, but on the other hand, the loss determined by the product of the collector voltage applied to the IGBT and the current flowing through the element becomes large. In the method of Japanese Utility Model Laid-Open No. 6-24393, the resistance in the gate drive circuit is changed according to the output current of the inverter, so that the gate resistance can be increased only when the output current is large. However, even in this case, both the voltage applied to the IGBT and the current flowing through the element change slowly, so that the switching loss increases.
Further, in any of the above-mentioned known examples, the electromagnetic energy accumulated in the inductance existing in the wiring connecting the main power source and the power semiconductor element is consumed as the loss (heat energy) of the element, so that the spike voltage at the time of current interruption or Reduces energy such as waveform vibration. This electromagnetic energy is proportional to the square of the current, and di / dt and dV / dt cannot be sufficiently suppressed unless the switching loss of the power semiconductor element is significantly increased as the current increases. However, there is a problem that a large increase in switching loss causes the cooling structure of the element to become large in size and cost, and also reduces the efficiency of the device. In this way, suppressing di / dt and dV / dt at the time of switching causes a result of simultaneously increasing switching loss. Therefore, it is desirable to reduce the increase in loss to the minimum and improve the unevenness of the sharing of the spike voltage and the current, which are problems, but none of the above-mentioned known examples describes such a driving method.

An object of the present invention is to suppress di / dt at the time of switching of a power semiconductor element to minimize increase in loss, reduce spike voltage caused by di / dt, and transiently increase. It is to improve non-uniformity of current sharing.

[0005]

The above object is to provide a power semiconductor device having first and second terminals for inputting / outputting a main current and a control gate terminal, and a control voltage or a control voltage applied to the control gate terminal according to an input signal. A power semiconductor device driving apparatus, comprising a drive circuit means for supplying or removing a control current, for passing or shutting off a main current, which is the first power semiconductor device.
A snubber circuit means is provided between the control gate terminal and the second terminal, and the control voltage or control current of the control gate terminal is changed according to the current flowing through the snubber circuit means during a period of supplying or removing the control voltage or control current to the control gate terminal. It is achieved by

[0006]

In the driving device for the power semiconductor element, by providing the snubber circuit means between the first and second terminals, the voltage applied to the power semiconductor element at the time of switching and its dV / dt are reduced, and at the same time as the main power source, The snubber circuit absorbs the electromagnetic energy accumulated in the wiring inductance between the power semiconductor elements. However, when only the snubber circuit means is provided, when the power semiconductor element is turned off or turned on, the change (d) in the current flowing through the element is changed.
i / dt) is not suppressed, and when the current is commutated to the snubber circuit, the inductance of the snubber circuit wiring and the above di / d
In addition to the spike voltage generated by t, when a plurality of power semiconductor elements are connected in parallel, there still remains a problem of excessive current sharing caused by di / dt.
Therefore, in the present invention, by detecting the current flowing through the snubber circuit, the control voltage or control current of the power semiconductor element is changed from the time when the current flowing through the power semiconductor element decreases or increases, and It suppresses di / dt during the decreasing or increasing period. This suppression suppresses an increase in switching loss to a necessary minimum, reduces spike voltage, and improves excessive non-uniformity of current sharing when power semiconductor elements are connected in parallel.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a power semiconductor device driving apparatus according to an embodiment of the present invention. In FIG. 1, Q1, Q
Reference numerals 2, Q3 and Q4 are IGBTs, each of which has a collector terminal for inputting a current, an emitter terminal for outputting a current, and a gate terminal for applying a control voltage. Q1 and Q2 are connected in series to form a half bridge of an inverter. Q1,
Diodes D1 and D2 are respectively connected in antiparallel to Q2, and a load current is circulated when Q1 or Q2 is turned off. Further, in this embodiment, Q3 and Q4 are connected in parallel to Q1 and Q2, respectively, and an inverter in which two output stage elements are connected in parallel is shown. Similarly, diodes D3 and D4 are connected in antiparallel to Q3 and Q4. Q1
And Q3, Q2 and Q4 have their gate terminals and collector terminals connected in common, and Q1 and Q3, Q4.
The emitter terminals of 2 and Q4 are inductances Lc1 and Lc
2 are connected by a wiring. Next, VE is a main power source, and the output stage element of the inverter is connected to the positive and negative electrodes of VE by a wiring having inductances L1 and L2.
An output terminal is taken out from the connection point of Q1 and Q2, and the load 3 is connected to this terminal. Although not shown in FIG. 1, it is assumed that the main power supply VE and the load 3 are connected by some circuit means so that the current can be supplied from the output terminal to the load 3. Further, Le1 to Le8 are respectively I
The GBT module represents the inductance inside the package. Each of Q1 and Q2 is provided with a snubber circuit. When Q1 is taken as an example, a diode DS1 and a capacitor CS1 are connected in series between the collector terminal and the emitter terminal of Q1 by a wiring having inductances L3 and L4. Here, Ls1 is the parasitic inductance of the capacitor CS1. A resistor Rs1 is placed between both terminals of DS1.
And serves as a current path when CS1 is discharged. Q2
The same applies to the case where the diode DS2 and the capacitor CS2 between the collector terminal and the emitter terminal of Q2 and the parasitic inductance Ls2 are the inductances L4 and L5.
Are connected in series with a wiring having a resistance Rs2 between both terminals of DS2. The above is the configuration of a general inverter and snubber, and in this embodiment, since it is intended to improve the unevenness of the spike voltage and the current distribution at the time of switching, regarding the inductance of the wiring that is not normally displayed on the circuit diagram, Also, in particular, the parts that are related to the above purpose are shown in the figure.

Next, drive circuit means for varying the gate voltage, which is a feature of the present invention, will be described. Since the gate drive circuits of Q1 and Q2 have the same configuration, the drive circuit of Q2 will be described here. First, Vc1 and Vc2 are provided as control power supplies, and switch means S4 and S3 and resistance means Rg3 are connected in series between the gate terminals of Q2 and Q4 and the positive electrode of Vc1, and resistance means Rg4 is connected to S3.
Are connected in parallel. Further, switch means S1 and S2 and resistance means Rg1 are connected in series between the gate terminals of Q2 and Q4 and the negative electrode of Vc2, and resistance means Rg2 is connected in parallel to S1. S4 is a command Sig of the control means 2.
2 turns on when Q2 and Q4 are turned on, and S2 turns on when Q2 and Q4 are turned off by the command Sig2 of the control means 2. Switching means 1
Controls ON / OFF of S1 and S3 according to the command Sig2 of the control means 2 and the output of the snubber current detection means. Here, in the present embodiment, the snubber current detecting means is L5.
A resistance Rd is provided at both ends of the snubber wiring having the inductance of
1 and Rd2 are connected in series, and the output voltage is taken out from the connection point of both. Regarding Q1, resistors Rd3 and Rd4 are connected in series at both ends of a snubber wire having an inductance of L4, and an output voltage is taken out from the connection point of both. According to this configuration, when Q2 cuts off the current at the time of turn-off and the current for charging CS2 of the snubber circuit flows due to the electromagnetic energy accumulated in the main circuit wirings L1 and L2, the emitter terminal of Q2 is supplied with the reference potential when the current rises. The output voltage (voltage of Rd2) that is defined as a positive voltage is generated.
When Q2 is turned on, a current is passed therethrough, and when a current for discharging the charge stored in CS2 is started to flow, the output voltage becomes a negative voltage at the rising edge. The switching means 1 is
When Q2 and Q4 are turned off by the command Sig2 of the control means 2, after the off command Sig2 is input, if the output (voltage of Rd2) of the snubber current detection means is positive and equal to or more than a predetermined value, S1 Is turned off, and conversely, when it is a predetermined value or less or a negative voltage, S1 is turned on. Also, Q2
To turn on Q4, turn on command Sig2
If the output of the snubber current detecting means (voltage of Rd2) is negative and its absolute value is equal to or more than a predetermined value after
3 is turned off, and conversely, if it is less than a predetermined value or a positive voltage, S3 is turned on.

FIG. 2 shows a detailed structure of the switching means 1. In FIG. 2, the command Sig2 output by the control means 2
Is inputted to the gate terminals of the switch means S2, S4, and this signal is a low level voltage when turning on Q2 and a high level voltage when turning off Q2. The above signals are also input to the AND circuit 4 and the OR circuit 5 represented by logic symbols. and
The other input signal of the circuit is the output of the comparing means 6-1. The comparing means 6-1 compares the output of the above-mentioned snubber current detecting means (voltage of Rd2) with the value of the positive predetermined value voltage 7-1. If the output voltage of the snubber current detecting means is high, a low level voltage is output, and conversely, if the output voltage is low, a high level voltage is output. With this configuration, when the output of the snubber current detection means is equal to or less than a positive predetermined value when Q2 is off, all the inputs of the and circuit 4 are at the high level, and the outputs of the and circuit are also at the high level.
Is turned on. Further, when Q2 is on or when the output of the snubber current detecting means is a positive predetermined value or more, the output of the and circuit is at a low level, and this output causes the switching means S1.
Keep off. Similarly, the other input signal to the or circuit is the output of the comparing means 6-2, and the comparing means 6-2 outputs the output of the snubber current detecting means (the voltage of Rd2) and the negative predetermined value voltage 7-. When the voltage of Rd2 is negative and the absolute value thereof is larger than the absolute value of the predetermined value 7-2, a high level voltage is output, and when the absolute value is small, a low level voltage is output. To do. As a result, when the output of the snubber current detecting means is equal to or greater than a negative predetermined value when Q2 is on, the or circuit
Input is low level, the output of the or circuit also becomes low level, and the switch means S3 is turned on by this output. Further, when Q2 is off or when the output of the snubber current detecting means is less than a predetermined negative value, the output of the or circuit is at high level, and this output keeps the switch means S3 in the off state.

Next, FIG. 3 shows operation waveforms of the embodiment shown in FIG. The operation principle regarding suppression of di / dt by changing the gate voltage after detection of the snubber current, suppression of spike voltage, and uniformization of dynamic current sharing will be described with reference to FIG. FIG. 3 shows the voltage V between the collector and emitter of Q2.
current Ic flowing through ce and Q2, snubber capacitor CS2
Current Is flowing through the output voltage of the snubber current detection means (R
(d2 voltage) and the relationship between the gate resistance at the time of off and the gate resistance at the time of on. First, at the time of turn-off, S1 is turned on according to the command Sig2 of the control means 2, and when the current Ic of Q2 starts to decrease, the current is commutated to the snubber circuit by the electromagnetic energy accumulated in the main circuit wirings L1 and L2, Snubber current begins to flow. At this time, the change in the current flowing through the snubber circuit (d
i / dt), a positive voltage is generated across the inductance L5, and the voltage divided by Rd1 and Rd2 becomes the detection voltage of Rd2. If the detected voltage is equal to or higher than the predetermined value 7-1, S1 is turned off by the function of the switching means 1, and the gate resistances connecting the capacitor between the gate and emitter terminals of Q2 and the control power supply Vc2 are Rg1 and Rg.
It becomes the value of the sum of 2. If the resistance value of Rg2 is sufficiently larger than that of Rg1, the time constant with which the voltage charged in the capacitor between the gate and emitter terminals decreases decreases, and the gate voltage of Q2 decreases slowly. As a result, Ic gradually decreases as shown in the drawing from the time when it starts to decrease, and the decrease in Ic is suppressed by di / d.
t becomes small. Since the suppression of di / dt is performed only during the current falling period tf, the increase in switching loss can be suppressed to the necessary minimum. Further, in the process of decreasing Ic, a spike voltage Vcsp having an absolute value of the product of the di / dt and the total inductance (L4 + Ls2 + L5) of the snubber circuit is generated, but by suppressing the di / dt, the spike voltage Vcsp is generated. Is also reduced as shown. Suppression of di / dt continues until Ic is completely blocked. After that, the electromagnetic energy of L1 and L2 is changed to C
The snubber current Is flows until it is absorbed by S2, and the voltage of CS2, that is, the voltage Vce between the collector and emitter of Q2 reaches a value exceeding the voltage of the main power source VE by ΔV. With the disappearance of the snubber current Is, Vce of Q2 returns to the normal voltage of the main power supply VE. On the other hand, di / dt of the snubber current Is is I
Since the voltage becomes gentle after c is cut off, the detection voltage (voltage of Rd2) of the snubber current detecting means sharply decreases and eventually becomes a negative value. In this case, S1 is turned on by the operation of the switching means 1, the gate resistance value returns to the low resistance of only Rg1, and the gate and emitter thereof are short-circuited with a low impedance so that Q2 is not erroneously ignited by external noise or the like. To do.

Next, it will be described that the current sharing of Q2 and Q4 connected in parallel in FIG. 1 is made uniform at the time of turn-off by suppressing the above di / dt. There are two possible causes of uneven current sharing in parallel: 1) the difference in the characteristics of Q2 and Q4, and 2) the induced voltage of the wiring connecting Q2 and Q4 makes the gate voltages of both non-uniform. However, the present invention addresses the excessive factor 2). That is, in FIG. 1, when Q2 and Q4 start to turn off at the same time, the current flowing through Q4 is equal to the current passing through Le8 and Lc.
2 and Le4, assuming that the current is shunted, Lc
The current flowing through 2 and Le4 depends on its di / dt
An induced voltage is generated across c2. This induced voltage is
The difference between the gate and emitter voltages of Q2 and Q4 is Q2.
And the current flowing through Q4 becomes non-uniform. In such a case, in the present embodiment, the current flowing through Q2 and Q4 begins to decrease, and immediately after the current commutates to the snubber circuit, the gate resistance is increased as described above to increase the current change di between Q2 and Q4.
/ dt is suppressed. This suppression reduces the induced voltage of Lc2. For this reason, the gate-emitter voltages of Q2 and Q4 become substantially equal, and the non-uniform current sharing of Q2 and Q4 is prevented.

Next, the turn-on time will be described. At the time of turn-on, S4 is turned on according to the command Sig2 of the control means 2, and starts charging the voltage between the gate and emitter of Q2,
When the value exceeds the threshold value, the current Ic starts to flow. At this time, the charges accumulated in CS2 are Rs2 and Q2.
It is discharged through Q4, and its discharge current is Q together with Ic.
2, the sum of the two becomes the maximum value Icp. A negative voltage is generated across the inductance L5 according to the current change (di / dt) at this time, and the detection voltage of Rd2 also becomes a value proportional to the negative voltage. If the absolute value of this voltage is equal to or greater than the predetermined value 7-2, S3 is turned off by the action of the switching means 1, and the gate resistances connecting the capacitor between the gate and emitter terminals of Q2 and the control power supply Vc1 are Rg3 and Rg.
It becomes the value of the sum of 4. If the resistance value of Rg4 is sufficiently larger than that of Rg3, the time constant of the voltage for charging the gate-emitter terminal capacitor increases, and the gate voltage of Q2 slowly increases. As a result, Ic gradually increases as shown in the figure from the time when it starts to increase, and di / dt related to the increase of Ic becomes smaller. Since the suppression of di / dt is performed only during the current rising period tr, the increase in switching loss can be suppressed to the necessary minimum. Even at turn-on, as described above, Q
Although the current sharing between the two and Q4 becomes non-uniform due to the influence of the induced voltage of the wiring connecting them, in the present embodiment, di / dt is suppressed and the induced voltage of Lc2 is reduced, so that Q2 and Q2 are reduced.
It is possible to prevent nonuniformity of the current sharing of No. 4. The suppression of di / dt is continued until the voltage (absolute value) of Rd2 becomes equal to or lower than the predetermined value 7-2. After that, S3 is turned on by the operation of the switching means 1, the gate resistance value returns to the low resistance of only Rg3, and the gate and emitter of Q2 and Vc1 are short-circuited with low impedance.

As described above, in this embodiment, by detecting the current flowing through the snubber circuit, the control voltage or control of the power semiconductor element is started from the time when the current flowing through the power semiconductor element decreases or increases. The current is changed to suppress di / dt during the period when the current decreases or increases. By this suppression, it is possible to suppress an increase in switching loss to a necessary minimum, reduce spike voltage, and improve non-uniformity of current sharing when power semiconductor elements are connected in parallel. Also, di / dt at turn-on
The suppression of (1) has the effect of improving the non-uniformity of current sharing and reducing snubber loss by reducing the electromagnetic energy of the main circuit wirings L1, L2. During the off period, the current of the load 3 flows back through the diodes D1 and D3 of the upper arm, and carriers are accumulated inside D1 and D3. Then, when Q2 and Q4 are turned on, accumulated carriers of D1 and D3 are released, and a recovery current flows. When the recovery current component is represented by Ir, the current flowing through L1 and L2 is I
It will be reduced by the value of r. As a result, the electromagnetic energy 1/2 (L1 + L2) Ir ² accumulated in L1 and L2 is released and absorbed in the snubber circuit. However, the recovery current Ir has a characteristic that the smaller the di / dt is, the smaller the Ir becomes. Therefore, when the di / dt suppression of the present embodiment is used, Ir is reduced.
Can be reduced, and the electromagnetic energy can be reduced. This energy is the snubber circuit capacitor CS1.
After being absorbed by, the resistance Rs1 becomes heat, so that according to the present embodiment, snubber loss can be reduced.

FIG. 4 is a block diagram showing another embodiment of the present invention. In FIG. 4, the same as in the embodiment of FIG.
Q1 and Q2 form a half bridge of the inverter.
The configuration in which Q1 and Q2, and the diodes D1 and D2 are connected to the positive and negative electrodes of the main power source VE by the wiring having the inductances L1 and L2 is the same as that in FIG.
Le4 is also an IGBT module and represents the inductance inside the package. The configuration of the snubber circuit connected to Q1 and Q2 is different from that of FIG. 1, and a diode DS1 and a capacitor CS are provided between the collector terminal and the emitter terminal of Q1.
1 is connected in series by a wiring having inductances L3 and L4. Incidentally, Ls1 is a parasitic inductance of the capacitor CS1. The resistor Rs1 is provided between the connection point of CS1 and DS1 and the emitter of Q2, and L7 is the resistor Rs.
This is the inductance of the wiring that connects 1 to each other. The snubber circuit of this configuration is of a clamp type, in which the snubber capacitor CS1 is always charged with the voltage of the main power supply VE, and the collector-emitter voltage Vce becomes equal to or higher than the voltage of the main power supply VE when Q1 is turned off. When increasing the current, the current is diverted to the snubber circuit, and the electromagnetic energy of the wiring is absorbed by CS1. The energy stored in CS1 is regenerated to the main power supply VE through the resistor Rs1. However, in this method, the voltage applied to Q1 is the sum of the voltage of CS1 charged to the voltage of VE, the spike voltage determined by the product of the change di / dt of the current flowing into the snubber circuit and the wiring inductance of the snubber circuit. Therefore, the voltage of Q1 becomes very high when the current is cut off, and conventionally, the current and the voltage might exceed the limit of the reverse bias safe operation area of the device. In this embodiment, the spike voltage is reduced so that di / dt is suppressed so that the maximum voltage when the current is cut off becomes equal to or lower than the value guaranteed in the safe operation area. Similarly, a diode DS2 and a capacitor CS2 are connected in series between the collector terminal and the emitter terminal of Q2 by wiring having inductances L4 and L5. Ls2 is a parasitic inductance of the capacitor CS2. Resistor Rs2 is DS1 and CS1
Is provided between the connection point of Q1 and the collector of Q1, and L8 is the inductance of the wiring connecting the resistor Rs2. still,
As a snubber current detecting means, a resistor Rd4 is provided between the emitter terminals of L4 and Q1 and between the emitter terminals of L5 and Q2.
Rd2 is connected to each other and the snubber current is detected by the resistance voltage. Since the gate drive circuits for Q1 and Q2 have the same configuration, only the drive circuit for Q2 will be described here. Vc1 and Vc2 are control power sources as in FIG. 1, and a switch means S3 and a resistance means Rg3 are connected in series between the gate terminal of Q2 and the positive electrode of Vc1.
3 is turned on when Q2 is turned on by the command Sin2 of the control means 2. Also, the gate terminal of Q2 and V
Switch means S1 and S2 and resistance means Rg1 are connected in series between the negative electrodes of c2, and resistance means Rg2 is connected in parallel to S1. S2 is Q2 in response to a command from the control means 2.
Is turned on when turning off, and S1 is the control means 2
ON / OFF is controlled by the output of the switching means 1 which changes according to the command Sin2 and the output (detection voltage) of the snubber current detection means. In this embodiment, di / dt is performed only for reducing the spike voltage at turn-off. The configuration of the switching means 1 is the same as that of the and circuit 4, the comparison means 6-1, and the predetermined voltage 7-1 provided for turning on and off S1 in FIG. As described above, the voltage of the resistor Rd2 provided between the emitter terminals of L5 and Q2 is detected, and Q
When the current that charges CS2 flows when turning off 2,
At the rising time, the voltage of Rd2 generates a positive voltage with the emitter terminal of Q2 as a reference potential. As in the case of FIG. 2, the switching means 1 turns off S1 when the signal of the off command Sin2 is applied from the control means 2 and the condition that the voltage of Rd2 is positive and equal to or more than a predetermined value is satisfied. On the contrary, when it is less than the predetermined value or is a negative voltage, S1 is turned on.

FIG. 5 shows operation waveforms of the embodiment shown in FIG. In FIG. 5, a collector-emitter voltage Vce of Q2, a current Ic flowing through Q2, and a snubber capacitor C
The relationship between the current Is flowing through S2, the detection voltage of the snubber current detection means (voltage of Rd2), and the gate resistance when off is shown. At the time of turn-off, S1 turns on according to the command Sin2 of the control means 2, but the voltage Vce of Q2 rises before the current Ic starts to decrease, and when it reaches the charging voltage VE of CS2, the decrease of Ic starts from that point. To be done. At this time, due to the electromagnetic energy accumulated in the main circuit wirings L1 and L2, the current is commutated to the snubber circuit, the snubber current starts to flow, the spike voltage Vcsp is applied to Q2, and then the voltage of Q2 is charged as CS2 is charged. Vce is the main power supply V
The voltage reaches a maximum value Vcm that exceeds the voltage of E by ΔV, and returns to the normal voltage of the main power supply VE with the disappearance of the snubber current Is. On the other hand, the voltage of Rd2 also rises to the detection voltage value proportional to the snubber current Is, as shown in FIG. If this voltage is equal to or higher than a predetermined value, S1 is turned off by the action of the switching means 1, and the gate resistances connecting the capacitor between the gate and emitter terminals of Q2 and the power supply Vc2 are Rg1 and Rg2.
It becomes the value of the sum of. If the resistance value of Rg2 is sufficiently larger than that of Rg1, the time constant with which the voltage charged in the capacitor between the gate and emitter terminals decreases decreases, and the gate voltage of Q2 decreases slowly. As a result, the decrease of Ic is suppressed and di / dt becomes small. Since the suppression of di / dt is performed only during the current falling period tf, the increase in switching loss can be suppressed to the necessary minimum. Also, I
In the process of decreasing c, a spike voltage Vcsp whose absolute value is the product of di / dt and the total inductance (L4 + Ls2 + L5) of the snubber circuit is generated.
By suppressing / dt, the spike voltage Vcsp is also reduced as shown in the figure, and it is possible to maintain low loss due to regeneration by returning the energy stored in CS2 to the main power supply VE. The snubber current Is is the electromagnetic energy of L1 and L2, which is C
The current flows during the period until it is absorbed by S2, but the waveform in FIG. 5 shows that the gate resistance is the sum of Rg1 and Rg2 during this period. However, the period in which di / dt needs to be suppressed is only the current falling period tf,
After the period of tf has passed, S1 may be returned to the ON state by the switching means 1. When S1 is returned to the ON state by the switching means 1, the gate resistance value returns to the low resistance of only Rg1, and the gate and emitter thereof are short-circuited with a low impedance so that Q2 is not erroneously ignited by external noise or the like.

As an embodiment of the present invention, the case where the power semiconductor element is an IGBT has been described. IGB
In a voltage-driven element such as T, since the control terminal has an electrostatic capacitance, the voltage at the time of discharging or charging the gate electrostatic capacitance (that is, the gate voltage) can be changed by switching the resistance. In the present invention, a current drive type element such as a bipolar transistor may be used instead of the voltage drive type element such as the IGBT. In a current drive type element such as a bipolar transistor, electric charges called carriers are present in a base layer provided with a control terminal, and a current change at switching (d
i / dt) changes. Taking the case of turn-off as an example, since the control current increases as the resistance value decreases due to the switching of the resistance, the charge accumulation amount decreases sharply, the main current is cut off faster, and di / dt increases. On the contrary, when the resistance value is large, the control current decreases, so that the charge accumulation amount decreases slowly, the main current is interrupted slowly, and di / dt decreases. Thereby, the same effect as when the IGBT is used can be obtained.

[0017]

As described in detail above, according to the present invention,
By detecting the current flowing through the snubber circuit when the power semiconductor element is turned on and off, the control voltage or control current of the power semiconductor element is changed from the time when the current flowing through the power semiconductor element decreases or increases, By suppressing di / dt during the period when the current decreases or increases, the increase in switching loss is suppressed to the necessary minimum, and the spike voltage is reduced to operate the device safely and the power semiconductor devices are connected in parallel. In this case, the current sharing can be made uniform to guarantee the operation of the device up to the full allowable current. Also, di / d
By suppressing t, it is possible to reduce the recovery current of the diode at the time of turn-on, reduce the electromagnetic energy of the wiring, and reduce the loss of the snubber circuit generated for absorbing this energy.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a drive device for a power semiconductor element showing an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a switching unit.

3 is an operation waveform chart for explaining the operation of the embodiment of FIG.

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

5 is an operation waveform diagram for explaining the operation of the embodiment of FIG.

[Explanation of symbols]

1 switching means 2 control means 3 load 4 and circuit 5 or circuit 6 comparison means 7 predetermined voltage Q1 to Q4 IGBT D1 to D4, Ds1, Ds2 diodes S1 to S4 switch means VE main power supply Vc1, Vc2 control power supply Rg1 to Rg4, Rs1 , Rs2, Rd1 to Rd4 Resistances CS1 and CS2 Capacitors Le1 to Le8, L1 to L8, Lc1 and Lc2 Wiring inductance Ls1 and Ls2 Capacitor parasitic inductance

Claims (7)

[Claims] 1. A power semiconductor device having first and second terminals for inputting and outputting a main current and a control gate terminal, and supplying or removing a control voltage or a control current to the control gate terminal according to an input signal. A drive device for a power semiconductor element, comprising drive circuit means for passing or shutting off the main current, wherein snubber circuit means is provided between the first and second terminals to supply or remove the control voltage or control current. A drive device for a power semiconductor element, characterized in that the control voltage or the control current is changed in accordance with a current flowing in the snubber circuit means during the period. 2. A power semiconductor device having first and second terminals for inputting and outputting a main current and a control gate terminal, and supplying or removing a control voltage or a control current to the control gate terminal according to an input signal. A drive device for a power semiconductor element, comprising drive circuit means, for flowing or interrupting the main current, wherein the snubber circuit means is connected between the first and second terminals, and the current flowing through the snubber circuit means is detected. Snubber current detection means is provided, and when the control voltage or control current is supplied or removed, the output of the snubber current detection means is detected, and the control is performed only during a period when the main current flowing through the power semiconductor element changes. A drive device for a power semiconductor element, which is characterized by changing a voltage or a control current. 3. An inverter comprising a bridge in which at least two power semiconductor elements are connected in series to a main power source, and a snubber circuit means connected between input / output terminals of each of the power semiconductor elements or at both ends of the bridge, In a drive device for a power semiconductor element having a drive circuit means for supplying or removing a control voltage or control current according to an input signal to a control gate terminal of each power semiconductor element, a period for supplying or removing the control voltage or control current In addition, the drive device of the power semiconductor element, characterized in that the control voltage or the control current is changed according to the current flowing through the snubber circuit means. 4. An inverter comprising a bridge in which at least two power semiconductor elements are connected in series to a main power source and a snubber circuit means connected between input / output terminals of each of the power semiconductor elements or both ends of the bridge, In a drive device for a power semiconductor element having a drive circuit means for supplying or removing a control voltage or a control current according to an input signal to a control gate terminal of each power semiconductor element, a snubber current detection for detecting a current flowing through the snubber circuit means. Means for detecting the output of the snubber current detecting means and changing the control voltage or the control current only during a period in which the main current flowing through the power semiconductor element changes. apparatus. 5. The bridge according to claim 3, wherein at least two power semiconductor elements are connected in series to the main power source, and at least one power semiconductor element is connected in parallel to each of the power semiconductor elements. A drive device for a power semiconductor element, which is characterized by: 6. The driving circuit means according to claim 1, further comprising a resistance means,
A driving device for a power semiconductor element, wherein a resistance value of the resistance means is changed according to a current flowing through the snubber circuit means. 7. The snubber circuit means according to claim 1, further comprising a diode and a capacitor connected in series between the first and second terminals (input / output terminals). A driving device for a power semiconductor element, wherein the capacitor is connected between electrodes of a main power source via a resistance means.